Abstract: A circuit includes a signal generating circuit that generates a pre-charge signal based on a clock signal and a column select signal for a column of memory cells associated with the signal generating circuit. A first state of the pre-charge signal depends on a first state of the column select signal, and the first state of the column select signal corresponds to selection of the column of memory cells. The circuit also includes a charge circuit associated with the signal generating circuit and a first data line coupled to the charge circuit. The charge circuit charges the first data line in response to the first state of the pre-charge signal and allows the first data line to float in response to a second state of the pre-charge signal.

Abstract: An object is to miniaturize a semiconductor device. Another object is to reduce the area of a driver circuit of a semiconductor device including a memory cell. The semiconductor device includes an element formation layer provided with at least a first semiconductor element, a first wiring provided over the element formation layer, an interlayer film provided over the first wiring, and a second wiring overlapping with the first wiring with the interlayer film provided therebetween. The first wiring, the interlayer film, and the second wiring are included in a second semiconductor element. The first wiring and the second wiring are wirings to which the same potentials are supplied.

Abstract: A memory cell including two transistors and one capacitor, which is known as a gain cell, is improved. One electrode of the capacitor is connected to a bit line, and the other electrode thereof is connected to a drain of a write transistor. A source of the write transistor is connected to a source line. As a result, for example, in the case where a stacked capacitor is used, the one electrode of the capacitor can be part of the bit line. Only one specific write transistor is turned on when a potential of the source line and a potential of the write bit line are set; thus, only one memory cell can be rewritten.

Abstract: There is provided a manufacturing method of a semiconductor device having an N-type semiconductor layer on a P-type semiconductor layer. The manufacturing method comprises: a dry etching process of performing dry etching to go through the N-type semiconductor layer in a thickness direction and make the plane in the thickness direction of the P-type semiconductor layer exposed; and a annealing process of annealing the P-type semiconductor layer in an atmosphere containing oxygen, after the dry etching process. This manufacturing method improves the electrical properties of the P-type semiconductor layer.

Abstract: A memory device having a plurality of banks of memory cells may be provided. Each memory cells may be interconnected via a local write bit-line and a complementary local write bit-line to a local write bit-line buffer circuit. The local write bit-line buffer circuit may be connected via a global write bit-line and a complementary one to a negative bias write assist circuit. The memory device may also comprise an address decoder separately connected to the local write bit-line buffer circuits. The address decoder may comprise a generating unit for enabling exactly one local write enable signal for a respective one of said local write bit-line buffer circuits. The local write bit-line buffer circuit may be adapted for generating local write data on said local write bit-line in response to receiving global write data on said global write bit-line when its local write enable signal is enabled.

Abstract: A memory device may include memory cells. The method may include receiving a request of reading a selected data word associated with a selected code word stored with an error correction code, and reading a first code word representing a first version of the selected code word by comparing a state of each selected memory cell with a first reference. The method may include verifying the first code word, setting the selected code word according to the first code word in response to a positive verification, reading at least one second code word representing a second version of the selected code word, verifying the second code word, and setting the selected code word according to the second code word in response to a negative verification of the first code word and to a positive verification of the second code word.

Abstract: A memory subsystem incorporating a die-stacked DRAM (DSDRAM) is disclosed. In one embodiment, a system include a processor implemented on a silicon interposer of an integrated circuit (IC) package, a DSDRAM coupled to the processor, the DSDRAM implemented on the silicon interposer of the IC package, and a DRAM implemented separately from the IC package. The DSDRAM and the DRAM form a main memory having a contiguous address space comprising a range of physical addresses. The physical addresses of the DSDRAM occupy a first contiguous portion of the address space, while the DRAM occupies a second contiguous portion of the address space. Each physical address of the contiguous address space is augmented with a first bit that, when set, indicates that a page is stored in the DRAM and the DSDRAM.

Abstract: A programmable feed forward equalizer (FFE) includes a plurality of unit cells, each unit cell comprising a capacitive element coupled to an input connection by a first switch and coupled to an output connection by a second switch. The FFE also comprises clock logic configured to control the first switch and the second switch so that a selected voltage signal is applied to the capacitive element at a selected time such that the selected voltage signal defines a capacitance of the capacitive element, the clock logic causing the second switch to couple the capacitive element to the output connection so as to apply the selected voltage signal as a filter coefficient to a summing element.

Abstract: Information handling system secret protection is enhanced by encrypting secrets into a common file and breaking up the encrypted file into plural portions stored at plural memory devices, such as across plural DIMMs disposed in the information handling system. In one embodiment, a decryption key to decrypt the encrypted file is broken into plural portions stored at the plural memory devices. Upon detection of a predetermined security factor, such as an indication of removal of a the encrypted file is removed from the plural portions.

Abstract: According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a voltage generation circuit, and control logic. The memory cell array includes a plurality of memory blocks on a substrate. Each of the memory blocks includes a plurality of strings connected between bit lines and a common source line. The address decoder is configured to measure impedance information of word lines of a selected memory block. The voltage generation circuit is configured to generate word line voltages to be applied to word lines, and at least one of the word line voltages includes an offset voltage and a target voltage. The control logic is configured to adjust a level of the offset voltage and the offset time depending on the measured impedance information of the word lines.

Abstract: Provided is a semiconductor device including first to fifth circuits. The first circuit includes first and second transistors. The second circuit is capable of supplying one of first and second wirings with a gradually changing potential. The third circuit is capable of supplying a predetermined potential to the other of the first and second wirings and is capable of reading data stored in the first circuit. The fourth circuit is capable of comparing first data to be written to the first circuit with second data read by the third circuit. When a comparison result obtained by the fourth circuit concludes that the first data is consistent with the second data, the fifth circuit disconnects the second circuit from the first circuit, and a potential of the one of the first and second wirings is supplied to a gate of the second transistor.

Abstract: A semiconductor device with reduced leakage current and a method of manufacturing these reduced leakage current semiconductor devices are disclosed. The reduced leakage current semiconductor devices may be used for both static circuits and dynamic circuits. The reduced leakage current semiconductor devices reduce leakage current in the device when the node is not transitioning which occurs more than 95% of the time.

Abstract: In one embodiment, a memory such as a dynamic random access memory employs charge boosting to bitcells prior to sensing charge levels in the storage nodes of the bitcells. It is believed that such an arrangement may be employed to improve bitcell read-out voltages, reduce refresh power consumption, improve restore voltage levels or other features, depending upon the particular application. Other aspects are described herein.

Abstract: Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.

Abstract: A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in chips or wafers to selectively screen out cells with low or high thermal stability factor. The coercivity (Hc) is used as a proxy for thermal stability factor (delta). In the various embodiments the sequence, direction and strength of the external magnetic fields is used to determine the high coercivity cells that are not switched by a normal field and the low coercivity cells that are switched by a selected low field. In some embodiment the MRAM's standard internal electric current can be used to switch the cells. Standard circuit-based resistance read operations can be used to determine the response of each cell to these magnetic fields and identify the abnormal high and low coercivity cells.

Abstract: A normally-off JFET is provided. The normally-off JFET includes a channel region of a first conductivity type, a floating semiconductor region of a second conductivity type adjoining the channel region, and a contact region of the first conductivity type adjoining the floating semiconductor region. The floating semiconductor region is arranged between the contact region and the channel region. Further, a normally-off semiconductor switch is provided.

Abstract: A semiconductor memory device in which capacitance of a capacitor is lower and integration degree is higher. A plurality of memory blocks is connected to one bit line BL_m. A memory block MB_n_m includes a sub bit line SBL_n_m, a write switch, and a plurality of memory cells. A sub bit line SBL_n+1_m adjacent to the sub bit line SBL_n_m is connected to an amplifier circuit AMP_n/n+1_m including two inverters and two selection switches. A circuit configuration of the amplifier circuit can be changed with the selection switches. The amplifier circuit is connected to the bit line BL_m through a read switch. Because of a sufficiently low capacitance of the sub bit line SBL_n_m, potential change due to electric charges of the capacitor in each memory cell can be amplified by the amplifier circuit AMP_n/n+1_m without an error, and the amplified data can be output to the bit line BL_m.

Abstract: The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.

Abstract: A semiconductor device which stores data by using a transistor whose leakage current between source and drain in an off state is small as a writing transistor. In a matrix including a plurality of memory cells in which a drain of the writing transistor is connected to a gate of a reading transistor and the drain of the writing transistor is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line; a source of the writing transistor is connected to a writing bit line; and a source and a drain of the reading transistor are connected to a reading bit line and a bias line. In order to reduce the number of wirings, the writing bit line or the bias line is substituted for the reading bit line in another column.

Abstract: Provided is a memory device having a plurality of memory cells and a refresh circuit. Each of the memory cells is configured to retain multiple data as a potential of a node connected to a gate of a first transistor, one of a source and a drain of a second transistor, and one of electrodes of a capacitor. The refresh circuit is configured to refresh the memory cells. That is, the refresh circuit is configured to determine an interval between refresh operations, estimate a change of the potential of the node due to the leakage of the charge, and provide a refresh potential to the memory cells, where the refresh potential is a sum of the potential read from the node and the potential lost due to the charge leakage.

Abstract: A nonvolatile memory device is provided. The nonvolatile memory device includes a memory cell array, an anti-fuse cell array, a sense amplifier, a page buffer, and a control logic. The memory cell array includes memory cells connected to word lines and bit lines. The anti-fuse cell array stores setting information for controlling the memory cell array. The anti-fuse cell array includes anti-fuse cells connected to the bit lines. The sense amplifier is connected to the bit lines to sense the memory cells or the anti-fuse cells. The page buffer stores data that is read out from the memory cells or the anti-fuse cells. The control logic controls the sense amplifiers and the page buffer to read out data from the memory cell array or the anti-fuse cell array.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell array including a first block that includes memory cells, a second memory cell array including a second block that includes memory cells, word lines arranged in the first and second memory cell arrays, and a row decoder including transfer gates that respectively transfer voltages to the word lines. Word lines arranged in the first block include first and second groups, word lines arranged in the second block include third and fourth groups, and the first and third groups commonly use the transfer gates.

Abstract: A tracking circuit in a memory macro includes a data line, a tracking cell electrically coupled with the data line, a logical gate, a feedback transistor, and a plurality of pulling devices. The logical gate has an input terminal and an output terminal. The input terminal of the logical gate is electrically coupled with the data line. The feedback transistor has a first terminal, a second terminal, and a gate terminal. The first terminal of the feedback transistor is electrically coupled with the data line, and the gate terminal of the feedback transistor is electrically coupled with the output terminal of the logical gate. The plurality of pulling devices is configured to pull the second terminal of the feedback transistor toward a first voltage.

Abstract: This disclosure provides a display device having a built-in touch input unit, the display device including: a lower substrate; an upper substrate; a plurality of first signal lines and second signal lines; touch cells that are formed in a plurality of areas, respectively including a conductive pad that forms an electrostatic capacity between a touch input means and the conductive pad when the touch input means approaches to the conductive pad within a predetermined distance (d) in each divided area, and at least a 3-terminal type switching element whose gate electrode is connected to the conductive pad; and a touch position detector that transmits and receives position detection signals to and from the first signal lines and the second signal lines, and detects whether output signals of the switching element are changed by capacitance that is formed between the touch input means and the conductive pad.

Abstract: A low-power programmable LSI that can perform configuration (dynamic configuration) at high speed and can quickly start is provided. The programmable LSI includes a plurality of logic elements and a memory element for storing configuration data to be input to the plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements in accordance with the configuration data stored in the configuration memory. The memory element is formed using a storage element including a transistor whose channel is formed in an oxide semiconductor layer and a node set in a floating state when the transistor is turned off.

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

Abstract: An SEU protection circuit comprises first and second storage means for receiving primary and redundant versions, respectively, of an n-bit wide data value that is to be corrected in case of an SEU occurrence; the correction circuit requires that the data value be a 1-hot encoded value. A parity engine performs a parity operation on the n bits of the primary data value. A multiplexer receives the primary and redundant data values and the parity engine output at respective inputs, and is arranged to pass the primary data value to an output when the parity engine output indicates ‘odd’ parity, and to pass the redundant data value to the output when the parity engine output indicates ‘even’ parity. The primary and redundant data values are suitably state variables, and the parity engine is preferably an n-bit wide XOR or XNOR gate.

Abstract: A semiconductor device includes a substrate with an active region defined by a device isolation layer. A word line extends over the active region in a first direction, and a plurality of interconnections extends over the word line in a second direction perpendicular to the first direction. A contact pad is disposed between and spaced apart from the word line and the plurality of interconnections, extending in the first direction to overlap the plurality of interconnections and the active region when viewed from a plan view. A lower contact plug electrically connects the contact pad to the active region. An upper contact plug electrically connects the contact pad to one of the plurality of interconnections.

Abstract: The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.

Abstract: In a memory device, memory capacity per unit area is increased while a period in which data is held is ensured. The memory device includes a driver circuit provided over a substrate, and a plurality of memory cell arrays which are provided over the driver circuit and driven by the driver circuit. Each of the plurality of memory cell arrays includes a plurality of memory cells. Each of the plurality of memory cells includes a first transistor including a first gate electrode overlapping with an oxide semiconductor layer, and a capacitor including a source electrode or a drain electrode, a first gate insulating layer, and a conductive layer. The plurality of memory cell arrays is stacked to overlap. Thus, in the memory device, memory capacity per unit area is increased while a period in which data is held is ensured.

Abstract: An arithmetic processing unit including an SRAM with low power consumption and performing backup and recovery operation with no burden on circuits. One embodiment is a memory device including a plurality of memory cells. The memory cells include inverters in which capacitors for backing up data are provided. When data of all the memory cells in a region is not rewritten after data is returned from the capacitors to the inverters, data in the region is not transferred from the inverters to the capacitors and the inverters are turned off. When data of at least one of the memory cells in the region is rewritten, data in the region is transferred from the inverters to the capacitors and then power of the inverters are turned off. In this manner, backup is selectively performed to reduce power consumption. Other embodiments are described and claimed.

Abstract: A system and method of writing data to a memory block includes receiving user data in a memory controller, the user data to be written to the memory block. The user data is first written to a buffer in the memory controller. A screening pattern is written to at least one screening column in the memory block and a first memory integrity test is performed. The first memory integrity test includes reading screening column data from the at least one screening column and comparing the screening column data read from the at least one screening column to the screening pattern. The user data is written to at least one user data column in the memory block when the screening column data read from the at least one screening column matches the screening pattern in the first memory integrity test.

Abstract: The circuit includes a first wiring for supplying a power supply potential to a signal processing circuit, a transistor for controlling electrical connection between the first wiring and a second wiring for supplying the a power supply potential, and a transistor for determining whether or not the first wiring is grounded. At least one of the two transistors is a transistor whose channel is formed in the oxide semiconductor layer. This makes it possible to reduce power consumption due to cutoff current of at least one of the two transistors.

Abstract: The semiconductor device includes a CPU core having functions of a control unit, an arithmetic unit, and a register; a first memory device including a plurality of blocks each including one or a plurality of rows of memory cells; a second memory device copying data that is to be treated in the CPU core from a first block selected by the CPU core from the plurality of blocks included in the first memory device, and storing the data; a plurality of switches controlling supply of power supply voltage to the respective blocks; a memory management unit recognizing an address of the first block; and a power controller turning off one of the plurality of switches using the address to stop supply of the power supply voltage to a second block of the plurality of blocks which is different from the first block.

Abstract: Rows of a memory array are segmented into a predetermined number of word line groups. Each row in a word line group has a word line disposed between parallel power supply lines. Each of the power supply lines in a row of a word line group is shared by an adjacent row in the word line group. A row on a boundary of a word line group has a power supply line shared by a row on a boundary of an adjacent word line group. All power supply lines in a word line group are at a full power voltage in response to one of the rows in the word line group being selected by a word line. Most power supply lines in an adjacent word line group are at a full power voltage. All power supply lines in other word line groups are at a power-gated voltage.

Abstract: Provided is a semiconductor device wherein chip size is reduced, while potential on the dummy word lines is fixed. The semiconductor device is provided with: a memory cell array including a plurality of memory cells, a plurality of word lines for controlling memory operations of the plurality of memory cells, and a plurality of dummy word lines that do not participate in memory operations of the plurality of memory cells; and a guard ring surrounding the memory cell array. The plurality of dummy word lines are electrically fixed to the guard ring.

Abstract: A memory circuit includes at least one first memory cell of a first memory array for storing a first datum. The at least one first memory cell is coupled with a first word line and a first bit line. A first bit line bar is disposed substantially parallel with the first bit line. A first switch is coupled between a sense amplifier and the first bit line bar. The first switch can electrically isolate the sense amplifier from the first bit line bar if the sense amplifier is capable of sensing a first voltage difference between the first bit line. The first bit line bar and the first voltage difference is substantially equal to or larger than a predetermined value.

Abstract: A resistive memory device includes a memory cell array, an input/output (I/O) sense amplifier unit, an address input buffer, a row decoder, and a column decoder. The memory cell array includes unit memory cells, and operates in response to a word line driving signal and a column selecting signal, each unit memory cell includes a resistive device and a compensation resistive device. The I/O sense amplifier unit amplifies data output from the memory cell array to generate first data, and transfers input data to the memory cell array. The address input buffer generates a row address signal and a column address signal based on an external address. The row decoder decodes the row address signal and generates the word line driving signal based on the decoded row address signal. The column decoder decodes the column address signal and generates the column selecting signal based on the decoded column address signal.

Abstract: Provided is a memory device with reduced overhead power. A memory device includes a first circuit retaining data in a first period during which a power supply voltage is supplied; a second circuit saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which the power supply voltage is not supplied; and a third circuit saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which the power supply voltage is not supplied. The third circuit includes a transistor in which a channel formation region is provided in an oxide semiconductor film and a capacitor to which a potential corresponding to the data is supplied through the transistor.

Abstract: A memory device biasing circuit is disclosed, the circuit having a pair of semiconductor devices coupled to receive a supply voltage having a supply voltage level suitable for operating a memory device in an active mode and operable for providing an adjustable biased voltage to the memory device that is greater than a minimal voltage level for operating the memory device in a data retention mode. The pair of semiconductor devices includes a first semiconductor device; and, a second semiconductor device that includes an opposite type of semiconductor device than the first semiconductor device such that the pair of semiconductor devices includes each of an N-type semiconductor device and a P-type semiconductor device. The memory device biasing circuit further includes a bias adjustment circuit coupled to the second semiconductor device and configured to adjust the operation of the second semiconductor device based on the supply voltage.

Abstract: Nonvolatile memory devices including three transistor unit cells are provided. The nonvolatile memory device includes a selection transistor having a first terminal and a second terminal, a first charge trap transistor electrically connected in series to the first terminal of the selection transistor, a second charge trap transistor electrically connected in series to the second terminal of the selection transistor, and a word line electrically connected to gate electrodes of the selection transistor, the first charge trap transistor and the second charge trap transistor. Related methods are also provided.

Abstract: A method is performed on a silicon-on-insulator (SOI) wafer formed of a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, where the active silicon layer has a surface opposite the bottom oxide layer. The method includes forming a first mask over the surface at a first portion of the wafer and leaving a second portion of the wafer unmasked, etching the wafer at the unmasked second portion of the wafer to form a depression in the active silicon layer, the depression having a bottom, forming a thermal oxide layer substantially filling the depression, removing the first mask, and forming fins at the first and second portions of the wafer.

Abstract: A method with a circuit that includes a memory (130) coupled to an analog line coverage circuit (104). The analog line coverage circuit includes a plurality of buffers (151-154) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (161-164) in which each bin cell is coupled to a buffer, a multiplexer (170), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter (180) coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor (102), coupled to the memory and to the analog line coverage circuit, enables the analog line coverage circuit when the processor is in a debug mode.

Abstract: The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an active region defined by a device isolation layer formed in a cell region, a transistor including a buried gate in the active region, a metal contact formed on the active region positioned at one side of the buried gate, a landing pad on the metal contact, a capacitor on the landing pad and electrically connected to the active region, and a metal oxide layer between the metal contact and the active region.

Abstract: According to one aspect of the invention, a contact detecting device includes: a contact responding section configured to produce an electric change in response to an object to be detected coming into contact with or proximity to a detecting surface; and a contact driving scanning section configured to scan application of driving voltage to the contact responding section in one direction within the detecting surface, and control output of the electric change in time series, wherein the contact driving scanning section performs a plurality of scans of different regions of the contact responding section in parallel with each other, and outputs a plurality of the electric changes in parallel with each other.

Abstract: The first circuit has a function of retaining data in a first period during which a power supply voltage is supplied. The second circuit has functions of saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which application of the power supply voltage is stopped. The third circuit has functions of saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which application of the power supply voltage is stopped. The second circuit is capable of being written with the data for a shorter time than the third circuit. The third circuit is capable of maintaining the data for a longer time than the second circuit.

Abstract: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. Random access memories with a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for DRAM and NVM devices.

Abstract: A semiconductor device comprises a memory cell, a bit line, a sense amplifier operating between a first voltage and a second voltage higher than the first voltage, a transfer control circuit including a transfer transistor, and a write circuit writing data into the memory cell through the bit line based on the first voltage and a third voltage. The sense amplifier receives and amplifiers the signal voltage at a sense node when the transfer transistor controls the connection between the bit line and the sense node in response to a transfer control voltage. The third voltage is set to a voltage lower than the second voltage and higher than the transfer control voltage, and the sense node is set to a voltage higher than the transfer control voltage in an initial period of a read operation before the data of the memory cell is read out to the bit line.