Abstract: Provided is a semiconductor device which can generate a new test pattern even after design and have a reduced footprint of a circuit not used in normal operation. The semiconductor device includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a memory circuit that stores data and a plurality of circuits that make a signal for an operation test of the second integrated circuit. The signal is made when the continuity between the plurality of circuits is controlled by the memory circuit according to the data. In the second integrated circuit, the memory circuit is used as a buffer memory device after the operation test is conducted according to the signal.

Abstract: Methods and apparatus for identifying a process corner are provided. Provided is an exemplary method for identifying a process corner of an integrated circuit (IC). The IC has a first asymmetrical ring oscillator (ARO1) including pull-up transistors that have a low threshold voltage (LVT) and pull-down transistors that have a regular threshold voltage (RVT), and has a second asymmetrical ring oscillator (ARO2) including pull-up transistors that have an RVT and pull-down transistors having an LVT. The exemplary method includes applying an ultra-low power supply voltage to the ARO1 and the ARO2 that causes the integrated circuit to operate near a verge of malfunction, measuring an output frequency of the ARO1, measuring an output frequency of the ARO2, calculating a calculated ratio of the output frequency of the ARO1 and the output frequency of the ARO2, and comparing the calculated ratio to a fiduciary ratio to identify the process corner.

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

Abstract: A self-tracked bistable latch cell includes a cross-coupled latch, and two programmable transistors. The cross-coupled latch has a first data terminal, a second data terminal, a first voltage input terminal for receiving a latch control signal, and a second voltage input terminal for receiving a reference voltage. The first programmable transistor has a first terminal for outputting a first bit, a second terminal coupled to the first data terminal of the cross-coupled latch, and a control terminal for receiving a track control signal. The second programmable transistor has a first terminal for outputting a second bit, a second terminal coupled to the second data terminal of the cross-coupled latch, and a control terminal for receiving the track control signal. The gate oxide of both the first and the second programmable transistor are thinner than the gate oxide of the transistor of the cross-coupled latch.

Abstract: Provided are a method and an apparatus for controlling a register of a reconfigurable processor. The power of a register may be efficiently used by obtaining a command for each of a plurality of read ports of the register from a memory, obtaining activation information for each of the plurality of read ports from the obtained command, and determining an address value of each of the plurality of read ports on the basis of the obtained activation information.

Abstract: A static random access memory (SRAM) includes a bit cell that receives an operating voltage and a reference voltage, and includes a p-type pass gate. A bit information path is connected to the bit cell by the p-type pass gate, and a pre-discharge circuit is connected to the bit information path. The pre-discharge circuit includes an n-type transistor that discharges the bit information path to the reference voltage.

Abstract: An integrated circuit structure includes an SRAM array including a first sub-array having a first plurality of rows and a plurality of columns of SRAM cells, and a second sub-array having a second plurality of rows and the plurality of columns of SRAM cells. A first bit-line and a first complementary bit-line are connected to the first and the second pass-gate MOS devices of SRAM cells in a column in the first sub-array. A second bit-line and a second complementary bit-line are connected to the first and the second pass-gate MOS devices of SRAM cells in the column in the second sub-array. The first bit-line and the first complementary bit-line are disconnected from the second bit-line and the second complementary bit-line. A sense amplifier circuit is electrically coupled to, and configured to sense, the first bit-line, the first complementary bit-line, the second bit-line, and the second complementary bit-line.

Abstract: A memory circuit memory circuit comprises at least one memory cell for storing a datum. The memory cell is coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line. A first conductive layer comprising a first landing pad and a second landing pad is arranged at a first level. A second conductive layer is coupled to the first conductive layer and arranged at a second level different from the first level. The second conductive layer is routed to define the first voltage line and the second voltage line. A third conductive layer is coupled to the second conductive layer and arranged at a third level different from the first level and the second level. The third conductive layer is routed to define the word line.

Abstract: A word-line enable pulse generator for a SRAM is provided. The word-line enable pulse generator includes a delay unit. The delay unit is configured to delay a word-line enable pulse signal to be provided to a plurality of word line drivers of the SRAM. The delay unit includes a first transistor coupled between the plurality of word line drivers of the SRAM and a first power source, a resistance unit coupled between the first transistor and a second power source that is different from the first power source, and a second transistor coupled between the first transistor and the resistance unit. The first transistor has a gate for receiving an enable signal. The second transistor has a gate for receiving the enable signal. An edge of the word-line enable pulse signal is delayed from the enable signal by a delay time corresponding to a resistance of the resistance unit.

Abstract: A memory controlling device includes: a control circuit arranged to generate a multi-pulse control signal with a first duration; and a memory cell coupled to a pair of bit lines and a word line, wherein the multi-pulse control signal is coupled to the word line, and the memory cell is arranged to output an output signal on the pair of bit lines during the first duration.

Abstract: The present invention provides a memory cell. The memory cell includes a static random access memory (SRAM) cell located on a substrate. The SRAM cell includes a first storage node. At least one tunneling field-effect transistor (TFET), the gate of the tunneling field-effect transistor is electrically connected to the first storage node of the SRAM cell. A read bit line (RBL) electrically connected the drain of the TFET. A read terminal which is connected to a read port voltage (Vrp) and electrically connects to a source of the TFET.

Abstract: An autocorrective writing to a multiport static random access memory device is performed on at least one multiport static random access memory cell circuit. A first datum is written to the multiport static random access memory cell circuit and a second datum stored in the circuit is read from the multiport static random access memory cell subsequent to writing. The first and second data are compared. In response to the results of that comparison, an operation to rewriting the first datum to the circuit along with application of a write assist mechanism is selectively performed.

Abstract: The standby leakage current reduction schemes for digital data storing components are disclosed. By floating the low digital voltage node of the digital data storing components in standby mode, the major standby leakage current paths to the ground voltage caused by the channel diffusion leakage current of MOSFET devices can be terminated. The standby leakage currents will be reduced to the small reverse junction leakage currents to the grounded substrate. For retaining the stored data in the digital data storing components in standby mode, the low digital voltage node is connected to the ground voltage periodically according to a plurality of rectangular voltage pulses outputted from a pulse generator trigged by a low frequency clock oscillator. Due to no external voltage bias to the low digital voltage node other than floating the digital low voltage node, the data recovering process is instant.

Abstract: A static random access memory (SRAM) comprises a plurality of memory cells each having a pair of cross-coupled inverters, a first of the inverters being supplied by first and second power supply rails and a second of the inverters being supplied by third and fourth supply rails, an input of the second inverter being coupled to a first bit line via a first transistor; and a power supply circuit adapted to apply a first voltage difference across the first and second power supply rails and a second voltage difference across the third and fourth power supply rails, the second voltage difference being greater than the first voltage difference.

Abstract: A static random access memory cell includes a controlling signal line unit, a latch and an access transistor unit. The first bottom transistor unit is controlled by the controlling signal line unit to change voltage levels of the first pseudo node and the second pseudo node. The second bottom transistor unit is controlled by the first internal node to perform connection and disconnection between the controlling signal line unit and the second pseudo node, and the second bottom transistor unit is controlled by the second internal node to perform connection and disconnection between the controlling signal line unit and the first pseudo node. The access transistor unit is controlled by the controlling signal line unit to perform connection and disconnection between the controlling signal line unit, the first pseudo node and the second pseudo node.

Abstract: The memory cell of static random access memory based on resistance-capacitance reinforcement, which comprises a latch circuit and a bit selection circuit, the latch circuit consists of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, a first resistance-capacitance network and a second resistance-capacitance network; the bit selection circuit consists of NMOS transistors N5 and N6; the latch circuit forms four storage nodes X1, X1B, X2, X2B, among which a coupling capacitor C is provided between a pair of complementary data storage nodes. Compared to the conventional memory cell of 6T structure, a resistance-capacitance network and a coupling capacitor are added, so that without changing the original read operation circuit and without obviously increasing complexity, the memory cell is prevented from having single event upset merely at a cost of increasing a small amount of area, thus ensuring correctness of data.

Abstract: A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.

Abstract: A semiconductor device includes a SRAM circuit. The SRAM circuit includes: a memory array having a plurality of memory cells arranged in a matrix; a ground interconnection commonly connected to each of the memory cells; and a first potential control circuit for controlling a potential of the ground interconnection depending on an operation mode. The first potential control circuit includes a first NMOS transistor and a first PMOS transistor connected in parallel to each other between a ground node providing a ground potential and the ground interconnection.

Abstract: A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC) programming is still possible in addition to programming according to the number of bits per cell that the memory is designed for. Multiple SLC programming steps can be used to modify the number of states for certain memory cells by the memory controller.

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.

Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

Abstract: An Integrated Circuit (IC) includes a memory, circuit interconnections and control logic. The memory includes multiple standard-library Static Random Access Memory (SRAM) cells disposed on a substrate of the IC in multiple first layers, so that access to a respective SRAM cell to read and write data is through a cell-interface. The circuit interconnections, fabricated in one or more second layers separate from the first layers, interconnect cell-interfaces of a subgroup of the SRAM cells to form a ring oscillator that includes a cascade of N stages defined by the interconnected SRAM cells. The control logic is coupled to the cell-interfaces via the circuit interconnections, and is configured to apply an input signal to one or more of the cell-interfaces so as to trigger an oscillation of the ring oscillator whose frequency of oscillation is indicative of a speed of the SRAM cells of the memory.

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Abstract: A sensor for locating metallic or magnetizable objects comprises two emission coils and a receiving coil which are inductively interconnected. A method for determining the influence of temperature on the sensor includes supplying a first pair of predetermined alternating currents to the emitter coils, and simultaneously sampling current flows which pass through the emitter coils and a first current of the receiver coil. Subsequently, the method includes supplying a second pair of predetermined alternating currents to the emitter coils, and simultaneously sampling current flows which pass through the emitter coils and a second current of the receiver coil. The method further includes determining coupling factors between the emitter coils and the receiver coils based on the determined current flows and voltages, and determining the object based on the coupling factors.

Abstract: A semiconductor memory device including: a first transistor connected between a first node and ground, the first transistor having a gate connected to a second node; a second transistor connected between the second node and ground, the second transistor having a gate connected to the first node; a third transistor connected between first and third nodes, the third transistor having a gate connected to the second node; a fourth transistor connected between second and fourth nodes, the fourth transistor having a gate connected to the first node; a fifth transistor connected between the first node and bit line, the fifth transistor having a gate connected to a word line; a sixth transistor connected between the second node and complementary bit line, the sixth transistor having a gate connected to the word line; and a circuit to reduce a gate-source voltage of the third or fourth transistor in a write operation.

Abstract: An SRAM cell includes first through fifth active regions. The first through fourth active regions comprise channel regions and source/drain (S/D) regions of first through fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors. The SRAM cell further includes first through sixth gates configured to engage the channel regions of the first through sixth transistors. The first and second gates are electrically connected. The third and fourth gates are electrically connected. The SRAM cell further includes first conductive features that electrically connect one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, and the third gate. The SRAM cell further includes second conductive features that electrically connect the second gate, one of the S/D regions of the third transistor, one of the S/D regions of the fourth transistor, and the fifth gate.

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

Abstract: A semiconductor device includes a flip-flop circuit, a control line, a first P-type transistor and a first non-volatile storage element, and a second P-type transistor and a second non-volatile storage element. The flip-flop circuit has a circular structure in which a first inverter circuit, a first connection line including a first node, a second inverter circuit, and a second connection line including a second node are coupled in order. The first P-type transistor and the first non-volatile storage element are coupled together in series between the first node and the control line. The second P-type transistor and the second non-volatile storage element are coupled together in series between the second node and the control line. The non-volatile storage element is a magnetic tunnel junction element including a pinned layer, a tunnel barrier layer, and a free layer arranged in order from a position close to the control line.

Abstract: A semiconductor device can include a voltage detector circuit configured to generate a first potential that is essentially proportional to a first power supply potential and to provide a first and second voltage window signal by comparing the first potential to a first and second reference potential. The voltage window signals indicate voltage windows in which the first power supply potential is located. An assist control circuit receives the voltage window signals and provides at least one assist signal which can alter read or write operations to a static random access memory cell.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing signed element compare operations. An apparatus can include a first group of memory cells coupled to a sense line and to a number of first access lines. The apparatus can include a second group of memory cells coupled to the sense line and to a number of second access lines. The apparatus can include a controller configured to operate sensing circuitry to perform a number of operations to compare a value of a first signed element stored in the first group of memory cells to a value of a second signed element stored in the second group of memory cells.

Abstract: In some implementations, a method of fabricating an integrated circuit includes obtaining first data for a first chip containing a first version of the integrated circuit, determining that a transistor should be coupled with another transistor, selecting one or more masks for coupling the transistor with the other transistor to adjust the threshold voltage of the transistor, obtaining second data for a second chip containing a second version of the integrated circuit, determining that the second version of the integrated circuit meets one or more requirements, and preparing a final integrated circuit design for production based on the second version of the integrated circuit.

Abstract: A write-assist cell includes a first pull-up transistor electrically coupled to a voltage array and a first node, a first pass-gate transistor electrically coupled to the first node, and a bit-line electrically coupled to the first pass-gate transistor and a pull-down voltage. The first pass-gate is configured to selectively couple the bit-line to the first node. The pull-down voltage is configured to adjust a voltage of the voltage array from a first voltage to a second voltage when the bit-line is coupled to the first node.

Abstract: Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of positive bitline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).

Abstract: Provided is a local bit line-sharing memory device, including a plurality of memory cells that share a local bit line pair; a pre-charging unit that is connected to a write bit line pair and pre-charges the local bit line pair; and a data reading unit that reads data when bit line voltage pre-charged in a memory cell selected from the memory cells is discharged.

Abstract: A Static Random Access Memory (SRAM) Cell includes a first gate electrode layer covering a channel region of a read pull-down transistor, a second gate electrode layer covering channel regions of a first pull-down transistor and a first pull-up transistor, a third gate electrode layer covering a channel region of a second pass-gate transistor, a fourth gate electrode layer covering a channel region of a read pass-gate transistor, a fifth gate electrode layer covering a channel region of a first pass-gate transistor, and a sixth gate electrode layer covering channel regions of a second pull-down transistor and a second pull-up transistor. The first and second gate electrode layers are separated from each other by a first dielectric layer interposed therebetween, and are electrically connected to each other by a first interconnection layer formed thereon.

Abstract: A method of operating a semiconductor device that is powered by a first power supply potential can include detecting a change in at least one voltage window signal, the voltage window signal indicates a predetermined voltage window in which a potential of the first power supply potential is located; latching the at least one voltage window signal to provide at least one latched voltage window signal; and generating at least one assist signal in response to at least one latched voltage window signal; wherein the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell as compared to operations without the assist signal.

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

Abstract: An arithmetic processing block in which two inputs are provided for a multiplier, the block also including a pre-adder for combining the inputs to provide an additional option for a multiplier input.

Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.

Abstract: A system for dual mode operation having power saving and active modes in a stacked circuit topology having logic preservation is provided. The system includes a pre-charge circuit and a sleep mode control circuit for providing a signal to disable a plurality of circuit elements and switching a mode of the system, the sleep mode control circuit being coupled to the pre-charge circuit and further being coupled to a logic function circuit, wherein the plurality of circuit elements comprise logic gates and transistor devices. The system also includes a keeper circuit coupled to the global bitline, and the logic function circuit coupled to a solar bitline, wherein the logic function circuit preserves a state of the solar bitline, the state of the global bitline determines the state of the solar bitline. The system includes an effective pull-up transistor coupled to the sleep mode control circuit and the logic function circuit.

Abstract: The present disclosure includes apparatuses and methods related to accessing data in memory. One example method comprises storing data associated with a first operation in a first sense amplifier responsive to receiving a request to perform a second operation, and performing the second operation associated with a row of memory cells while the data associated with the first operation is being stored in the first sense amplifier.

Abstract: The memory device includes a first transistor and a circuit. The circuit includes a second to a (2n+1)th transistor, a first to an n-th capacitor, a first wiring, and a first to an n-th retention node (n is an integer greater than or equal to 2). When n is 2, a memory cell MC[1] includes a transistor ROS[1], a transistor WOS[1], and a capacitor C[1] and a memory cell MC[2] includes a transistor ROS[2], a transistor WOS[2], and a capacitor C[2]. A back gate of the transistor WOS[1] and a back gate of the transistor WOS[2] are electrically connected to a wiring WBG. A bake gate of a first transistor, a back gate of the transistor ROS[1], and a back gate of the transistor ROS[2] are electrically connected to a wiring RBG.

Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: A method includes: examining, by a test engine, whether a first bit of a memory array is functional; in response to the first bit being not functional, storing, by the test engine, address information of the first bit into a memory device; and retrieving, by an assist circuit trimming (ACT) circuit, the address information of the first bit from the memory device to selectively activate at least a first one of a plurality of assist circuits associated with the first bit.

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include lower wires, upper wires crossing the lower wires, select elements provided at intersections between the lower and upper wires, and memory elements provided between the select elements and the upper wires. Each of the memory elements may include a lower electrode having a top width greater than a bottom width, and a data storage layer including a plurality of magnetic layers stacked on a top surface of the lower electrode and having a rounded edge.

Abstract: A memory device includes: memory cells arranged in rows and columns; and regulated ground circuits corresponding to the columns. Each regulated ground circuit includes: a column ground node; at least three low-side voltage sources; at least three switches, each of the at least three switches being coupled between the column ground node and a corresponding one of the at least three voltage sources; and each of the at least three switches being controlled by a corresponding one of different control signals; Each memory cell includes: a high-side voltage source; an internal ground node coupled to the column ground node; and a cross latch having output and output_bar nodes. The cross latch is coupled between the high-side voltage source and the internal ground node, and is configured to selectively connect the output and output_bar nodes to corresponding bit and bit_bar lines.

Abstract: In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.

Abstract: An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells.