Abstract: A method of programming a nonvolatile memory cell. The nonvolatile memory cell includes a diode steering element in series with a carbon storage element The method includes providing a first voltage to the nonvolatile memory cell. The first voltage reverse biases the diode steering element. The carbon storage element sets to a lower resistivity state.

Abstract: A data read/write device according to an example of the present invention includes a recording layer, and means for applying a voltage to the recording layer, generating a resistance change in the recording layer, and recording data. The recording layer is composed of a composite compound having at least two types of cation elements, at least one type of the cation element is a transition element having a “d” orbit in which electrons have been incompletely filled, and the shortest distance between the adjacent cation elements is 0.32 nm or less.

Abstract: A memory includes conductive layers provided to extend along the word lines, memory cells each including a diode having a cathode connected to the conductive layer and a source line reading data stored in the memory cells, wherein either the conductive layers or the bit lines are in floating states in a standby time.

Abstract: A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.

Abstract: In the present resistive memory array, included are a substrate, a plurality of source regions in the substrate, and a conductor connecting the plurality of source regions, the conductor being positioned adjacent to the substrate to form, with the plurality of source regions, a common source. In one embodiment, the conductor is an elongated metal body of T-shaped cross-section. In another embodiment, the conductor is a plate-like metal body.

Abstract: A resistance-change random access memory device includes a resistance-change memory cell array having a plurality of resistance-change memory cells, where a plurality of word lines are connected to respective first terminals of the plurality of resistance-change memory cells. A plurality of bit lines are disposed perpendicular to the word lines and connected to respective second terminals of the plurality of resistance-change memory cells. The device also includes a plurality of discharge elements that are capable of connecting or disconnecting respective bit lines from a discharge voltage, where the discharge elements connect the respective bit lines to the discharge voltage before write and read operations.

Abstract: A memory device includes a memory unit comprising a substrate supporting mobile charge carriers. Insulative features formed on the substrate surface define first and second substrate areas on either side of the insulative features areas being connected by an elongate channel defined by the insulative features. The memory unit is switchable between first and second states in which the channel respectively provides a first conductance and a second, different conductance between the first and second areas at a predetermined potential difference between said first and second. A write circuit is arranged to apply a first potential difference across the first and second areas for changing the memory unit to the first state, and a second, different potential difference for changing the memory unit to the second state. A read circuit is arranged to apply the predetermined potential difference across the first and second areas for reading the state.

Abstract: A method of programming a nonvolatile memory device includes (i) providing a nonvolatile memory cell comprising a diode in series with at least one metal oxide, (ii) applying a first forward bias to change a resistivity state of the metal oxide from a first state to a second state; (iii) applying a second forward bias to change a resistivity state of the metal oxide from a second state to a third state; and (iv) applying a third forward bias to change a resistivity state of the metal oxide from a third state to a fourth state. The fourth resistivity state is higher than the third resistivity state, the third resistivity state is lower than the second resistivity state, and the second resistivity state is lower than the first resistivity state.

Abstract: A method of programming a nonvolatile memory array including a plurality of nonvolatile memory cells, a plurality of bit lines, and a plurality of word lines, wherein each memory cell comprises a diode, or a diode and a resistivity switching element is disclosed. The method includes both bias programming the memory cells of the device.

Abstract: A storage node may include a bottom electrode contact layer, a phase change layer connected to the bottom electrode contact layer, and a top electrode layer connected to the phase change layer. The bottom electrode contact layer may protrude toward the phase change layer. A phase change memory device may include a switching device and the storage node. The switching device may be connected to the bottom electrode contact layer. A method of manufacturing the storage node may include forming a via hole in an insulating interlayer, at least partially filling the via hole to form a bottom electrode contact layer, protruding the bottom electrode contact layer from the via hole, and forming a phase change layer that covers the bottom electrode contact layer. A method of manufacturing a phase change memory device may include forming the switching device on a substrate and manufacturing the storage node.

Abstract: A multi-layer, phase change material (PCM) memory apparatus includes a plurality of semiconductor layers sequentially formed over a base substrate, wherein each layer comprises an array of memory cells formed therein, each memory cell further including a PCM element, a first diode serving as a heater diode in thermal proximity to the PCM element and configured to program the PCM element to one of a low resistance crystalline state and a high resistance amorphous state, and a second diode serving a sense diode for a current path used in reading the state of the PCM element; the base substrate further including decoding, programming and sensing circuitry formed therein, with each of the plurality of semiconductor layers spaced by an insulating layer; and intralayer wiring for communication between the base substrate circuitry and the array of memory cells in each of the semiconductor layers.

Abstract: A metal-insulator diode is disclosed. In one aspect, the metal-insulator diode comprises a first electrode comprising a first metal, a first region comprising a first insulating material, a second region comprising a second insulating material, and a second electrode comprising a second metal. The first region and the second region reside between the first electrode and the second electrode. The second insulating material is doped with nitrogen. Note that the second insulating material may have an interface with either the first electrode or the second electrode.

Abstract: A method for fabrication and a structure of a self-aligned (crosspoint) memory device comprises lines (wires) in a first direction and in a second direction. The wires in the first direction are formed using a hard mask material that is resistant to the pre-selected etch processes used for creation of the lines in both the first and the second direction. Consequently, the hard mask material for the lines in the first direction form part of the memory stack.

Abstract: A nonvolatile memory device may include a memory cell array having a plurality of nonvolatile memory cells arranged in a matrix including a plurality of rows of the nonvolatile memory cells. Each of a plurality of word lines may be coupled with nonvolatile memory cells of a respective row of the matrix. A row decoder may be coupled to the plurality of word lines with the row decoder being configured to disable at least one of the word lines using a row bias having a level that is adjusted responsive to changes in temperature. Such a nonvolatile memory device may operate with reduced standby currents.

Abstract: An anti-fuse memory device includes a plurality of word lines, a plurality of bit lines, and a memory cell provided with respect to an intersecting portion of any of the plurality of word lines and any of the plurality of bit lines. Memory cell includes a PIN diode and an anti-fuse. An anode of the PIN diode is electrically connected to any of the bit lines. A cathode of the PIN diode is electrically connected to a first terminal of the anti-fuse. A second terminal of the anti-fuse is electrically connected to any of the word lines. The anti-fuse includes a silicon layer and an insulating layer which are interposed between electrodes.

Abstract: Provided is a non-volatile memory device that may include a plurality of variable resistors, each of the variable resistors having first and second terminals, the plurality of variable resistors arranged as a first layer of a plurality of layers and having data storage capability, at least one common bit plane arranged as a second layer of the plurality of layers and coupled to the first terminal of each of the variable resistors of the first layer, and a plurality of bit lines coupled to the second terminal of each of the variable resistors of the first layer.

Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Each memory cell comprises a diode and a plurality of memory elements each comprising one or more metal-oxygen compounds, the diode and the plurality of memory elements arranged in electrical series along a current path between a corresponding word line and a corresponding bit line.

Abstract: A memory includes a programmable resistance array and unipolar MOS peripheral circuitry. The peripheral circuitry includes address decoding circuitry. Because unipolar MOS circuitry is employed, the number of mask steps and, concomitantly, the cost of the programmable resistance memory may be minimized.

Abstract: A memory integrated circuit has memory arrays that are vertically layered. These memory arrays include word lines and bit lines. Intersections between the word lines and the bit lines include a diode and a memory state storage element. The diode and the memory storage element are connected in between a word line and a bit line. The diode at the intersections includes a first diode node and a second diode node. Various aspects of the memory integrated circuit are electrically interconnected in various ways, such as corresponding word lines, corresponding first diode nodes, or corresponding second diode nodes of different memory arrays being electrically interconnected. Various aspects of the memory integrated circuit are isolated in various ways, such as word lines, first diode nodes, or second diode nodes of different memory arrays being isolated.

Abstract: Memory cells (MC) are formed at intersections of bit lines (BL) extending in the X direction and word lines (WL) extending in the Y direction. A plurality of basic array planes sharing the word lines (WL), each formed for a group of bit lines (BL) aligned in the Z direction, are arranged side by side in the Y direction. In each basic array plane, bit lines in even layers and bit lines in odd layers are individually connected in common. Each of selection switch elements (101 to 104) controls switching of electrical connection/non-connection between the common-connected even layer bit line and a global bit line (GBL), and each of selection switch elements (111 to 114) control switching of connection/non-connection between the common-connected odd layer bit line and the global bit line (GBL).

Abstract: A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a first diode portion, a second diode portion and an antifuse separating the first diode portion from the second diode portion, and forming a second electrode over the at least one nonvolatile memory cell.

Abstract: A thermally programmable memory has a programmable element (20) of a thermally programmable resistance preferably of phase change material, material and a blown antifuse (80) located adjacent to the programmable material. Such a blown antifuse has a dielectric layer (100) surrounded by conductive layers (90, 110) to enable a brief high voltage to be applied across the dielectric to blow a small hole in the dielectric during manufacture to form a small conductive path which can be used as a tiny electrical heater for programming the material. Due to the current confinement by the hole, the volume of the material that must be heated in order to switch to a highly-resistive state is very small. As a result the programming power can be low.

Abstract: An object of the present invention is to provide nonvolatile, rewritable, easily-manufactured, and inexpensive storage element, storage device, and semiconductor device, which are superior in switching characteristics and which has low operation voltage. In an element including a first conductive layer, a second conductive layer facing the first conductive layer, and a layer containing at least one kind of an organic compound provided between the first conductive layer and the second conductive layer, the organic compound can be electrochemically doped or dedoped. By feeding current in this element, the organic compound provided between the conductive layers is electrochemically doped, i.e., electrons are transported, whereby the conductivity can be increased by about three to ten digits.

Abstract: A memory cell embodiment includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. A charge representative of a memory state of the memory cell is held across the intrinsic region of the diode.

Abstract: An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.

Abstract: Provided are a phase change random access memory (PRAM), a method of fabricating the PRAM, and a method of operating the PRAM. The PRAM may include a gate electrode configured to temporarily increase an electrical resistance of the lower electrode contact layer if a voltage is applied to the gate electrode, and around the lower electrode contact layer between a switching device and a phase change layer. A spacer insulating layer is disposed between the lower electrode contact layer and the gate electrode.

Abstract: One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the non-addressed columns or rows of the array, respectively, also becomes very large. While the leakage current through any one non-addressed diode on the selected row or column will have little impact on the operation of the device, the cumulative leakage through multiple thousands of non-addressed diodes can become significant. This aggregate leakage current can become great enough that the output voltage can be shifted such that the threshold for distinguishing between a one state and a zero state of the addressed diode location can become obscured and can result in a misreading of the addressed diode location. The present invention is a means to manage the leakage currents in a diode array storage device.

Abstract: A memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.

Abstract: A cross point memory cell includes a portion of a first distributed diode, a portion of a second distributed diode, a memory layer located between the portion of the first distributed diode and the portion of a second distributed diode, a bit line electrically connected to the first distributed diode, and a word line electrically connected to the second distributed diode.

Abstract: A nonvolatile memory cell including at least two two-terminal non-linear steering elements arranged in series, and a resistivity switching storage element arranged in series with the at least two two-terminal non-linear steering elements. A memory array, comprising a plurality of the nonvolatile memory cells is also described. A method of forming a nonvolatile memory cell is also described.

Abstract: A high performance memory based computation system comprises an array of memory cells. Each memory cell stores a logic data corresponding to a chosen combination of inputs based on a specific logic function. For improved performance, the memory cell array can be divided into sub-blocks; and the sub-blocks can be serially disposed or juxtaposed. The performance of the memory based computation system can further be improved by removing the repeated memory cell rows, column, and/or sub-arrays.

Abstract: A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell (20) is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform erase actions, all cells (20) of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity.

Abstract: A memory cell is provided which includes an access transistor and a gated lateral thyristor (GLT) device. The access transistor includes a source node. The gated lateral thyristor (GLT) device includes an anode node coupled to the source node of the access transistor.

Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.

Abstract: A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).

Abstract: A memory device includes a plurality of word lines extending as rows and bit lines extending as columns. A memory cell is coupled between a word line and a bit line, wherein the memory cell includes a unipolar memory element selectively coupled to the bit line via a trigger element.

Abstract: A nonvolatile memory cell includes a steering element located in series with a storage element. The storage element includes a carbon material and the memory cell includes a rewritable cell having multiple memory levels.

Abstract: A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes.

Abstract: Methods and apparatus for differentially measuring the bit state of a particular element in an array of passive nonlinear elements against the output of a reference generator. The reference generator may be, for example, a dummy row circuit, a dummy column circuit, or both a dummy row circuit and a dummy column circuit.

Abstract: The subject invention provides systems and methods that facilitate formation of semiconductor memory devices comprising memory cells with one or more injecting bilayer electrodes. Memory arrays generally comprise bit cells that have two discrete components; a memory element and a selection element, such as, for example, a diode. The invention increases the efficiency of a memory device by forming memory cells with selection diodes comprising a bilayer electrode. Memory cells are provided comprising bilayer cathodes and/or bilayer anodes that facilitate a significant improvement in charge injection into the diode layers of memory cells. The increased charge (e.g. electrons or holes) density in the diode layers of the selected memory cells results in improved memory cell switching times and lowers the voltage required for the memory cell to operate, thereby, creating a more efficient memory cell.

Abstract: A resistance change memory device including a memory cell array with first wirings, second wirings, and memory cells, the memory cell including a diode and a variable resistance element, anode of diodes being located on the first wiring side, wherein the memory cell array is sequentially set in the following three states after power-on: a waiting state defined by that both the first and second wirings are set at a first voltage; a standby state defined by that the first wirings are kept at the first voltage and the second wirings are set at a second voltage higher than the first voltage; and an access state defined by that a selected first wiring and a selected second wiring are set at a third voltage higher than the first voltage and the first voltage, respectively.

Abstract: A phase change memory device may include an integrated circuit substrate and first and second phase change memory elements on the integrated circuit substrate. The first phase change memory element may include a first phase change material having a first crystallization temperature. The second phase change memory element may include a second phase change material having a second crystallization temperature. Moreover, the first and second crystallization temperatures may be different so that the first and second phase change memory elements are programmable at different temperatures. Related methods and systems are also discussed.

Abstract: A method of programming a nonvolatile memory array including a plurality of nonvolatile memory cells, a plurality of bit lines, and a plurality of word lines, wherein each memory cell comprises a diode, or a diode and a resistivity switching element is disclosed. The method includes both bias programming the memory cells of the device.

Abstract: A non-volatile memory including a diode and a memory cell is described. The diode includes a doped region, a metal silicide layer, and a patterned doped semiconductor layer. The doped region of a first conductive type is formed in a substrate. The metal silicide layer is formed on the substrate. The patterned doped semiconductor layer of a second conductive type is formed on the metal silicide layer. The memory cell is formed on the substrate and coupled with the diode.

Abstract: Methods and apparatus for providing an array of passive nonlinear elements having an interface circuit that isolates the array from loading effects from external connections to the array. In one embodiment, a capacitive switching circuit is used to electrically isolate the elements in the array from the external load.

Abstract: A memory cell and method for making a memory cell in accordance with embodiments of the present invention includes two or more tunnel diodes, a loading system, and a driving system. The two or more tunnel diodes are coupled together, the loading system is coupled to the tunnel diodes and the driving system is coupled to the tunnel diodes and the loading system. The driving system drives a sense node from the tunnel diodes, the loading system, and the driving system between at least three or more substantially stable logic states.

Abstract: Methods and apparatus for measuring the bit state of a particular element in an array of passive nonlinear elements that are insensitive to loading effects from external connections to the array. In one embodiment, a switching element is used to electrically isolate the elements in the array from the external load.

Abstract: One embodiment of the present invention relates to an integrated circuit that includes a memory cell. The memory cell includes a capacitor configured to store a charge or voltage. The capacitor includes a first semiconductor fin having a first conductivity type and overlying a semiconductor body, a dielectric overlying at least part of the semiconductor fin, and a gate electrode overlying the dielectric. The memory cell also includes a diode. The diode includes an end portion of the first semiconductor fin and a second semiconductor fin that forms a junction with the end portion of the first semiconductor fin. The second semiconductor fin has a second conductivity type and includes first and second legs in different directions from the junction. Other devices and methods are also disclosed.

Abstract: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.

Abstract: The present invention provides a method of reading data from a non-volatile memory device including word lines and bit lines that intersect each other and electrically rewritable memory cells that are arranged at intersections of the word lines and the bit lines and that respectively have variable resistive elements nonvolatily storing a resistances as data. The method includes: precharging a selected word line and unselected word lines to a first word line voltage and a selected bit line and unselected bit lines to a first bit line voltage; and reading data from a memory cell connected to the selected word line and the selected bit line by changing the voltage of the selected word line from the first word line voltage to a second word line voltage and changing the voltage of the selected bit line from the first bit line voltage to a second bit line voltage after the precharging.