Insulated Gate Devices Patents (Class 365/182)
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Patent number: 9672911Abstract: A memory device includes a volatile memory cell and a non-volatile memory cell. The non-volatile memory cell includes a first resistive element having a first terminal and a second terminal and a second resistive element having a first terminal and a second terminal. The first terminal of the first resistive element is coupled to the first terminal of the second resistive element at a first node. The second terminal of the first resistive element is coupled to a first source line voltage. The second terminal of the second resistive element is coupled to a second source line voltage. A first transistor includes a first current electrode coupled to a first data storage node of the volatile memory cell, a second current electrode coupled to a supply voltage, and a control gate coupled to the first node.Type: GrantFiled: August 25, 2015Date of Patent: June 6, 2017Assignee: NXP USA, Inc.Inventors: Anirban Roy, Michael A. Sadd
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Patent number: 9564184Abstract: A single ended line sense amplifier having an input coupled to a single ended line having a near end and a far end device comprises a plurality of nFET stacks coupled between the near end of the single ended line and the far end of the single ended line, a single ended line comparator coupled to the near end of the single ended line configured to compare a voltage at the near end of the single ended line to provide a logic state output, and a charge transistor coupled to the single ended line at a point that is between the near end of the single ended line and the far end of the single ended line to shift occurrence of snap back from strong charging of the single ended line.Type: GrantFiled: November 12, 2015Date of Patent: February 7, 2017Assignee: Invecas, Inc.Inventor: John Edward Barth, Jr.
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Patent number: 9559185Abstract: A semiconductor device includes a substrate including an active fin structure, a plurality of gate structures, a first spacer on sidewalls of each of the gate structures, and a second spacer on sidewalls of the first spacer. The active fin structure may extend in a first direction and including a plurality of active fins with adjacent active fins divided by a recess. Each of the plurality of gate structures may extend in a second direction crossing the first direction, and may cover the active fins. The first spacer may include silicon oxycarbonitride (SiOCN), and may have a first carbon concentration. The second spacer may include SiOCN and may have a second carbon concentration which is different from the first carbon concentration. The semiconductor device may have a low parasitic capacitance and good electrical characteristics.Type: GrantFiled: April 21, 2016Date of Patent: January 31, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Suk Tak, Gyeom Kim, Ki-Yeon Park, Sung-Hyun Choi, Bon-Young Koo
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Patent number: 9461055Abstract: An advanced metal-nitride-oxide-silicon (MNOS) multiple time programmable (MTP) memory is provided. In an example, an apparatus includes a two field effect transistor (2T field FET) metal-nitride-oxide-silicon (MNOS) MTP memory. The 2T field FET MNOS MTP memory can include an interlayer dielectric (ILD) oxide region that is formed on a well and separates respective gates of first and second transistors from the well. A control gate is located between the respective gates of the first and second transistors, and a silicon-nitride-oxide (SiN) region is located between a metal portion of the control gate and a portion of the ILD oxide region.Type: GrantFiled: May 16, 2014Date of Patent: October 4, 2016Assignee: QUALCOMM INCORPORATEDInventors: Xia Li, Zhongze Wang, Daniel Wayne Perry
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Patent number: 9373412Abstract: An apparatus includes a semiconductor transistor structure. The semiconductor transistor structure includes dielectric material, a channel region, a gate, a source overlap region, and a drain overlap region. The source overlap region is biasable to cause a first voltage difference between the source overlap region and the gate to exceed a breakdown voltage of the dielectric material. The drain overlap region is biasable to cause a second voltage difference between the drain overlap region and the gate to exceed the breakdown voltage. The apparatus includes a well line coupled to a body of the semiconductor transistor. The apparatus includes circuitry configured to apply a voltage to the well line to prevent a breakdown condition between the channel region and the gate.Type: GrantFiled: December 15, 2014Date of Patent: June 21, 2016Assignee: Qualcomm IncorporatedInventors: Xia Li, Bin Yang
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Patent number: 9293196Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.Type: GrantFiled: March 15, 2013Date of Patent: March 22, 2016Assignee: Micron Technology, Inc.Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitigawa, Jun Sumino, D. V. Nirmal Ramaswamy
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Patent number: 9286968Abstract: Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines.Type: GrantFiled: September 14, 2012Date of Patent: March 15, 2016Assignee: Renesas Electronics CorporationInventors: Kenichi Osada, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi
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Patent number: 9257152Abstract: Multi-dimensional memory architectures are provided having access wiring structures that enable different access patterns in multiple dimensions. Furthermore, three-dimensional multiprocessor systems are provided having multi-dimensional cache memory architectures with access wiring structures that enable different access patterns in multiple dimensions.Type: GrantFiled: November 9, 2012Date of Patent: February 9, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Alper Buyuktosunoglu, Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan K. Kailas
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Patent number: 9219117Abstract: According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage.Type: GrantFiled: April 22, 2014Date of Patent: December 22, 2015Assignee: Infineon Technologies AGInventors: Dmitri Alex Tschumakow, Erhard Landgraf, Claus Dahl, Steffen Rothenhaeusser
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Patent number: 9182925Abstract: A memory system is provided in which at least one memory chip and a memory controller chip are mounted in a side-by-side relationship on an interposer. The memory chip is connected to the interposer via a Wide I/O interface to enable the memory chip and the memory controller chip to communicate with each other via the Wide I/O interface. The memory controller chip has an interface for communicating with an interface of an integrated circuit (IC) chip of the memory system.Type: GrantFiled: December 19, 2013Date of Patent: November 10, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventor: Larry J. Thayer
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Method of converting between non-volatile memory technologies and system for implementing the method
Patent number: 9171120Abstract: A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference.Type: GrantFiled: December 11, 2014Date of Patent: October 27, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Cheng Sung, Yue-Der Chih, Chia-Hsing Chen -
Patent number: 9159392Abstract: Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed.Type: GrantFiled: April 16, 2014Date of Patent: October 13, 2015Assignee: Micron Technology, Inc.Inventors: Tae Kim, Howard C. Kirsch, Charles L. Ingalls, Shigeki Tomishima, K. Shawn Smith
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Patent number: 9153517Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.Type: GrantFiled: May 17, 2011Date of Patent: October 6, 2015Assignee: Invensas CorporationInventors: Reynaldo Co, Jeffrey S. Leal, Suzette K. Pangrle, Scott McGrath, DeAnn Eileen Melcher, Keith L. Barrie, Grant Villavicencio, Elmer M. del Rosario, John R. Bray
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Patent number: 9036422Abstract: Disclosed are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell block including a plurality of memory cells, a voltage providing unit suitable for providing a pass voltage or a read voltage to word lines coupled with the memory cells and a control circuit suitable for controlling the voltage providing unit to adjust a pass voltage applied to the memory cells disposed at one side of a selected memory cell and a pass voltage applied to the memory cells disposed at the other side of the selected memory cell based on an address of a word line of the selected memory cell among the memory cells during a read operation or a verification operation.Type: GrantFiled: November 8, 2013Date of Patent: May 19, 2015Assignee: HK Hynix Inc.Inventor: Myeong Cheol Son
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Patent number: 9007838Abstract: A semiconductor integrated circuit includes a transistor with a source region, a drain region, and a control gate electrode. The integrated circuit additionally includes a controller that selectively applies voltages to the control gate of the transistor. The controller may apply a first voltage that forms a permanent conductive path between the source and drain of the transistor.Type: GrantFiled: February 25, 2013Date of Patent: April 14, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Koichiro Zaitsu, Kosuke Tatsumura
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Publication number: 20150098270Abstract: An apparatus includes a semiconductor transistor structure. The semiconductor transistor structure includes dielectric material, a channel region, a gate, a source overlap region, and a drain overlap region. The source overlap region is biasable to cause a first voltage difference between the source overlap region and the gate to exceed a breakdown voltage of the dielectric material. The drain overlap region is biasable to cause a second voltage difference between the drain overlap region and the gate to exceed the breakdown voltage. The apparatus includes a well line coupled to a body of the semiconductor transistor. The apparatus includes circuitry configured to apply a voltage to the well line to prevent a breakdown condition between the channel region and the gate.Type: ApplicationFiled: December 15, 2014Publication date: April 9, 2015Inventors: Xia Li, Bin Yang
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Patent number: 8964461Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device including the steps of applying a first non-negative voltage potential to a first region via a bit line and applying a second non-negative voltage potential to a second region via a source line. The method may also include applying a third voltage potential to a word line, wherein the word line may be spaced apart from and capacitively to a body region that may be electrically floating and disposed between the first region and the second region. The method may further include applying a fourth positive voltage potential to a third region via a carrier injection line, wherein the third region may be disposed below at least one of the first region, the body region, and the second region.Type: GrantFiled: November 19, 2013Date of Patent: February 24, 2015Assignee: Micron Technology, Inc.Inventor: Yogesh Luthra
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Patent number: 8942034Abstract: A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between ad rain overlap region of the semiconductor transistor structure and the gate.Type: GrantFiled: February 5, 2013Date of Patent: January 27, 2015Assignee: QUALCOMM IncorporatedInventors: Xia Li, Bin Yang
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Patent number: 8937304Abstract: A first field-effect transistor provided over a substrate in which an insulating region is provided over a first semiconductor region and a second semiconductor region is provided over the insulating region; an insulating layer provided over the substrate; a second field-effect transistor that is provided one flat surface of the insulating layer and includes an oxide semiconductor layer; and a control terminal are provided. The control terminal is formed in the same step as a source and a drain of the second field-effect transistor, and a voltage for controlling a threshold voltage of the first field-effect transistor is supplied to the control terminal.Type: GrantFiled: January 24, 2012Date of Patent: January 20, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masashi Fujita, Yutaka Shionoiri, Hiroyuki Tomatsu, Hidetomo Kobayashi
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Publication number: 20150016179Abstract: While the supply of power is stopped, a data signal that has been held in a volatile memory section can be held in a nonvolatile memory section. In the nonvolatile memory section, a transistor having an extremely low off-state current allows a data signal to be held in the capacitor for a long period of time. Thus, the nonvolatile memory section can hold the logic state even while the supply of power is stopped. When the supply of power is started again, the data signal that has been held in the capacitor while the supply of power has been stopped is set at such a potential that malfunction does not occur by turning on the reset circuit.Type: ApplicationFiled: July 17, 2014Publication date: January 15, 2015Inventor: Masashi Fujita
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Publication number: 20140369115Abstract: Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer.Type: ApplicationFiled: January 15, 2014Publication date: December 18, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Kook-Tae KIM, Young-Tak KIM, Ho-Sung SON, Seok-Jun WON, Ji-Hye YI, Chul-Woong LEE
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Publication number: 20140355339Abstract: In a memory cell including first to third transistors, the potential of a bit line is set to VDD or GND when data is written through the first transistor. In a standby period, the potential of the bit line is set to GND. In reading operation, the bit line is brought into a floating state at GND, and a source line is set to a potential VDD??, consequently, the third transistor is turned on. Then, the potential of the source line is output according to the potential of a gate of the second transistor. Note that ? is set so that the second transistor is surely off even when the potential of the gate of the second transistor becomes lower from VDD by ?V in the standby period. That is, Vth+?V<? is satisfied where Vth is the threshold value of the second transistor.Type: ApplicationFiled: May 28, 2014Publication date: December 4, 2014Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hiroki Inoue, Takanori Matsuzaki, Tomoaki Atsumi
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Patent number: 8885403Abstract: A method of programming a split gate memory applies voltages differently to the terminals of the selected cells and the deselected cells. For cells being programming by being coupled to a selected row and a selected column, coupling the control gate to a first voltage, coupling the select gate to a second voltage, programming is achieved by coupling the drain terminal to a current sink that causes the split gate memory cell to be conductive, and coupling the source terminal to a third voltage. For cells not being programmed by not being coupled to a selected row, non-programming is maintained by coupling the control gate to the first voltage, coupling the select gate to a fourth voltage which is greater than a voltage applied to the select gate during a read in which the split gate memory cells are deselected but sufficiently low to prevent programming.Type: GrantFiled: January 28, 2013Date of Patent: November 11, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Cheong M. Hong, Ronald J. Syzdek, Brian A. Winstead
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Publication number: 20140328122Abstract: Exemplary embodiments of the present invention disclose a method and system for asserting a voltage transition from a low voltage to a high voltage with a voltage difference between the low and high voltages on a word line with a word line driver logic that is composed of thin-oxide MOS transistors, wherein the thin-oxide MOS transistors experience less than the voltage difference on the word line between any two of a source, a drain, and a gate. In a step, charging the word line from the low voltage to an intermediate voltage level. In another step, charging the word line to the high voltage from the intermediate voltage level.Type: ApplicationFiled: May 6, 2013Publication date: November 6, 2014Applicant: International Business Machines CorporationInventor: John E. Barth, JR.
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Publication number: 20140313821Abstract: A fin-type device system and method is disclosed. In a particular embodiment, a transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent to a second BOX layer face of the BOX layer.Type: ApplicationFiled: July 1, 2014Publication date: October 23, 2014Inventors: Stanley Seungchul SONG, Mohamed Hassan ABU-RAHMA, Beom-Mo HAN
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Patent number: 8854877Abstract: A nonvolatile semiconductor memory device and a method of reusing the same that allow a good use of the semiconductor device without degrading characteristics even when reused. The semiconductor memory device comprises information holding means for holding information that indicates an operation mode of said memory cell array, a decoder for generating, to said memory cell array, a selection signal to designate at least a read address of said memory cell array in accordance with an address signal that comprises plural bits; and mode setting means for fixing a logical value of at least one bit of said plural bits of said address signal in accordance with the information held by said information holding means, and supplying said address signal, on which fixing of the logical value is effected, to said decoder.Type: GrantFiled: July 8, 2011Date of Patent: October 7, 2014Assignee: Lapis Semiconductor Co., Ltd.Inventors: Yuji Nagashima, Bunsho Kuramori, Hiroyuki Tanikawa
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Patent number: 8853791Abstract: A memory cell includes diffusion regions formed in a substrate. Each of the diffusion regions extends along a vertical direction in a layout view at a substrate level. A first gate electrode structure at a gate electrode level is generally dogleg shaped. The first gate electrode structure extends in an oblique direction, turns to a horizontal direction, extends over and crosses the diffusion regions in the horizontal direction. A first contact structure at a contact level is generally rectangular shaped in the layout view of the cell. The first contact structure electrically connects a first source/drain region of the first diffusion region to the first gate electrode structure and the first source/drain region of the second diffusion region. The first contact structure extends from the first source/drain region of the first diffusion region to the first source/drain region of the second diffusion region at the contact level.Type: GrantFiled: November 6, 2006Date of Patent: October 7, 2014Assignee: Infineon Technologies AGInventors: Uwe Paul Schroeder, Martin Ostermayr
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Patent number: 8848449Abstract: A memory device capable of being operated with a single potential uses capacitive coupling of a capacitor connected to a gate of a transistor for data writing. That is, the capacitive coupling is induced by inputting a signal, which is supplied by a delay circuit configured to delay a write signal having a potential equal to the power supply potential, to the capacitor. Increase in the potential of the gate by the capacitive coupling allows the transistor to be turned on in association with the power supply potential applied to the gate from a power supply. Data is written by inputting a signal having a potential equal to the power supply potential or a grounded potential to a node through the transistor.Type: GrantFiled: May 16, 2012Date of Patent: September 30, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Masami Endo
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Publication number: 20140254259Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.Type: ApplicationFiled: May 20, 2014Publication date: September 11, 2014Applicant: Zeno Semiconductor, Inc.Inventor: Yuniarto Widjaja
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Publication number: 20140241053Abstract: Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant of energetic species is used to densify the dielectric material to provide a uniform wet etch rate across the surface of the dielectric material. Embodiments also include memory devices, integrated circuits, and electronic systems that include shallow trench isolation structures having the dielectric material with the high flux of energetic species implanted to the predetermined depth of the dielectric material.Type: ApplicationFiled: February 26, 2014Publication date: August 28, 2014Applicant: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, John A. Smythe, III
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Publication number: 20140241029Abstract: A memory cell array comprises first wiring lines, second wiring lines, and memory cells disposed at intersections thereof. A control circuit comprises a first power-supply line supplying a first voltage to selected ones of the first or second wiring lines, and first selection circuits connected between the first or second wiring lines and the first power-supply line, each first selection circuit comprising first and second transistors connected in series. The first selection circuits arranged along a first direction are connected to a first selection line. The first selection circuits arranged along a second direction perpendicular to the first direction are commonly connected to a second selection line. The first and second transistors each comprise a columnar semiconductor portion extending in a direction perpendicular to a semiconductor substrate, a gate-insulating film in contact with a side surface of the columnar semiconductor, and a gate electrode in contact with the gate-insulating film.Type: ApplicationFiled: August 20, 2013Publication date: August 28, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Yoshihisa IWATA
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Publication number: 20140241052Abstract: A desired current through a carbon nano tube (CNT) element of a CNT memory device can be controlled by a wordline voltage, and a voltage on the CNT common node can be held constant.Type: ApplicationFiled: February 26, 2013Publication date: August 28, 2014Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Keith W. Golke, David K. Nelson
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Publication number: 20140219017Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.Type: ApplicationFiled: April 7, 2014Publication date: August 7, 2014Applicant: Micron Technology, Inc.Inventors: Fernando Gonzalez, Chandra V. Mouli
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Publication number: 20140219015Abstract: A method includes creating a breakdown condition at a semiconductor transistor structure that includes an overlap region and a channel region. The breakdown condition is created by causing a first voltage difference between a gate of the semiconductor transistor structure and the overlap region to exceed a breakdown voltage of the semiconductor transistor structure while maintaining a second voltage difference between the gate and the channel region at less than the breakdown voltage.Type: ApplicationFiled: February 5, 2013Publication date: August 7, 2014Applicant: QUALCOMM INCORPORATEDInventors: Xia Li, Seung H. Kang, Xiaochun Zhu
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Publication number: 20140219016Abstract: A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between ad rain overlap region of the semiconductor transistor structure and the gate.Type: ApplicationFiled: February 5, 2013Publication date: August 7, 2014Applicant: QUALCOMM IncorporatedInventors: Xia Li, Bin Yang
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Publication number: 20140211559Abstract: A method of programming a split gate memory applies voltages differently to the terminals of the selected cells and the deselected cells. For cells being programming by being coupled to a selected row and a selected column, coupling the control gate to a first voltage, coupling the select gate to a second voltage, programming is achieved by coupling the drain terminal to a current sink that causes the split gate memory cell to be conductive, and coupling the source terminal to a third voltage. For cells not being programmed by not being coupled to a selected row, non-programming is maintained by coupling the control gate to the first voltage, coupling the select gate to a fourth voltage which is greater than a voltage applied to the select gate during a read in which the split gate memory cells are deselected but sufficiently low to prevent programming.Type: ApplicationFiled: January 28, 2013Publication date: July 31, 2014Inventors: Cheong M. Hong, Ronald J. Syzdek, Brian A. Winstead
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Publication number: 20140185394Abstract: A memory includes a plurality of bit cells. Each bit cell includes a bit line and a storage cell coupled to the bit line. A header PMOS transistor is coupled to the storage cell in each bit cell. The header PMOS transistor is at least partially turned off during a write operation by a header control signal.Type: ApplicationFiled: May 24, 2013Publication date: July 3, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Han Huang, Ming-Yi Lee, Chia-En Huang, Fu-An Wu, Jung-Ping Yang, Cheng-Hung Lee
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Patent number: 8767457Abstract: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.Type: GrantFiled: October 1, 2013Date of Patent: July 1, 2014Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Mike N. Nguyen
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Publication number: 20140177331Abstract: In order to fabricate a semiconductor device, a semiconductor substrate in a peripheral region is etched to form a plurality of holes. A gap-filling material is buried in the holes of the semiconductor substrate in the peripheral region, and first and second device isolation films are formed in the semiconductor device. A fin structure is formed by recessing the gap-filling material, and a gate is formed over a surface including the fin structure. As a result, operation characteristics of transistors formed in the peripheral region are improved and the short channel effects are also reduced.Type: ApplicationFiled: December 4, 2013Publication date: June 26, 2014Applicant: SK hynix Inc.Inventor: Hyun Jin LEE
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Publication number: 20140160840Abstract: A memory device includes a memory array, an array gap, a voltage provider, and a voltage divider. The voltage provider is disposed in the array gap and coupled to a column of memory cells of the memory array for providing a first voltage to the column of memory cells when a memory cell of the column is selected at a write cycle. The voltage provider is coupled to the voltage provider and the column of memory cells for providing a second voltage lower than the first voltage to the column of memory cells when the memory of the column is half selected at the write cycle.Type: ApplicationFiled: December 7, 2012Publication date: June 12, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventor: Hsin-Wen Chen
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Patent number: 8723878Abstract: A graphics memory device includes a memory array configured to store data for a display device comprising b*y rows by a*x columns of pixels, where b>a. The memory array is arranged in a*y rows by b*x columns of memory locations. Each memory location is adapted to store n-bit image data for one of the pixels of the display device. A memory location remapping circuit is adapted to map image data stored in the b*x columns of memory locations in the memory device to the a*x columns of the display device.Type: GrantFiled: March 9, 2007Date of Patent: May 13, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jongkon Bae, Kyuyoung Chung
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Patent number: 8711622Abstract: An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.Type: GrantFiled: July 12, 2013Date of Patent: April 29, 2014Assignee: Zeno Semiconductor, Inc.Inventor: Yuniarto Widjaja
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Patent number: 8705289Abstract: A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells.Type: GrantFiled: January 6, 2012Date of Patent: April 22, 2014Assignee: eMemory Technology Inc.Inventors: Ching-Sung Yang, Wen-Hao Ching, Wei-Ming Ku, Yung-Hsiang Chen, Shih-Chen Wang, Hsin-Ming Chen
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Publication number: 20140092681Abstract: A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials.Type: ApplicationFiled: October 31, 2013Publication date: April 3, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
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Publication number: 20140092680Abstract: A multiple well bias memory device that includes a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate and having a memory cell formed therein; and a second well of the first conductivity type formed in the semiconductor substrate and having formed therein a sense amplifier configured to sense and amplify data from the memory cell. The first and second wells have different doping concentrations and are biased to first and second voltages, respectively. The first voltage being lower than the second voltage.Type: ApplicationFiled: July 10, 2013Publication date: April 3, 2014Inventors: Chung-ki LEE, Hong-sun HWANG, Hyung-shin KWON, Jong-hyoung LIM
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Patent number: 8687417Abstract: A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.Type: GrantFiled: October 5, 2007Date of Patent: April 1, 2014Inventors: Ruigang Li, Jingrong Zhou, David Donggang Wu, Zhonghai Shi, James F. Buller, Akif Sultan, Fred Hause, Donna Michael
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Patent number: 8674351Abstract: A data retention period of a memory circuit is lengthened, power consumption is reduced, and a circuit area is reduced. Further, the number of times written data can be read to one data writing operation is increased. A memory circuit has a first field-effect transistor, a second field-effect transistor, and a third field-effect transistor. A data signal is input to one of a source and a drain of the first field-effect transistor. A gate of the second field-effect transistor is electrically connected to the other of the source and the drain of the first field-effect transistor. One of a source and a drain of the third field-effect transistor is electrically connected to a source or a drain of the second field-effect transistor.Type: GrantFiled: December 22, 2011Date of Patent: March 18, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Jun Koyama, Shunpei Yamazaki
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Publication number: 20140063934Abstract: A semiconductor device includes junction regions formed in upper portions of both sidewalls of a trench formed in a semiconductor substrate, a first gate electrode buried in the trench and having a stepped upper surface, and a second gate electrode formed on the first gate electrode to overlap a junction region.Type: ApplicationFiled: December 18, 2012Publication date: March 6, 2014Applicant: SK HYNIX INC.Inventors: Tae Kyung OH, Min Soo YOO
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Patent number: RE44950Abstract: A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device includes a semiconductor layer having a channel, a first insulating film provided on the channel, a floating electrode provided on the first insulating film, a second insulating film provided on the floating electrode, and a gate electrode provided on the second insulating film, and changes its data memory state by injection of charges into the floating electrode.Type: GrantFiled: November 28, 2012Date of Patent: June 17, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Jun Fujiki
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Patent number: RE45307Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.Type: GrantFiled: March 21, 2013Date of Patent: December 30, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Dai Nakamura, Hiroyuki Kutsukake, Kenji Gomikawa, Takeshi Shimane, Mitsuhiro Noguchi, Koji Hosono, Masaru Koyanagi, Takashi Aoi