Abstract: A memory circuit includes a latch having a first node and a second node, a MIS transistor having a gate node, a first source/drain node coupled to the first node of the latch, and a second source/drain node, and a control circuit configured to control the gate node and second source/drain node to make a lingering change in a threshold voltage of the MIS transistor in a first operation and to cause the latch in a second operation to store data responsive to whether a lingering change in the threshold voltage is present, wherein the MIS transistor includes diffusion regions, a gate electrode, and sidewalls, wherein a metallurgical junction of each of the diffusion regions is positioned under the gate electrode, and a lateral boundary of a depletion layer in the diffusion region serving as a drain is positioned under a corresponding one of the sidewalls in the first operation.

Abstract: This disclosure concerns a semiconductor memory device including Fin semiconductors extending in a first direction; source layers provided in the Fin semiconductors; drain layers provided in the Fin semiconductors; floating bodies provided in the Fin semiconductors between the source layers and the drain layers, the floating bodies being in an electrically floating state and accumulating or discharging carries so as to store data; first gate electrodes provided in first grooves located between the Fin semiconductors adjacent to each other; second gate electrodes provided in second grooves adjacent to the first grooves and located between the Fin semiconductors adjacent to each other; bit lines connected to the drain layers, and extending in a first direction; word lines connected to the first gate electrodes, and extending in a second direction orthogonal to the first direction; and source lines connected to the source layers, and extending in the second direction.

Abstract: A method produces a vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the depression as well as the doped terminal region remote from the opening, a control region arranged in the depression, and an electrical insulating region between the control region and the channel region. The terminal region remote from the opening leads as far as a surface containing the opening or is electrically conductively connected to an electrically conductive connection leading to the surface. The control region is arranged in only one depression. The field-effect transistor is a drive transistor at a word line or at a bit line of a memory cell array.

Abstract: An integrated circuit includes a plurality of switching devices, wherein each device includes a gate dielectric capable of assuming at least a first and a second polarization state. The integrated circuit further includes an address circuit configured to control bit lines electrically coupled to first load regions of a load path of the switching devices and a word line electrically coupled to gate electrodes of the switching devices. The address circuit is configured to control a write cycle such that a first voltage is induced at the gate dielectrics of selected ones of the switching devices and a second voltage is induced at the gate dielectrics of non-selected ones of the switching devices. The first voltage suffices to switch the gate dielectrics of the selected devices from the first to the second polarization state and the second voltage does not suffice to switch the gate dielectrics of the non-selected devices.

Abstract: The present invention discloses a suspended nanochannel transistor structure and a method for fabricating the same. The transistor structure of the present invention comprises a substrate; a side gate formed on the substrate; a dielectric layer covering the substrate and the side gate; a suspended nanochannel formed beside the lateral of the side gate with an air gap existing between the suspended nanochannel and the dielectric layer; a source and a drain formed over the dielectric layer and respectively arranged at two ends of the suspended nanochannel. The electrostatic force of the side gate attracts or repels the suspended nanochannel and thus fast varies the equivalent thickness of the side-gate dielectric layer. Thereby, the on/off state of the element is rapidly switched, or the initial voltage of the channel is altered.

Abstract: Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

Abstract: Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a voltage swing comprising: a plurality of dynamic random access memory cells arranged in arrays of rows and columns, each dynamic random access memory cell including one or more memory transistors. The one or more memory transistors of the apparatus for reducing a voltage swing may comprise: a first region coupled to a source line, a second region coupled to a bit line, a first body region disposed between the first region and the second region, wherein the first body region may be electrically floating, and a first gate coupled to a word line spaced apart from, and capacitively coupled to, the first body region.

Abstract: One embodiment includes a plurality of word lines, a plurality of source lines, a plurality of bit lines intersecting with the plurality of word lines, and a plurality of memory cells formed at intersections of the plurality of word lines and the plurality of bit lines. Each of the plurality of memory cells is a floating body cell. A gate of each floating body cell is connected to one of the word lines, a drain of each floating body cell is connected to one of the bit lines, and a source of each floating body cell is connected to one of the source lines. At least one bit line and source line selecting circuit is configured to selectively connect each of the plurality of bit lines to a first output bit line and to selectively connect the source lines to a source voltage. At least one sense amplifier is configured to sense data based on a voltage on the first output bit line.

Abstract: A semiconductor memory device with low power consumption and improved transfer rate of an input/output buffer at reduced manufacturing cost is provided. Thick-film transistors are used for a memory cell array 33, a row decoder 30, and a sense amplifier 32, surrounded by a bold broken line. Thick-film transistors having a threshold voltage lower than the aforementioned transistors are used for input buffers 11 to 13 and an input/output buffer 26, surrounded by a bold line. Thin-film transistors are used for a clock generator 16, a command decoder 17, a mode register 18, a controller 20, a row address buffer and refresh counter 21, a column address buffer and burst counter 22, a data control circuit 23, a latch circuit 24, a DLL 25, and a column decoder 31. (FIG.

Abstract: The present invention relates to an 1-transistor DRAM cell, a DRAM device and a manufacturing method therefor, a driving circuit for a DRAM, a driving method therefore, and a driving method for an 1-transistor DRAM, and a double-gate type 1-transistor DRAM. The present invention comprises a data hold process biasing a word line at a negative voltage level and biasing a sensing line and a bit line at a first constant voltage level; a data purging process resetting data by biasing the word line and the bottom word line at a second constant voltage level and biasing the sensing line and the bit line at the first constant voltage level; and a data write process biasing the word line and the bottom word line at the second constant voltage level and supplying a write data to the bit line.

Abstract: A semiconductor device includes a tube-type channel formed over a semiconductor substrate. The tube-type channel is connected to first and second conductive lines. A bias electrode is formed in the tube-type channel. The bias electrode is connected to the semiconductor substrate. An insulating film is disposed between the tube-type channel and the bias electrode. A surrounding gate electrode is formed over the tube-type channel.

Abstract: A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor in a first operation such that a lingering change is created in transistor characteristics of the MIS transistor in response to the data stored in the latch, wherein the MIS transistor includes a highly-doped substrate layer, a lightly-doped substrate layer disposed on the highly-doped substrate layer, diffusion regions formed in the lightly-doped substrate layer, a gate electrode, sidewalls, and an insulating film.

Abstract: Disclosed is a memory device and method of operation thereof. The memory device may include a source region and a drain region of a first dopant type, the source and drain regions contain a first semiconductor material; a body region of a second dopant type, the body region being sandwiched between the source and drain regions, the body comprising a second semiconductor material; a gate dielectric layer over at least the body region; and a gate comprising a conductive material over the gate dielectric layer. Specifically, one of the first semiconductor material and the second semiconductor material is lattice matched with the other of the first semiconductor material and the second semiconductor material and has an energy gap smaller than the energy gap of the other of the first semiconductor material and the second semiconductor material.

Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one.

Abstract: The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.

Abstract: Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET.

Abstract: The present invention relates generally to integrated circuits, to methods for manufacturing integrated circuits, and to integrated memory arrays.

Abstract: A semiconductor device to improve layout uniformity may include an active region formed in a substrate, a dummy active region formed in the substrate and separated from the active region, a word line crossing over the active region, and a dummy word line. The dummy word line is formed over the dummy active region to overlap at least part of the dummy active region and may have an end positioned within the dummy active region.

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

Abstract: A combo memory cell having a SRAM cell and a mask-ROM code programmer. The SRAM cell comprises first and second inverters. The first inverter comprises a first PMOS transistor and a first NMOS transistor. Gates of the first PMOS and NMOS transistors are commonly connected to a first input node and drains thereof commonly connected to a first output node. The second inverter comprises a second PMOS transistor and a second NMOS transistor. Gates of the second PMOS and NMOS transistors are commonly connected to a second input node and drains thereof commonly connected to a second output node. The first input node and the second output node are connected, as are the second input node and the first output node. The mask-ROM code programmer is coupled to the sources of the first and second PMOS transistors or the first and second NMOS transistors.

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.

Abstract: An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating body transistors) arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the gate and gate dielectric are disposed on or above the first semiconductor layer that is disposed on or above an insulating layer or region, (ii) the body region of each transistor is electrically floating, (iii) the transistors of adjacent memory cells include a layout that provides a common first region, and (iv) the first regions of the transistors are comprised of a semiconductor material which is different from the material of the first semiconductor layer. Also disclosed are inventive methods of manufacturing, for example, such integrated circuit devices.

Abstract: A semiconductor memory structure based on gate oxide break down is constructed in a deep N-well. Thus, the electrical field over the programmable element during the transient procedure of gate oxide break down can be controlled to achieve the best memory programming results. The conductivity of the programmed memory cell is increased greatly and conductivity variation between the memory cells is reduced. This is achieved by adding a body bias during the programming process. The body here refers to a P-well formed within the deep N-Well. Furthermore, the read voltage offset is reduced greatly with this new memory configuration. These improved programming results will allow faster read speed and lower read voltage. This new structure also reduces current leakage from a memory array during programming.

Abstract: A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device.

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.

Abstract: A semiconductor device has a first inverter including a drive transistor and a load transistor; a second inverter including a drive transistor and a load transistor, a transmission transistor provided between the output terminal of the first inverter and one line of a bit line pair, a transmission transistor provided between the output terminal of the second inverter and the other line of the bit line pair; and an isolation transistor for isolating the drive transistor and the transmission transistor. The transmission transistor, the transmission transistor, the drive transistor, and the isolation transistor are formed in a continuous active region and the isolation transistor is provided between the drive transistor and the transmission transistor.

Abstract: A semiconductor memory device includes a memory cell array region in which vertical transistors each having a lower electrode connected to a bit line is regularly arranged with a predetermined pitch, including memory cells formed using at least the vertical transistors; a peripheral circuit region arranged adjacent to the memory cell array region in a bit line extending direction; and a predetermined circuit arranged overlapping the peripheral circuit region and the memory cell array region. In the semiconductor memory device, the vertical transistors each having an upper electrode connected to the predetermined circuit are included in an end region of the memory cell array region, in which no word line is provided.

Abstract: A field-effect transistor for nonvolatile memory holding use and a field-effect transistor for logical operation use are manufactured in the same structure on the same semiconductor substrate without separately providing manufacturing processes for the field-effect transistors for the two uses. Both a memory circuit and a logic circuit of a semiconductor integrated circuit are composed of n-channel and p-channel field-effect transistors including a memory holding material in a gate insulating structure. A logical operation state, a memory writing state and a nonvolatile memory holding state are electrically switched by controlling the level and application timing of a voltage to be applied between a gate conductor and a substrate region of the n-channel and p-channel field-effect transistors including the memory holding material in the gate insulating structure.

Abstract: In one embodiment, a first transistor is comprised of a first p+ source region doped in an n-well in the substrate and a first n+ drain region doped on one side at the top of the pillar. A second transistor is comprised of a second p+ source region doped into the second side of the top of the pillar and serially coupled to the top drain region for the first transistor. A second n+ drain region is doped into the substrate adjacent the pillar. Ultra-thin body layer run along each pillar sidewall between their respective active regions. A gate structure is formed along the pillar sidewalls and over the body layers. The transistors operate by electron tunneling from the source valence band to the gate bias-induced n-type channels, along the ultra-thin silicon bodies, thus resulting in a drain current.

Abstract: A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The nitride storage regions are isolated from each other by a depression in the control gate. In a vertical embodiment, the split nitride storage regions are separated by an oxide pillar. The cell is programmed by creating a positive charge on the nitride storage regions and biasing the drain region while grounding the source region. This creates a virtual source/drain region near the drain region such that the hot electrons are accelerated in the narrow pinched off region. The electrons become ballistic and are directly injected onto the nitride storage region that is adjacent to the pinched off channel region.

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.

Abstract: A one-transistor type DRAM comprises a floating body storage element configured to store data in a floating body in a SOI wafer, a plurality of access transistors each connected between a bit line and one end of the floating body storage element, a word line configured to control the floating body storage element, and a plurality of port word lines each configured to select one of the plurality of access transistors.

Abstract: A semiconductor memory device includes a one-transistor (1-T) field effect transistor (FET) type memory cell connected between a pair of bit lines, and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer. The device comprises a plurality of word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a pair of clamp dummy lines arranged in the column direction, a pair of reference dummy lines arranged in the column direction, a cell array including the memory cell and formed in a region where the word line and the bit line are crossed, a dummy cell array including the memory cell and formed where the word line, the pair of claim dummy lines and the pair of reference dummy lines are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.

Abstract: A combo memory cell comprising a SRAM cell and a mask-ROM code programmer. The SRAM cell comprises first and second inverters. The first inverter comprises a first PMOS transistor and a first NMOS transistor. Gates of the first PMOS and NMOS transistors are commonly connected to a first input node and drains thereof commonly connected to a first output node. The second inverter comprises a second PMOS transistor and a second NMOS transistor. Gates of the second PMOS and NMOS transistors are commonly connected to a second input node and drains thereof commonly connected to a second output node. The first input node and the second output node are connected, as are the second input node and the first output node. The mask-ROM code programmer is coupled to the sources of the first and second PMOS transistors or the first and second NMOS transistors.

Abstract: A thermally insulated memory device includes a memory cell, the memory cell having electrodes with a via extending therebetween, a thermal insulator within the via and defining a void extending between the electrode surfaces. A memory material, such as a phase change material, is within the void and electrically couples the electrodes to create a memory material element. The thermal insulator helps to reduce the power required to operate the memory material element. An electrode may contact the outer surface of a plug to accommodate any imperfections, such as the void-type imperfections, at the plug surface. Methods for making the device and accommodating plug surface imperfections are also disclosed.

Abstract: A semiconductor storage device comprising: unit blocks each including memory cells, first row of sense amplifiers on one side of bit lines; second row of sense amplifiers on an other side of the bit lines; first switch means which switches a connection state between the one side of the bit lines and the first row of sense amplifiers; second switch means which switches a connection state between the other side of the bit lines and the second row of sense amplifiers; third switch means arranged in the approximate center of the bit lines in an extending direction thereof to switch a connection state of the bit lines; and refresh control means which divides the unit block into two areas and controls the refresh operation using the switch means and the row of sense amplifiers according to which area a selected word line to be refreshed is in.

Abstract: A three-dimensional memory circuit provides reduction in memory cell instability due to half-select operation by reduction of the number of memory cells sharing a sense amplifier and, potentially, avoidance of half-select operation by placing some or all peripheral circuits including local evaluation circuits functioning as a type of sense amplifier on an additional chips or chips overlying the memory array. Freedom of placement of such peripheral circuits is provided with minimal increase in connection length since word line decoders may be placed is general registration with ant location along the word lines while local evaluation circuits and/or sense amplifiers can be placed at any location generally in registration with the bit line(s) to which they correspond.

Abstract: A magnetic memory cell and a magnetic memory incorporating the cell are described. The magnetic memory cell includes at least one magnetic element and at least one non-planar selection device. The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The magnetic memory may include a plurality of magnetic storage cells, a plurality of bit lines corresponding to the plurality of magnetic storage cells, and a plurality of source lines corresponding to the plurality of magnetic storage cells.

Abstract: A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower charge carrier mobility than the fin of the second transistor.

Abstract: A semiconductor memory device (1) has a FET (10) (first field-effect transistor), a FET (20) (second field-effect transistor), a contact plug (32) (first conductive plug), contact plugs (34) (second conductive plugs), and a detection circuit (50). The FET (20) is provided in a double well (40). M (m is a natural number) contact plugs (32) are connected to a diffusion layer (22) of the FET (20) while n (n is a natural number) contact plugs (34) are connected to a diffusion layer (24). Here, m is smaller than n. The detection circuit (50) detects the difference between the output of the FET (10) and the output of the FET (20).

Abstract: The disclosure concerns a semiconductor memory device includes a memory cell array including memory cells; word lines; bit lines; a counter cell array including counter cells provided corresponding to the word lines and storing the number of times of activating the word lines; an adder incrementing the number of times of activating the word lines which is read out from the counter cell array, when data is read or written in the memory cell; a counter buffer circuit temporarily storing the number of times of activating the word lines, and writing back the incremented number of times of activating the word lines into the counter cell array; and a sense amplifier executing a refresh operation during a data read cycle or a data write cycle, when the number of times of activating one of the word lines has reached a predetermined value.

Abstract: A semiconductor memory device including a dynamic random access memory (DRAM) cell and a ternary content addressable memory (TCAM) cell is disclosed. The DRAM cell may include a data storing portion and a data read portion. The data storing portion and data read portion comprising p-channel junction field effect transistors. The TCAM cell including an x-cell, y-cell, and comparator circuit. The x-cell, y-cell, and comparator circuits comprising p-channel JFETs.

Abstract: A fin FET array includes a number of fins 12 and a switch FET 52 between fins 12. The switch FET 52 acts to divide the transistor array into first 42 and second 44 FINFET regions having first 46 and second 48 gate electrodes controllably connected through the switch FET 52. Suitable voltages applied between the gate of the switch FET and the substrate 10 can allow the fin FET array either to act as a plurality of separate FETs or as a single device. A method of making the fin FET array to reduce the number of additional steps to fabricate the switch FET 52 is also described.

Abstract: Provided are a capacitorless dynamic random access memory (DRAM) and a method of manufacturing and operating the capacitorless DRAM. The capacitorless DRAM includes a substrate having a first dopant region formed on the upper part thereof, a first protrusion unit formed on the substrate, a first gate and a second gate formed on the substrate on both sides of the first protrusion unit, having a height lower than the first protrusion unit, and an insulating material layer interposed between the substrate and the first and second gates and between the first protrusion unit and the first and second gates, wherein a second dopant region is formed on the upper part of the first protrusion unit.

Abstract: The present invention relates generally to integrated circuits, to methods for manufacturing integrated circuits, and to integrated memory arrays.

Abstract: This disclosure concerns a semiconductor memory device comprising Fin semiconductors extending in a first direction; source layers provided in the Fin semiconductors; drain layers provided in the Fin semiconductors; floating bodies provided in the Fin semiconductors between the source layers and the drain layers, the floating bodies being in an electrically floating state and accumulating or discharging carries so as to store data; first gate electrodes provided in first grooves located between the Fin semiconductors adjacent to each other; second gate electrodes provided in second grooves adjacent to the first grooves and located between the Fin semiconductors adjacent to each other; bit lines connected to the drain layers, and extending in a first direction; word lines connected to the first gate electrodes, and extending in a second direction orthogonal to the first direction; and source lines connected to the source layers, and extending in the second direction.

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract: It is an object to solve inhibition of miniaturization of an element and complexity of a manufacturing process thereof. It is another object to provide a nonvolatile memory device and a semiconductor device having the memory device, in which data can be additionally written at a time besides the manufacturing time and in which forgery caused by rewriting of data can be prevented. It is further another object to provide an inexpensive nonvolatile memory device and semiconductor device. A memory element is manufactured in which a first conductive layer, a second conductive layer that is beside the first conductive layer, and conductive fine particles of each surface which is covered with an organic film are deposited over an insulating film. The conductive fine particles are deposited between the first conductive layer and the second conductive layer.

Abstract: A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

Abstract: Methods and apparatus that may help reduce standby current in memory devices are provided. By separating equalizing and precharging functions into separate circuit structures, current paths between a source of precharge voltage and a defective wordline (e.g., having an inadvertent short to a bitline due to a manufacturing defect) may be eliminated.