Abstract: A semiconductor device includes a current source, an input/output (IO) region having a first IO device and a second IO device, and a core region having a core device. The first and second IO devices form with the current source a current mirror circuit. Each of the first and second IO devices has a first threshold voltage, and the core device has a second threshold voltage that is lower than the first threshold voltage. The first core device is coupled to the first and second IO devices and the current source and provides an offset voltage to the current source.

Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining a voltage level of a stepped sense operation that activates a memory cell of the memory during a programming operation for the memory cell, and determining a voltage level of a ramped sense operation that activates the memory cell during a read operation for the memory cell.

Abstract: Apparatuses, systems, and methods are disclosed for dynamic read operations. A controller monitors one or more read statistics during a read operation for data of a non-volatile memory die. The controller determines whether one or more read statistics satisfy a threshold for a read operation. The controller dynamically modifies a read operation based on determining that one or more read statistics fail to satisfy a threshold.

Abstract: A memory system includes an array of non-volatile memory cells and a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.

Abstract: A semiconductor memory device includes: a first memory cell transistor; a bit line electrically connected to a first end of the first memory cell transistor; a source line electrically connected to a second end of the first memory cell transistor; and a control circuit. When a read operation for reading read data from the first memory cell transistor is performed, the control circuit is configured to apply a first voltage to the bit line in a first period, apply a second voltage, higher than the first voltage, to the bit line, and also apply a third voltage, lower than the first voltage, to the source line in a second period subsequent to the first period, and sense a threshold voltage of the first memory cell transistor in a third period subsequent to the second period.

Abstract: A method for determining an optimal threshold of a nonvolatile memory device, the method including: reading a page from a nonvolatile memory device with a default threshold and attempting to hard decode the page using the default threshold; reading the page two more times with a predetermined offset voltage when the hard decoding fails and attempting to soft decode the page using the default threshold; approximating an empirical distribution of successfully decoded bits with a Gaussian distribution for each level; finding an intersection of the Gaussian distributions; and setting the intersection as a new reading threshold and reading the page again with the new reading threshold.

Abstract: A memory system may include: a multi-level cell memory device; and a controller suitable for controlling the memory device, wherein the controller includes a processor suitable for searching for the last programmed word line in an open memory block when the memory system is powered up after a sudden power-off, and controlling sequential read operations on data of the memory device in a plurality of logical pages corresponding to the last programmed word line, wherein the processor ends the sequential read operations depending on whether error correction on sequentially read data fails, receives from a host the error correction-failed data and data on which the sequential read operations are not performed, and controls the memory device to program the received data.

Abstract: Apparatuses, systems and methods for dynamic timing of row pull-down operations are described herein. When a word line is accessed, the row decoder may drive that word line to an active voltage, and then to an intermediate voltage. The row decoder may maintain that word line at the intermediate voltage until another word line in the same group of word lines as the accessed word line receives an access command, at which point the first word line is driven to an inactive voltage. For example, if the word lines are grouped by bank, then after an access to a first word line, the first word line may be maintained at the intermediate voltage until a second wordline in the same bank as the first word line is accessed. This may help to mitigate the effect on other nearby word lines of driving a word line to the inactive voltage.

Abstract: Adaptive read-threshold schemes for a memory system determine read-threshold with the lowest BER/UECC failure-rates while continuing to serve the host-reads with the required QoS. When it is determined that the QoS or other quality metric is not met for a particular read-threshold, which may be an initial, default, read-threshold, the performance of other read-thresholds are estimated. These estimates may then be used to determine an optimal read-threshold. During the iterative process, selection variables, e.g., how many times, and for which read commands, to use each of the non-default read-thresholds in future read-attempts may be determined on-the-fly.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a memory string including memory cells including first to third memory cells, and a selection transistor connected to the memory cells, and first to third word lines that are connected to gates of the first to third memory cells of the memory string. The memory controller reads data of the first to third memory cells by applying first to third read voltages to the first to third word lines, respectively. The memory controller reads second data by applying a fourth read voltage to the second word line in parallel to processing of decoding first data, obtains likelihood information on the basis of the first data, the second data, and at least one of the third data and the fourth data, and decodes data on the basis of the likelihood information.

Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory cell; a bit line and a word line, coupled to the memory cell; and a page buffer configured to perform a read operation on the memory cell, wherein the page buffer senses a program state of the memory cell as one of at least three program states by performing a first evaluation operation, a first sensing operation, a second evaluation operation, and a second sensing operation when one read voltage is applied to the word line during the read operation.

Abstract: A non-volatile storage system includes a mechanism to compensate for over programming during the programming process. That is, after the programming process starts for a set of data and target memory cells, and prior to the programming process completing for the set of data and the target memory cells, the system determines whether a first group of the memory cells has more than a threshold number of over programmed memory cells. If so, then the system adjusts programming of a second group of memory cells to reduce the number of programming errors.

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, the duration of a programming voltage can change as the number of cells to be programmed changes.

Abstract: A memory system includes a semiconductor memory device including a memory block; and a scrambler and ECC block configured to generate program data using data received from a host, generate one or more data sets using the program data and page information data, and output the one or more data sets, during a write operation; and a memory controller configured to output the one or more data sets to the semiconductor memory device and to control the semiconductor memory device, wherein the semiconductor memory device is configured to read the page information data stored in each of the plurality of pages and detect, from among the plurality of pages, an erased page or a program-interrupted page in which a sudden power-off (SPO) has occurred during a boot operation.

Abstract: Provided herein may be a method of operating a semiconductor memory device. The method of operating a semiconductor memory device may include programming selected memory cells with first page data, and programming the selected memory cells with second page data and programming a flag cell with flag data according to a foggy-fine programming scheme. The flag data may indicate whether data programmed according to the program operation is the first page data or the second page data. An operation of programming the flag cell with the flag data may be initiated after foggy programming of the second page data is completed.

Abstract: An apparatus and/or system is described including a memory device or a controller to perform programming and verification operations including application of a shared voltage level to verify two program voltage levels of a multi-level cell device. For example, in embodiments, the control circuitry performs a program operation to program a memory cell and performs a verification operation by applying a single or shared verify voltage level to verify that the memory cell is programmed to a corresponding program voltage level. In embodiments, the program voltage level is one of two consecutive program voltage levels of a plurality of program voltage levels to be verified by application of the shared verify voltage. Other embodiments are disclosed and claimed.

Abstract: Addresses of accessed word lines are stored. Data related to victim word lines associated with the accessed word line are also stored. The victim word lines may have data stored in relation to multiple accessed word lines. The data related to the victim word lines is adjusted when the victim word line is refreshed during a targeted refresh operation or an auto-refresh operation. The data related to the victim word lines is adjusted when the victim word line is accessed during a memory access operation.

Abstract: A semiconductor memory device includes wirings arranged in parallel along a first direction, the wirings including first and second wirings that are adjacent and a third wiring adjacent to the second wiring, a first pillar between the first and second wirings and a second pillar between the second and third wirings, the first and second pillars each extending in a second direction crossing the first direction toward the semiconductor substrate, and first and second bit lines connected to the first and second pillars, respectively. A first voltage is applied to the second wiring during a program operation on a first memory cell at an intersection of the second wiring and the first pillar, and a second voltage higher than the first voltage is applied to the second wiring during a program operation on a second memory cell at an intersection of the second wiring and the second pillar.

Abstract: A semiconductor device includes a memory string that includes a plurality of memory cells and is coupled between a source line and a bit line. A method for operating the semiconductor device may include: boosting a first channel region in a channel region of the memory string, wherein the channel region includes the first channel region at one side of the selected memory cell and a second channel region at the other side of the selected memory cell; applying a pre-program bias to a gate electrode of the selected memory cell, to inject electrons into a space region of the selected memory cell; and applying a program bias to the gate electrode.

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

Abstract: A method of operating a semiconductor device, the semiconductor device includes: a memory block including a plurality of word lines; and a control logic for performing a first program operation on first memory cells corresponding to a first word line among the plurality of word lines, performing the first program operation on second memory cells corresponding to a second word line adjacent to the first word line, performing a second program operation on the first memory cells, performing a dummy program operation on third memory cells corresponding to a third word line adjacent to the second word line, and performing the second program operation on the second memory cells.

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory cells; a page buffer for performing a plurality of read operations and storing results of the read operations, wherein each of the read operations includes at least one sensing operation for selected memory cells from the plurality of memory cells; a multi-sensing manager for determining a number of sensing operations for each of the plurality of read operations and controlling the page buffer to perform the read operations; and a data identifier for identifying a data state of a bit for the selected memory cells based on the results of the read operations, wherein the multi-sensing manager determines the number of sensing operations for at least one read operation from among the read operations to be different from the number of sensing operations for other read operations from among the read operations.

Abstract: Methods, a memory device, and a system are disclosed. One such method includes providing a first pulse to one of multiple bit lines of a variable resistance memory structure at a first time using a first transistor, a second pulse to the one of the multiple bit lines at a second time later than the first time using the first transistor, and a third pulse to the one of the multiple bit lines at a third time later than the second time using a second transistor.

Abstract: Techniques for fabricating a semiconductor device having a two-part spacer. In one embodiment, a device is provided that comprises a spacer having a first portion and a second portion, where the first portion comprises one or more layers and the second portion comprises a dielectric material. In one or more implementations, the device further comprises an isolation layer coupled to the spacer, where the isolation layer comprises a silicon oxide material. In one or implementation, the device can further comprise a gate structure formed on a substrate, where the gate structure comprises a polysilicon contact portion, a first silicon dioxide portion, a silicon nitride portion and a second silicon dioxide portion.

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. The system can modify a high voltage signal applied to an array of cells during a programming operation as the number of cells being programmed changes.

Abstract: A first value is stored in a first memory cell. A first component output current, from a first electronic component, is provided based on the stored first value, wherein the first component output current is proportional to a place value represented by the first value. A second value is stored in a second memory cell. A second component output current, from a second electronic component, is provided based on the stored second value, wherein the second component output current is proportional to a place value represented by the second value. A combined current of at least the first component output current and the second component output current is detected, wherein the combined current corresponds to a sum of at least the first value and the second value.

Abstract: A memory system includes a semiconductor memory including memory cells and a memory controller configured to perform a first tracking process to determine a first voltage, and to read data using the first voltage in a read process after the first tracking process. In the first tracking process, the memory controller is configured to read only first, second, and third data respectively using a second, third, and fourth voltage, determine a number of first memory cells based on the first and second data, determine a number of second memory cells based on the second and third data, and determine the first voltage, based on the number of first and second memory cells.

Abstract: A memory system includes a memory device for storing data; and a memory controller performing a program operation on the memory device by using one of a first program mode and a second program mode. The memory controller counts a number of program operations performed by using the first program mode in which a ratio of dummy data to program data is greater than or equal to a predetermined value; and changes the program mode to the second program mode from the first program mode, when the counted number is greater than or equal to a predetermined number.

Abstract: Provided are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes a power-up signal generator configured to generate a power-up signal in response to a memory voltage reaching a target voltage level, an initializer configured to generate an initialization signal in response to the power-up signal and a reset signal and to generate an initial refresh command in response to completion of an initialization operation, and a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, the memory cell array configured to perform an initial refresh operation on the plurality of memory cells in response to the initial refresh command.

Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.

Abstract: Apparatuses, methods, and devices that can be utilized to provide temperature-based memory operations are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: determine an operating temperature of the apparatus, determine one of a plurality of designated open blocks of the memory device to write data based on the operating temperature of the apparatus and a size of the data, and write the data in the determined one of the plurality of designated blocks of the memory device.

Abstract: NAND memory devices are described that utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.

Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.

Abstract: A nonvolatile memory device includes multiple memory cells including first memory cells and second memory cells. A method of programming the nonvolatile memory device includes: performing first programming to apply a programming forcing voltage to a bit line of each of the first memory cells; and dividing the second memory cells into a first cell group, a second cell group, and a third cell group, based on a threshold voltage of the second memory cells after performing the first programming. The method also includes performing second programming to apply a programming inhibition voltage to the bit line of each of the first memory cells and a bit line of each of memory cells of the first cell group. A level of the programming forcing voltage is lower than that of the programming inhibition voltage.

Abstract: Provided is a programming method for a memory device including a memory array and a controller. The programming method including: controlling programming on a first page of a first word line by the controller; controlling programming on a first page of a second word line by the controller, the second word line being adjacent to the first word line; controlling for performing a first programming operation on a second page of the first word line by the controller; controlling programming on a first page of a third word line by the controller, the third word line being adjacent to the second word line; controlling for performing the first programming operation on a second page of the second word line by the controller; and controlling for performing a second programming operation on the second page of the first word line by the controller.

Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a particular multi-step programming pulse to a selected access line of a programming operation, and applying a next subsequent multi-step programming pulse to the selected access line, wherein the particular multi-step programming pulse has a first step having a first voltage level and a second step having a second voltage level different than the first voltage level, and wherein the next subsequent multi-step programming pulse has a first step having a third voltage level and a second step having a fourth voltage level different than the third voltage level and higher than the first voltage level.

Abstract: A semiconductor integrated circuit includes a cell array, an input unit and an output unit. Cell array includes word lines, bit lines and resistance change cells respectively formed at cross points between word lines and bit lines. Input unit includes an access controller and a driver. Access controller controls access of data to a cell in time series, the data being expressed by a matrix. Driver applies voltage to a word line coupled to the cell which is an access destination of the data, the voltage being adjusted depending on a value of the data to be accessed to the cell. The output unit includes holding circuits each holding a representative value of an output level of a corresponding one of the bit lines in time series.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes a grouping circuit that directs a single level writing circuit to write data corresponding to a first logical group to a set of single level cell blocks of a plurality of single level cell blocks.

Abstract: Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.

Abstract: A flash device access method, apparatus, and system, where a flash device includes a controller and a storage array. The method includes dividing the storage array into a specific storage unit and a user storage unit, such that a storage feature of the specific storage unit is the same as that of the user storage unit, writing, by the controller, specific data into the specific storage unit, reading, by the controller, the specific data stored in the specific storage unit, determining, by the controller, a decision voltage (Vread) based on the read specific data, and reading, by the controller using the determined Vread, the user data stored in the user storage unit. Hence, incorrect determining of the data stored in the flash device may be reduced using the access method, apparatus, and system.

Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.

Abstract: A memory system can identify target memory units to characterize by generating Cumulative Distribution Function (CDF)-based data for each memory unit and analyzing the CDF-based data to identify target memory units that are exceptional. Such target memory units can be those with CDF-based data with extrinsic tails or that crosses an info limit threshold. The memory system can perform characterization processes for the target memory units, e.g. using an Auto Read Calibration (ARC) analysis or a Continuous Read Level Calibration (cRLC) analysis. A manufacturing process for the memory device can use results of the characterization processes, e.g. by mapping them to types of problems observed during testing. Alternatively, results of the characterization processes to can be used during operation of the memory device, e.g. to adjust the initial read voltage threshold, the read retry voltage values, or the order of read retry voltages used in data recovery.

Abstract: A controller executes a plurality of first read operations and, when receiving a read request from a host, executes a second read operation. The first read operations are executed using, as determination voltage, different candidate values among a plurality of candidate values. In each of the first read operations, the controller executes error correction to acquired data, and acquires a first candidate value on the basis of results of the error corrections in the first read operations. The second read operation is executed using, as the determination voltage, a second candidate value that is ranked higher than the first candidate value.

Abstract: A data storage device include a nonvolatile memory device having a plurality of super blocks; a memory configured to store a free first logical page list including position information of free first logical pages which are present in completely used super blocks, among the plurality of super blocks; and a processor configured to select a super block having no valid page and having the free first logical pages, among the completely used super blocks, based on the free first logical page list, and to use the free first logical pages in the selected super block during a write operation.

Abstract: The present disclosure includes apparatuses and methods for counter update operations. An example apparatus comprises a memory including a managed unit that includes a plurality of first groups of memory cells and a second group of memory cells, in which respective counters associated with the managed unit are stored on the second group of memory cells. The example apparatus further includes a controller. The controller includes a core configured to route a memory operation request received from a host and a datapath coupled to the core and the memory. The datapath may be configured to issue, responsive to a receipt of the memory operation request routed from the core, a plurality of commands associated with the routed memory operation request to the memory to perform corresponding memory operations on the plurality of first groups of memory cells. The respective counters may be updated independently of the plurality of commands.

Abstract: A method of operating a memory device includes performing a first program operation on memory cells connected to a first word line among a plurality of word lines, performing the first program operation on memory cells connected to a second word line among the plurality of word lines, applying a turn-on voltage at a first level to the first and second word lines, applying a voltage at a level lower than the first level to a third word line among the plurality of word lines, performing a precharge operation on partial cell strings among a plurality of cell strings, and performing a second program operation on the memory cells connected to the first word line.

Abstract: According to one embodiment, a memory system comprising: a semiconductor storage device including a memory cell connected to a word line and capable of storing n-bit data (n is an integer of 2 or more); and a controller circuit, wherein the semiconductor storage device determines a value of the n-bit read data stored in the memory cell, by a first reading operation using k reading voltages different from each other (k is an integer equal to or higher than 2{circumflex over (?)}(n?1) and less than 2{circumflex over (?)}n?1), and the controller circuit converts the value of the n-bit read data into data corresponding to (k+1) decimal data.

Abstract: An operating method of a storage device, which includes a nonvolatile memory device, includes entering a power-on mode, searching for an open memory block, which includes at least one erase word line, from among memory blocks included in the nonvolatile memory device, applying a program voltage to the at least one erase word line to close the open memory block if the number of the erase word lines included in the open memory block is not more than a preset value, and after the power-on mode, entering a normal operation mode. Memory cells connected to the at least one erase word line to which the program voltage is applied are programmed to have a threshold voltage distribution range higher than a threshold voltage distribution range of an erase state.

Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry.