Abstract: A method applied into a memory controller coupled between a memory device and a host device wherein the memory device supports at least two different storing modes includes: receiving and buffering data transmitted from the host device; using a first storing mode to store a first data unit into the memory device, a size of the first data unit being not larger than a size of a specific storage unit defined in the memory device; and using a second storing mode, different from the first storing mode, to store a second data unit into the memory device, a size of the second data unit being larger than the size of the specific storage unit.

Abstract: A semiconductor memory device includes a memory cell transistor, a word line coupled to the memory cell transistor, a temperature detection element configured to detect a temperature, and a control unit. The control unit is configured to determine, responsive to receiving a first command from a controller, a compensation value for a read voltage designated by the controller according to the detected temperature, and to lock updating of the compensation value.

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract: Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a plurality of first lines; a plurality of second lines; a plurality of memory cells disposed in respective intersection regions between the plurality of first lines and the plurality of second lines; a first test circuit configured to apply a stress pulse to a first selection line coupled to a defective memory cell among the plurality of memory cells during a first test period, in response to a first test control signal, the first selection line including any one of the plurality of first lines; and a control unit configured to generate the first test control signal based on a first test mode signal.

Abstract: An operating method of the semiconductor memory device including a plurality of memory cells each having one of “n” number of program statuses as a target program status. The operating method includes performing a program operation to the memory cells according to one of first to third program mode set until a first condition is met; performing the program operation to the memory cells according to another one of first to third program mode set until a second condition is met; and performing the program operation to the memory cells according to a remaining one of first to third program mode set.

Abstract: A memory system includes a controller configured to transfer first data for a program operation, and a memory device configured to perform an error check operation for determining whether second data received from the controller are equal to the first data and the program operation for storing the first data.

Abstract: A semiconductor system may include a memory device and a controller. The memory device may include a plurality of decks. Each of the decks may include word lines and bit lines alternately stacked. The controller may control an operation for data of the decks included in the memory device. The controller may include a counting circuit block for counting access numbers of the word lines and the bit lines. The counting circuit block may include a plurality of x-counting blocks corresponding to the word lines that are stacked a plurality of y-counting blocks corresponding to the bit lines that are stacked. The x-counting blocks may count access numbers of selected word lines in accordance with a selection signal of a corresponding deck among the decks. The y-counting block may count access numbers of selected bit lines in accordance with the selection signal of the corresponding deck.

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

Abstract: A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of the true and complementary transistors have less state values than the lower state value, generating a state value range based on a difference between the upper state value and the lower state value, and comparing the state value range to a threshold value to determine whether the plurality of complementary memory cells is in a blank state or a non-blank state. Other embodiments are also disclosed herein.

Abstract: A neuromorphic circuit, chip, and method are provided. The neuromorphic circuit includes a crossbar synaptic array cell. The crossbar synaptic array cell includes a Complimentary Metal-Oxide-Semiconductor (CMOS) transistor having an on-resistance controlled by a gate voltage of the CMOS transistor to update a weight of the crossbar synaptic array cell. The gate voltage of the CMOS transistor is controlled by performing a charge sharing technique that updates the weight of the crossbar synaptic array cell using non-overlapping pulses on control lines that are aligned with a set of row lines and a set of column lines.

Abstract: A memory device includes a command decoder and a status circuit. The command decoder decodes a command. The status circuit sequentially stores operation information of the memory device determined based on the decoded command and outputs at least one of the sequentially stored operation information in response to an output control signal.

Abstract: Data to store at a storage system is received. The storage system includes data blocks and the plurality of blocks that include a first region corresponding to a first storage density and a second region corresponding to a second storage density that is less dense than the first storage density. The data is stored at the first region of the plurality of data blocks that corresponds to the first storage density. A write attribute related to storing the data at the first region of the plurality of data blocks is determined. Thereupon, the write attribute related to storing the data at the first region is stored in the second region of the plurality of data blocks that corresponds to the second storage density.

Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

Abstract: A semiconductor storage device achieving stabilization of an operating voltage of a selected memory chip. A flash memory device of the disclosure includes a master chip and at least one slave chip. A voltage output portion of a charge pump circuit of the master chip is connected to an internal pad of the master chip, and a voltage output portion of a charge pump circuit of the slave chip is connected to an internal pad of the slave chip, the internal pad of the master chip and the internal pad of the slave chip are connected by a wire. When the mater chip is operated, the charge pump circuit of the master chip is turned off, the charge pump circuit of the slave chip is turned on, and a voltage generated by the charge pump circuit of the slave chip is supplied to the master chip.

Abstract: A memory device includes: a memory cell array including a plurality of memory cells respectively coupled to a plurality of word lines; a peripheral circuit configured to perform at least one program loop including applying a program voltage to selected memory cells coupled to a selected word line among the plurality of word lines and determining whether the selected memory cells have been completely programmed; and control logic configured to control the peripheral circuit to, while the program voltage is being applied to the selected word line, apply program control voltages of different levels to bit lines respectively coupled to memory cells in a first memory cell group among the selected memory cells and apply a program allowable voltage to bit lines respectively coupled to memory cells in a second memory cell group among the selected memory cells.

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

Abstract: Devices and techniques for performing copy-back operations in a memory device are disclosed herein. A trigger to perform a copy-back operation in relation to a section of data stored on the memory device can be detected. Circuitry of the memory device can then read the section of data at two voltage levels within a read window to obtain a first set of bits and a second set of bits respectively. The first and second sets of bits—which should be the same under normal circumstances—are compared to determine whether a difference between the sets of bits is beyond a threshold. If the difference is beyond a threshold, error correction is invoked prior to completion of the copy-back operation.

Abstract: A failure mode detection method is provided. A first default read voltage is changed to a first read retry voltage by a first increment, and a second default read voltage is changed to a second read retry voltage by a second increment. A memory cell array of a solid state storage device is successfully read according to the first and second read retry voltages. If an absolute value of the first increment minus an absolute value of the second increment is larger than a predetermined voltage value, the memory cell array is in a data retention failure mode. If the absolute value of the first increment minus the absolute value of the second increment is smaller than the predetermined voltage value, the memory cell array is in a low temperature write high temperature read failure mode.

Abstract: A memory sub-system can be determined to be operating within a target operating characteristic based on a threshold success rate associated with error control operations using a particular parameter. Upon determining that the memory sub-system is operating within the target operating characteristic, a sticky read mode is entered by performing subsequent read operations using the particular parameter. It is determined that additional error control operations are triggered for at least a first threshold number of read operations using the particular parameter during the sticky read mode. Upon determining that the additional error control operations are triggered for at least the first threshold number of read operations using the particular parameter during the sticky read mode, the sticky read mode is exited by performing further read operations using a default parameter associated with the memory sub-system.

Abstract: Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract: Apparatuses, systems, and methods are disclosed for adjusting a programming setting such as a programming voltage of a set of non-volatile storage cells, such as an SLC NAND array. The non-volatile storage cells may be arranged into a plurality of word lines. A subset of the non-volatile storage cells may be configured to store a programming setting. An on-die controller may be configured to read the programming setting from the setting subset, and write data to the non-volatile storage cells, using the programming setting. The on-die controller may further be configured to determine that the programming setting causes suboptimal programming of one or more of the non-volatile storage cells, and in response to the determination, store a revised programming setting on the setting subset.

Abstract: A method of operating a memory device having improved threshold voltage distributions of select transistors, the memory device including a plurality of cell strings each including a plurality of source select transistors, a plurality of memory cells, and a plurality of drain select transistors stacked in a vertical direction to a substrate include performing a first program operation to program at least one source select transistor coupled to a first source select line adjacent to a common source line, among the plurality of source select transistors, using a fixed program voltage, and performing a second program operation to program at least one source select transistor coupled to a second source select line adjacent to the first source select line, among the plurality of source select transistors, using an incremental step pulse program (ISPP) method after the first program operation is completed.

Abstract: The present subject matter relates to an electrical programmable read only memory (EPROM) cell. The EPROM cell comprises a semiconductor substrate and a floating gate separated from the semiconductor substrate by a first dielectric layer. A control gate is capacitively coupled to the floating gate through a second dielectric layer disposed between the floating gate and the control gate. In an example, the EPROM cell further comprises a conductive gate connected to the floating gate, wherein the conductive gate is to leak charges from the floating gate in a predetermined leak time period.

Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.

Abstract: Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.

Abstract: A data backup method for performing a post package repair (PPR) operation includes reading repair unit information of a memory device, storing the repair unit information in a register, determining whether to perform the PPR operation in response to a read error occurring while the memory device is being accessed, and performing a data backup operation of the memory device based on the repair unit information in response to determining that the PPR operation is to be performed.

Abstract: In a method of programming in a nonvolatile memory device, channels of a plurality of cell strings are precharged through ground selection transistors by a precharge voltage of a source line. A turn-on voltage is applied to a selected ground selection transistor of a selected cell string among the plurality of cell strings, during a verification read period of an N-th program loop. The turn-on voltage applied to the selected ground selection transistor is maintained to precharge the channels for an (N+1)-th program loop, without recovery after the verification read period of the N-th program loop is finished. Power consumption is reduced and an operation speed is increased by maintaining the turn-on voltage of the selected ground selection line to precharge the channels of the cell strings without recovery after the verification read operation is finished.

Abstract: Devices and techniques for an adjustable voltage drop detection threshold in a memory device are disclosed herein. A voltage drop detection threshold of a memory device is dynamically established. A power loss event is triggered when the supply voltage falls below the voltage drop detection threshold. An error parameter associated with performing multiple memory operations on the memory device is collected. The multiple memory operations are performed while applying a supply voltage at a second supply voltage level of the memory device which is less than a first supply voltage level established as a first operating voltage for the memory device. Determining whether the error parameter is below an allowable error threshold. In response to determining that the error parameter is below the allowable error threshold, the voltage drop detection threshold is established at a voltage level less than the first supply voltage level.

Abstract: A bit determining method, a memory control circuit unit and a memory storage device are provided. The method includes: reading a first storage state of a first memory cell to obtain a first value of a first significant bit; reading the first storage state of the first memory cell to obtain at least one second value of at least one second significant bit; performing a first decoding operation according to the at least one second value to obtain at least one third value of the decoded second significant bit; determining whether the first significant bit is a special bit according to the first storage state and a second storage state corresponding to the at least one third value; and if the first significant bit is the special bit, performing a corresponding decoding operation.

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable hybrid microcontroller having a state machine and one or more processors. The state machine is configured to generate a first set of execution signals in response to a request to perform memory operations on non-volatile memory cells in the memory system. The first set of execution signals have a format configured to interface with one or more circuits coupled to the non-volatile memory cells. The hybrid microcontroller has an interface that translates the first set of execution signals to instruction identifiers. The one or more processors execute instructions identified by the instruction identifiers to generate a second set of execution signals. The second set of execution signals are provided to the one or more circuits to perform the memory operations on the non-volatile memory cells.

Abstract: An operating method of a memory system includes: reading a first data from a particular data group among a plurality of data groups included in a memory device; performing a first error correction code (ECC) decoding for the first data; when the first ECC decoding fails, reading a plurality of the remaining data other than the first data from the particular data group; performing a second ECC decoding for the plurality of the remaining data; when the second ECC decoding fails, identifying data, to which the second ECC decoding fails, among the plurality of the remaining data; obtaining first and second soft read values respectively corresponding to the first data, to which the first ECC decoding fails, and the second data, to which the second ECC decoding fails; determining reliability of the first and second data based on the first and second soft read values; and correcting the first data based on the reliability of the first and second data.

Abstract: An electronic memory array includes a plurality of memory domains, a current controller, and a selector device. Each memory domain includes a plurality of bit cells. The current controller includes a current controller output electrically connectable to said plurality of memory domains and is configured to control a bit cell current. The selector device is electrically connected to the current controller and the plurality of memory domains. The selector device is configured to selectively electrically connect the current controller output to only a select one of said memory domains, such that the current controller controls only the bit cell current of the bit cells of the select memory domain.

Abstract: In a method of programming a three-dimensional nonvolatile memory device, a program loop is executed at least one time. The program loop includes a programming step for programming selected memory cells among memory cells and a verifying step for verifying whether the selected memory cells are program-passed or not. In programming the selected memory cells, a level of a voltage being applied to a common source line connected to the memory cells in common may be changed. Thus, in a program operation, power consumption which is needed to charge-discharge the common source line can be decreased while increasing boosting efficiency.

Abstract: A flash memory system may include a cell flash memory and a circuit for performing operations of the plurality of cells. The cell flash memory may have a plurality of cells. The circuit may be configured to estimate an interference state based on a result of a read operation on a first neighboring cell of a first cell among the plurality of cells. The circuit may be configured to perform a read operation on the first cell. The circuit may be configured to generate soft information based on a result of the read operation and the interference state. The circuit may be configured to decode the result of the read operation on the first cell based on the soft information.

Abstract: Disclosed herein is related to a system and a method of adjusting a programming pulse for programming memory cells. In one aspect, the system includes a controller that iteratively applies a programming pulse to the memory cells during programming loops. The programming pulse has progressively increasing magnitudes to program different subsets of the memory cells to corresponding target states. The controller determines that a programming loop to program a subset of the memory cells targeted to have a corresponding target state of the target states is performed. The controller counts a number of memory cells of the subset that have not reached the target state. The controller determines a magnitude for a programming pulse to be applied for a subsequent programming loop based on the counted number, and applies, during the subsequent programming loop, the programming pulse with the determined magnitude.

Abstract: An method of operating a nonvolatile memory device including a plurality of memory cells comprises receiving a read command from an external device, in response to the read command, performing, based on a reference voltage, a first cell counting operation with respect to the plurality of memory cells, adjusting at least one read voltage of first through nth read voltages (where n is a natural number greater than 1) based on a first result of the first cell counting operation, and performing, based on the adjusted at least one read voltage, a read operation corresponding to the read command with respect to the plurality of memory cells.

Abstract: Embodiments of 3D memory devices and methods for operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a NAND memory string and a peripheral circuit. The NAND memory string extends vertically above a substrate and includes a plurality of memory cells arranged vertically in series. The peripheral circuit is configured to program the memory cells based on incremental step pulse programming (ISPP). Different verification voltages of the ISPP are applied to at least two of the memory cells.

Abstract: An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second. The technique reduces or eliminates the number of previously programmed cells from being adversely incrementally programmed by an adjacent cell being programmed to higher program levels, and reduces the magnitude of adverse incremental programming for most of the memory cells, which is caused by floating gate to floating gate coupling. The memory device includes an array of non-volatile memory cells and a controller configured to identify programming values associated with incoming data, and perform a programming operation in which the incoming data is programmed into at least some of the non-volatile memory cells in a timing order of descending value of the programming values.

Abstract: A data storage device includes a nonvolatile memory device including an address map table in which a plurality of map segments including a plurality of logical-to-physical (P2L) entries are stored and a controller controlling the nonvolatile memory device. The controller includes a processor and a memory storing a map update module configured to be driven through the processor and perform map updating on the plurality of map segments. The map update module divides each of the map segments into a plurality of sub segments, updates a first sub segment as an updating target among the plurality of sub segments by loading the first sub segment into a map update buffer of the memory, and encodes second sub segments as a non-updating target among the plurality of sub segments and stores the encoded second sub segments in a page buffer of the nonvolatile memory device.

Abstract: Apparatuses and methods determine a length of a longest element in a memory. An example method comprises determining, using a controller to control sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array.

Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.

Abstract: A semiconductor memory device may include a memory cell array, a peripheral circuit and a control logic. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a program operation on a selected memory block among the memory blocks. The control logic may control the program operation of the peripheral circuit. The selected memory block may be coupled with a plurality of bit lines, and the bit lines may be grouped into a first bit line group and a second bit line group based on programming speeds of memory cells coupled to the bit lines that are grouped into the first and second bit line groups. During a blind program operation of the selected memory block, the control logic may control the peripheral circuit to apply different program permission voltages to bit lines of at least two bit line groups.

Abstract: A method of data writing for a data storage device includes steps of: determining whether an event of power drop/loss is recorded, wherein the event of power drop/loss is associated with a power supplied by an external device; when it is determined that the event of power drop/loss is recorded, determining whether a backup power source operates abnormally; and when it is determined that the backup power source operates abnormally, the data storage device enters from a normal mode into a write through mode, wherein in the write through mode, data from the external device is written into a buffer area of the data storage device. A data storage device is also provided.

Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator can be read. Responsive to determining that the status indicator cannot be read, it can be determined that programming of data to the data block of the memory component did not complete based on a prior loss of power to the memory component.

Abstract: Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.

Abstract: A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and second inputs and an output. For each of the differential sense amplifiers, the differential sense amplifier is configured to generate an output signal on the output having an amplitude that is based upon a difference in signal amplitudes on the first and second inputs, the first input is connected to one of the bit lines, and the second input is connected to another one of the bit lines. Alternately, one or more sense amplifiers are configured to detect signal amplitudes on the bit lines, and the device includes calculation circuitry configured to produce output signals each based upon a difference in signal amplitudes on two of the bit lines.