Parallel Row Lines (e.g., Page Mode) Patents (Class 365/185.12)
  • Patent number: 11081182
    Abstract: An integrated circuit and a computing method thereof are provided. The integrated circuit includes a memory array, word lines, bit lines and a page buffer. The memory array includes memory cells, each configured to be programmed with a weight. The word lines respectively connect a row of the memory cells. The bit lines are respectively connected with a column of the memory cells that are connected in series. More than one of the bit lines in a block of the memory array or more than one of the word lines in multiple blocks of the memory array are configured to receive input voltages. The memory cells receiving the input voltages are configured to multiply the weights stored therein and the received input voltages. The page buffer is coupled to the memory array, and configured to sense products of the weights and the input voltages.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: August 3, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hang-Ting Lue
  • Patent number: 11043274
    Abstract: Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: June 22, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yonghyuk Choi, Jae-Duk Yu, Kang-Bin Lee, Sang-Won Shim, Bongsoon Lim
  • Patent number: 11037983
    Abstract: The present disclosure provides a semiconductor structure, including a transistor layer, a memory region over the transistor layer, and a logic region adjacent to the memory region. The memory region includes a first Nth metal line, a magnetic tunneling junction (MTJ) over the first Nth metal line, a cap over the MTJ, a first stop layer on the cap; and a first (N+1)th metal via over the MTJ. The first (N+1)th metal via is laterally surrounded by the cap and the first stop layer. The logic region includes a second Nth metal line, a second stop layer being disposed over an (N+1)th metal line, and a second (N+1)th metal via over the (N+1)th metal line. N is an integer greater than or equal to 1. A method of manufacturing the semiconductor structure is also disclosed.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chern-Yow Hsu, Yuan-Tai Tseng, Shih-Chang Liu
  • Patent number: 11031084
    Abstract: A memory device, in accordance with a method of operation, may include: a plurality of pages coupled to a common word line and configured to be sequentially selected by different select lines; a program operation controller configured to perform a program operation on a first page that is to be programmed first, among the plurality of pages; and a start loop manager configured to generate start loop information about a program loop in which program verification corresponding to each of a plurality of program states to be formed by threshold voltages of memory cells included in the first page starts, during the program operation on the first page. The program operation controller is further configured to perform a program operation on a second page to be programmed subsequent to the first page, among the plurality of pages, based on the start loop information.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: June 8, 2021
    Assignee: SK hynix Inc.
    Inventors: Jong Hoon Lee, Se Chun Park
  • Patent number: 11011211
    Abstract: A semiconductor storage device includes a plurality of memory cells and a plurality of bit lines connected thereto, a plurality of sense amplifier units respectively connected to the plurality of bit lines, and a cache memory connected to the plurality of sense amplifier units. Each sense amplifier unit includes a sense node and a latch in which data transferred onto the sense node from a corresponding bit line is latched. First data latched in a first sense amplifier unit among the plurality of sense amplifier units is transferred to the cache memory, and second data latched in a second sense amplifier unit among the plurality of sense amplifier units is transferred to the sense node of the first second sense amplifier unit. Thereafter, the second data is latched in the first sense amplifier unit and transferred to the cache memory.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: May 18, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Hiromitsu Komai
  • Patent number: 11010065
    Abstract: A read retry method for a solid state storage device is provided. The solid state storage device is in communication with a host. The solid state storage device includes a non-volatile memory. The read retry method includes the following steps. Firstly, the solid state storage device judges whether a specified read block of the non-volatile memory is in a specified failure mode. If the specified read block of the non-volatile memory is in the specified failure mode, a failure mode read retry process corresponding to the specified failure mode is performed. If an accurate read data is acquired in the failure mode read retry process, the accurate read data is transmitted to the host. If the accurate read data is not acquired in the failure mode read retry process, a read fail message is sent to the host.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: May 18, 2021
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventor: Chih-Yuan Hu
  • Patent number: 10996862
    Abstract: A data storage system performs operations including determining an endurance level of a block of memory cells; adjusting a read performance profile for the block of memory cells based on the determined endurance level; receiving a data read command specifying data to be read from a particular memory cell of the block of memory cells; and in response to the data read command, performing a read operation on the particular memory cell using the adjusted read performance profile.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: May 4, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Phil Reusswig, Mohsen Purahmad, Sahil Sharma, Rohit Sehgal, Niles Yang
  • Patent number: 10984869
    Abstract: A memory device includes: a memory block including a plurality of main pages and a dummy page; a peripheral circuit for performing a normal program operation on the plurality of main pages and a dummy program operation on the dummy page in a program operation, and reading data stored in the dummy page and the plurality of main pages in a read operation; and control logic for controlling the peripheral circuit to program, to the dummy page, the same data as first logical page data of a first main page among the plurality of main pages in the program operation.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: April 20, 2021
    Assignee: SK hynix Inc.
    Inventors: Sung Ho Kim, Jong Han Ahn, Seong Cheon Yu
  • Patent number: 10977121
    Abstract: A memory device such as a page mode NAND flash is operated, using a first pipeline stage, to clear a page buffer to a second buffer level, and transfer a page to the page buffer; a second pipeline stage to clear the second buffer level to the third buffer level and transfer the page from the page buffer to the second buffer level; a third pipeline stage to move the page to the third buffer level and execute in an interleaved fashion a first ECC function over data in a first part of the page and output the first part of the page while performing an second ECC function, and to execute the first ECC function over data in a second part of the page in the third buffer level, and to output the second part while performing the second ECC function.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: April 13, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shuo-Nan Hung, Chun-Hsiung Hung
  • Patent number: 10978161
    Abstract: A memory system, a memory controller and a memory device. In a set operation, by applying different pass voltages to at least one first word line and at least one second word line among the plurality of word lines excluding a selected target word line, an operation error of the memory device may be prevented.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Young Il Jung
  • Patent number: 10963393
    Abstract: A method for accessing a storage system, the method may include receiving a block call, from a processor that executes an application and by a storage engine of a computer that is coupled to a storage system; generating, by the storage engine and based on the block call, a key value call; and sending the key value call to a key value frontend of the storage system.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: March 30, 2021
    Assignee: Lightbits Labs Ltd.
    Inventors: Shmuel Ben-Yehuda, Ofir Efrati, Abel Alkon Gordon, Eran Kirzner, Fabian Trumper
  • Patent number: 10957384
    Abstract: A memory device such as a page mode NAND flash, including a page buffer with first and second-level buffer latches is operated using a first pipeline stage, to transfer a page to the first-level buffer latches; a second pipeline stage, to clear the second-level buffer latches to a third buffer level and transfer the page from the first-level buffer latches to the second-level buffer latches; and a third pipeline stage to move the page to the third buffer level and execute in an interleaved fashion a first ECC function over data in a first part of the page and output the first part of the page while performing a second ECC function, and to execute the first ECC function over data in a second part of the page in the third buffer level, and to output the second part while performing the second ECC function.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: March 23, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ji-Yu Hung, Shuo-Nan Hung
  • Patent number: 10923163
    Abstract: Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Peter Sean Feeley
  • Patent number: 10915254
    Abstract: Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventors: Kunal A. Khochare, Camille C. Raad, Richard P. Mangold, Shachi K. Thakkar
  • Patent number: 10910073
    Abstract: A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: February 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Yoshihisa Kojima
  • Patent number: 10910076
    Abstract: Techniques are provided for mitigating issues of memory hole mis-shape. In one aspect, one or more control circuits are configured to program a group of non-volatile memory cells from an erase state to a plurality of programmed states using a first program parameter. The one or more control circuits measure threshold voltages of the group to determine a severity of memory hole mis-shape in the group. The one or more control circuits program the group from the erase state to the plurality of programmed states using a second program parameter selected based on the severity of the memory hole mis-shape in the group.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: February 2, 2021
    Assignee: SanDisk Technologies LLC
    Inventor: Xiang Yang
  • Patent number: 10910066
    Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: February 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Tsukasa Tokutomi, Marie Takada
  • Patent number: 10910065
    Abstract: A memory system includes a memory device configured to store data, and read and output the stored data in a read operation, and a memory controller configured to perform an error correction operation on the data received from the memory device in the read operation and control the memory device to perform a read retry operation, based on the result of the error correction operation. The memory device outputs the data read in the read retry operation to the memory controller when the number of specific data, among data read in the read retry operation, is in a set range. Only reliability-ensured data in the read retry operation is output to the memory controller. Thus, the number of times of outputting data to the memory controller can be decreased, and the number of times where the memory controller performs an error correction operation can be decreased.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: February 2, 2021
    Assignee: SK hynix Inc.
    Inventor: Jiman Hong
  • Patent number: 10902926
    Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: January 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sun Min, Vivek Venkata Kalluru, Tae-hong Kwon, Ki-won Kim, Sung-whan Seo, Bilal Ahmad Janjua
  • Patent number: 10878923
    Abstract: A partial page sensing method and system are provided in which, while a bit line voltage (VBLC) is applied to first bit lines of a first partial page of a memory cell array, second bit lines, of a second partial page are floated. The second bit lines of the second partial page are bit lines which are interleaved with the first bit lines of the first partial page. Bit lines associated with one or more additional partial pages may be grounded or floated. A bit line associated with an additional partial page which is adjacent to one of the first bit lines may be floated.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: December 29, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Yu-Chung Lien
  • Patent number: 10867681
    Abstract: A memory device includes an array of memory cells that has a first sub array and a second sub array. A plurality of bit lines are connected to the memory cells, and an IO block is situated between the first sub array and the second sub array. The bit lines extend from the first and second memory sub arrays of the memory device directly to the IO block. The IO block further includes data input and output terminals configured to receive data to be written to the array of memory cells and output data read from the array of memory cells via the plurality of bit lines.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, LTD.
    Inventors: Michael Clinton, Bryan David Sheffield, Marty Tsai, Rajinder Singh
  • Patent number: 10831395
    Abstract: According to one embodiment, a memory system includes a memory and a controller electrically connected to the memory. The memory includes blocks. Each of the blocks includes one or more sub-blocks. Each of the one or more sub-blocks includes nonvolatile memory cells. The controller is configured to obtain read frequency of at least one of the sub-blocks, and move data stored in the at least one of the sub-blocks so that data having substantially the same read frequency are written into one block.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: November 10, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Riki Suzuki, Yoshihisa Kojima, Toshikatsu Hida
  • Patent number: 10824182
    Abstract: A semiconductor integrated circuit includes a first power supply line, a second power supply line, and a voltage supplied circuit. The first power supply line is connected to a voltage supply source. The second power supply line is connected to the first power supply line at a connection point connecting a first point of the first power supply line and a second point of the second power supply line. The second point is included in a portion of the second power supply line excluding end portions of the second power supply line. The voltage supplied circuit is connected to the second power supply line.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: November 3, 2020
    Assignee: Ricoh Company, Ltd.
    Inventors: Sho Kamezawa, Tohru Kanno
  • Patent number: 10789125
    Abstract: A memory system includes a plurality of memory cells and a controller. During a write operation to write data to the memory cells, the controller encodes first data to be written at a first code rate. During a read operation to read data from the memory cells, the controller decodes second data read from the memory cells at the first code rate. The controller changes the first code rate to a second code rate that is less than the first code rate upon determining that the number of error bits during the read operation of the second data is above a threshold number for error bits or upon determining that the number of memory cells having a threshold voltage that is in a voltage range that includes a read voltage is above a threshold number for memory cells.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: September 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsuhiko Ueki, Sumio Kuroda, Yasuyuki Ozawa
  • Patent number: 10762963
    Abstract: A semiconductor memory device comprises a first memory cell array including a first memory cell and a second memory cell array including a second memory cell, a first transistor electrically connectable to a first end of the first memory cell via a first source line, a second transistor connectable to a first end of the second memory cell via a second source line, a pad supplied with a reference voltage from outside, a first wiring that electrically connects the first transistor and the pad, and a second wiring that is different from the first wiring and electrically connects the second transistor and the pad.
    Type: Grant
    Filed: September 2, 2018
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuki Shimizu, Yoshihiko Kamata, Tsukasa Kobayashi, Hideyuki Kataoka, Koji Kato, Takumi Fujimoto, Yoshinao Suzuki, Yuui Shimizu
  • Patent number: 10755791
    Abstract: According to an embodiment, a semiconductor storage device includes a first memory cell and a control circuit. The first memory cell is configured to store first data. The control circuit is configured to apply a first voltage to a source of the first memory cell in a read operation of the first data in the first memory cell, and to apply a second voltage to the source of the first memory cell in a verify operation of the first data in the first memory cell. The second voltage is lower than the first voltage.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: August 25, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihiko Kamata, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi
  • Patent number: 10732874
    Abstract: A method for operating a memory system includes: detecting a first erase page of a super block, which is formed of memory blocks, by scanning the super block according to a binary search scheme based on a program order in which pages in the super block are programmed; and performing a Sudden Power Off Recovery (SPOR) based on the detected first erase page.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventor: Jang-Hwan Jun
  • Patent number: 10726925
    Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 28, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Murong Lang, Zhenming Zhou, Deepanshu Dutta
  • Patent number: 10720214
    Abstract: A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wen Tseng, Tsung-Yu Yang, Chung-Jen Huang
  • Patent number: 10720207
    Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: July 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong Sung Cho, Jeung Hwan Park, Jong Min Kim, Jung Kwan Kim
  • Patent number: 10706919
    Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: July 7, 2020
    Assignees: Toshiba Memory Corporation, SanDisk Technologies LLC
    Inventors: Tomoharu Tanaka, Jian Chen
  • Patent number: 10665308
    Abstract: Provided herein is a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of pages; a voltage supply unit configured to provide operating voltages to the plurality of pages; a plurality of page buffers coupled to a plurality of bit lines of the memory cell array and configured to control and sense currents flowing through the plurality of bit lines in response to a page buffer sensing signal; and a control logic configured to control the voltage supply unit and the plurality of page buffers such that the plurality of pages are successively programmed, and to control a potential level of the page buffer sensing signal depending on a program sequence of the plurality of pages during a program verify operation of a program operation.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: May 26, 2020
    Assignee: SK hynix Inc.
    Inventor: Won Hee Lee
  • Patent number: 10650895
    Abstract: Memory device having a tile architecture are disclosed. The memory device may include a first plane having multiple pairs of tiles, wherein at least some of the pairs of tiles of the first plane include a distributed block select circuit and page buffer circuitry. Another memory device may include a memory array, and a CMOS under array region. At least some tile regions may include portions of a total amount of block select circuitry distributed throughout the CUA region, vertical string drivers located outside of the memory array, and page buffer circuitry coupled with the memory array. Another memory device may include a first tile pair including a first tile, a second tile, a first vertical string driver therebetween, a first page buffer region that is greater than 50% of area for the first tile pair, and a first portion of a distributed block select circuitry.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Eric N. Lee
  • Patent number: 10642535
    Abstract: A memory system, architecture, and method for storing data in response to commands received from a host is disclosed. The memory system includes a memory control circuit configured to receive commands from the host; at least one memory device configured to store data; and at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register. The system preferably includes communication links between the host, the at least one memory control circuit, the at least one data buffer circuit, and the at least one memory device. The system preferably is configured so that register access commands are sent by the host to the memory control circuit over the communication links between the host and the memory control circuit.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Markus Cebulla, Susan M. Eickhoff, Logan I. Friedman, Patrick J. Meaney, Walter Pietschmann, Nicholas Rolfe, Gary A. Van Huben
  • Patent number: 10643704
    Abstract: A semiconductor memory device includes a memory structural body including first and second planes each of which includes memory cells coupled to word lines extending in a first direction and bit lines extending in a second direction and which are disposed along the first direction; and a logic structural body disposed between a substrate and the memory structural body, and including a row decoder. The row decoder includes a pass transistor circuit which is coupled in common to the first and second planes and a block switch circuit which controls the pass transistor circuit. The block switch circuit is disposed in first and second plane regions of the logic structural body which overlap with the first and second planes in a third direction perpendicular to the first and second directions, and the pass transistor circuit is disposed in an interval region between the first and second plane regions.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: May 5, 2020
    Assignee: SK hynix Inc.
    Inventors: Sung-Lae Oh, Dong-Hyuk Kim, Soo-Nam Jung
  • Patent number: 10636482
    Abstract: Methods of operating a memory include receiving a plurality of digits of data for programming to a plurality of memory cells of the memory, redistributing the received plurality of digits of data in a reversible manner to generate a plurality of digits of redistributed data each corresponding to a respective memory cell of the plurality of memory cells, and for each memory cell of the plurality of memory cells, programming the corresponding digit of redistributed data for that memory cell to a first digit position of a respective data state of that memory cell, programming a second digit of data having a first data value to a second digit position of the respective data state of that memory cell, and programming a third digit of data having a second data value to a third digit position of the respective data state of that memory cell.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: April 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Preston A. Thomson, Peiling Zhang, Junchao Chen
  • Patent number: 10628257
    Abstract: A memory management method for a storage device having a rewritable non-volatile memory module is provided, wherein the rewritable non-volatile memory module has a plurality of physical units, and each of the physical units has a plurality of word-lines. The method includes: performing a first checking operation on a target physical unit among the physical units according to an occurrence of a specific event; and determining whether a first operation needs to be performed on valid data in the target physical unit according to a checking result of the first checking operation that corresponds to the target physical unit.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: April 21, 2020
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventors: Yu-Hua Hsiao, Chia-Wei Chang
  • Patent number: 10614889
    Abstract: An erase voltage is applied to channels of a selected string group to erase only the selected string group. A size and a number of the spare blocks for storing meta data are reduced and thus a size of the nonvolatile memory device is reduced by reducing unit capacity of the erase operation through grouping of the cell strings. Lifetime of the nonvolatile memory device is extended by having control over erasing some cell strings and not others. Control of cell strings for erasure includes allowing some control lines to float, in some embodiments. In some embodiments, ground select transistors with different thresholds and appropriately applied voltages are used to control erasure of particular cell strings. In some embodiments, biasing of word lines is applied differently to portions of a particular cell string to only erase a portion of the particular cell string.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kui-Han Ko, Jin-Young Kim, Bong-Soon Lim, Il-Han Park
  • Patent number: 10614900
    Abstract: A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least eight threshold voltages, a first bit line connected to the first memory cell, a word line connected to a gate of the first memory cell, a sense amplifier connected to the first bit line, wherein the sense amplifier has at least four data latch circuits, and an extra data latch circuit connected to the sense amplifier through a data bus. A verification operation for verifying the threshold voltage of the first memory cell is performed after a programming operation is performed on the first memory cell, and the verification operation includes seven verification operations during which the four data latch circuits, but not the extra data latch circuit, are accessed.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: April 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi Maejima, Noboru Shibata
  • Patent number: 10600488
    Abstract: A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: March 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho Song, Se-heon Baek, Yong-sung Cho
  • Patent number: 10580499
    Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: March 3, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Pang Lu, Chi-Hsiu Hsu, Chung-Hao Chen, Ya-Nan Mou, Chung-Cheng Tsai
  • Patent number: 10552316
    Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe D'Eliseo, Luigi Esposito, Xinghui Duan, Lucia Santojanni, Massimo Iaculo
  • Patent number: 10541031
    Abstract: A program circuit may two-dimensionally program data into cells by applying different selected bit line or channel voltages to different bit lines or channels located in different bit line zones of a block during a program operation. The block may be further separated or divided into word line zones. The program circuit may adjust the different bit line or channel voltages as it programs in different word line zones of the block. In accordance with the two-dimensional programming, the program circuit may perform single-pulse program-only SLC program operations.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: January 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mohan Vamsi Dunga, Piyush Dak, Pitamber Shukla
  • Patent number: 10504599
    Abstract: Programming methods include programming first and second data in first and second memory cells, reading the first data from the first memory cell by applying a read voltage to an access line connected to the first and second memory cells while the first memory cell is electrically connected to a data line and while the second memory cell is electrically disconnected from the data line, reading the second data from the second memory cell by electrically disconnecting the first memory cell from the data line and electrically connecting the second memory cell to the data line while the read voltage remains applied to the access line, and programming the read first data and the read second data in a single memory cell connected to a different access line.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: December 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Ramin Ghodsi, Toru Tanzawa
  • Patent number: 10460776
    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a column selection circuit, a sensing circuit, an output circuit, and a verification circuit. The column selection circuit selects n-bit data from data read from a memory cell array according to a column selection signal and outputs the selected n-bit data to an n-bit data bus. The sensing circuit senses the n-bit data on the data bus in response to an activation signal. The output circuit selects m-bit data from the n-bit data sensed by the sensing circuit in response to an internal clock signal synchronized with a serial clock signal applied from outside and outputs the selected m-bit data from output terminals. The verification circuit compares the data sensed by the sensing circuit with the data output by the output circuit to verifying the correctness of read-out data.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: October 29, 2019
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Hidemitsu Kojima
  • Patent number: 10418113
    Abstract: A NAND flash memory suppresses an influence caused by FG coupling and has high reliability. The flash memory of the invention includes: a memory array formed with a plurality of NAND strings; a row selection unit selecting rows of the memory array; and a bit line selection circuit (200) selecting even-numbered pages or odd-numbered pages of the selected row. The even-numbered pages (BL0, BL1, BL4, BL5) include a plurality of pairs of adjacent bit line pairs, the odd-numbered pages (BL2, BL3, BL6, BL7) include a plurality of pairs of adjacent bit line pairs, and the bit lines of the even-numbered page and the bit lines of the odd-numbered page are arranged alternately.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 17, 2019
    Assignee: Windbond Electronics Corp.
    Inventor: Naoaki Sudo
  • Patent number: 10409499
    Abstract: According to one embodiment, a semiconductor memory device includes a memory string including first and second selection transistors, a first transistor, and first and second memory cell transistors, first and second selection gate lines, first to third word lines, and a row decoder. A write operation includes a first mode to write one-bit data and a second mode to write two-bit data. In a case of writing the one-bit data to the first memory cell transistor in the first mode, the row decoder applies a first voltage to the first word line. In a case of writing the two-bit data to the first memory cell transistor in the second mode, the row decoder applies, to the first word line, a second voltage that is higher than the first voltage.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: September 10, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Keita Kimura
  • Patent number: 10394682
    Abstract: A system is described for identifying key lock contention issues in computing devices. A computing device is executed and lock contention information relating to operations during execution of the computing device is recorded. The data is parsed and analyzed to determine blocking relationships between operations due to lock contention. Algorithms are implemented to analyze dependencies between operations based on the data and to identify key areas of optimization for performance improvement. Algorithms can be based on the Hyperlink-Induced Topic Search algorithm or the PageRank algorithm.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: August 27, 2019
    Assignee: VMware, Inc.
    Inventors: Jiaojiao Song, Zhelong Pan, Inna Rytsareva
  • Patent number: 10365855
    Abstract: A controller includes: a first buffer suitable for buffering data read from a memory device; a second buffer suitable for buffering data to be written into the memory device; a processor suitable for, in response to a read command, controlling the memory device to read data therefrom and the first buffer to buffer the read data; and a buffer management unit suitable for, in response to the read command, providing the buffered data of the first buffer when the second buffer does not currently buffer data to be read.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: July 30, 2019
    Assignee: SK hynix Inc.
    Inventor: Byeong-Gyu Park
  • Patent number: 10324839
    Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley