Bank Or Block Architecture Patents (Class 365/185.11)
  • Patent number: 9299447
    Abstract: A semiconductor device includes a plurality of memory blocks, wherein each of the plurality of memory blocks includes a first select transistor electrically coupled to a common source line, a second select transistor electrically coupled to a bit line, and a plurality of memory cells electrically coupled between the first and second select transistors, and an operation circuit suitable for applying operation voltages for a program operation, a read operation, and an erase operation to a selected memory block selected from the plurality of memory blocks, and applying a first positive voltage to gates of the first select transistors in unselected memory blocks of the plurality of memory blocks when an erase voltage is applied to the common source line during the erase operation.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: March 29, 2016
    Assignee: SK Hynix Inc.
    Inventors: Yeonghun Lee, Hyun Heo, Min Gyu Koo, Dong Hwan Lee
  • Patent number: 9286213
    Abstract: A file management system for managing a file using a logical erase block (LEB) corresponding to a physical erase block (PEB). The file management system includes a free LEB list storing a free LEB allowing writing on all pages; a dirty LEB list storing a dirty LEB that is not the free LEB; and an obsolete area determining module determining an obsolete area in at least one dirty LEB, by referring to a block table storing information about whether or not at least one block is being used and according to whether or not the at least one dirty LEB is mapped to a PEB.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: March 15, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Han Sung Chun
  • Patent number: 9286994
    Abstract: Read disturb is reduced for dummy memory cells in a charge-trapping memory device such as a 3D memory device. The memory device includes a selected NAND string and an unselected NAND string. In the unselected NAND string, a dummy memory cell is adjacent to a select gate transistor. During a read operation involving the selected NAND string, a voltage of the dummy memory cell is increased in two steps to minimize a gradient in a channel of the unselected NAND string between the dummy memory cell and the select gate transistor. During the first step, the select gate transistor is conductive so that the channel is connected to a driven bit line. During the second step, the select gate transistor is non-conductive. Voltages on unselected word lines can also be increased in two steps to set a desired channel boosting level in the unselected NAND string.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: March 15, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Hong-Yan Chen, Yingda Dong, Wei Zhao
  • Patent number: 9281070
    Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: March 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Won-Taeck Jung, Junghoon Park
  • Patent number: 9281019
    Abstract: A three-dimensional semiconductor device includes bit lines provided on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel pipes connecting the bit lines to the common source line. Each of the channel pipes may include a pair of vertical portions extending through the gate structure and a horizontal portion connecting the vertical portions. The pair of vertical portions are provided under a pair of the bit lines arranged adjacent to each other, respectively.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: March 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jintaek Park, Youngwoo Park
  • Patent number: 9275737
    Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: March 1, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi Maejima
  • Patent number: 9275748
    Abstract: A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, a control gate disposed over the floating gate, and an erase gate disposed over the first region. The method includes placing a small positive voltage on the unselected source lines, and/or a small negative voltage on the unselected word lines, during the read operation to suppress sub-threshold leakage and thereby improve read performance.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: March 1, 2016
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Nhan Do, Steven Malcolm Lemke, Jinho Kim, Jong-Won Yoo, Alexander Kotov, Yuri Tkachev
  • Patent number: 9263154
    Abstract: A method for evaluating a chip manufacturing process is described comprising measuring, for each of a plurality of chips manufactured in a chip manufacturing process, a bit failure rate of the chip, determining a distribution of bit failure rates from the measured bit failure rates; determining a maximum allowed bit failure rate from a given chip failure rate limit, determining a value representing the probability that a chip manufactured in the chip manufacturing process is below the maximum allowed bit failure rate and determining, based on the value, whether the chip manufacturing process is suitable for the chip failure rate limit.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: February 16, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Georg Tempel
  • Patent number: 9257166
    Abstract: Disclosed is a current sense amplifier suitable for a nonvolatile memory device such as a magnetic random access memory. In the current sense amplifier, a reference memory cell for sensing is implemented by a memory cell equal to a normal memory cell without fabricating different reference memory cells. The current sense amplifier is formed of first and second cross coupled differential amplifiers being covalent bonded. The current sense amplifier compares a current flowing to a sensing node of a memory cell directly with currents flowing to reference sensing nodes.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: February 9, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chankyung Kim, Dong-Seok Kang, Yunsang Lee, Soo-Ho Cha
  • Patent number: 9251889
    Abstract: In one embodiment, a self-timed, dual-rail SRAM includes a self-timing circuit having a logic gate that is powered by voltage VDD and configured to receive a fire-sense-amplifier timing signal and to produce a VDD-domain sense-amplifier-enable signal SOELV. The self-timing circuit includes an inverting level-shifter having complementary N-type and P-type transistors connected in series between voltage VDDA and ground. The N-type transistor's gate is connected to signal SOELV, and both transistors' drain terminals are connected together to produce output signal SOEHVB. The inverting level-shifter also includes two series-connected P-type transistors connected (i) between supply voltage VDDA and the output and (ii) in parallel with the first P-type (pull-up) transistor. An inverter is connected between the output node and the control terminal of one of the series transistors, and the other series-transistor's gate is connected to signal SOELV.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: February 2, 2016
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Ankur Goel, Dharmendra Kumar Rai, Sumith Kaippalathingal Soman
  • Patent number: 9245644
    Abstract: A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: January 26, 2016
    Assignee: Macronix International Co., Ltd
    Inventors: Chun-Hsiung Hung, Bo-Chang Wu, Kuen-Long Chang, Ken-Hui Chen
  • Patent number: 9245630
    Abstract: A memory system includes a nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device such that memory cells connected with a selected row of the nonvolatile memory device are programmed by one of a first program mode and a second program mode. At the first program mode, a plurality of logical pages corresponding in number to a maximum page number is stored at the memory cells, and at the second program mode, one or more logical pages the number of which is less than the maximum page number are stored at the memory cells using a bias condition that is different from that used in the first program mode.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: January 26, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Donghun Kwak, Kitae Park
  • Patent number: 9240239
    Abstract: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: January 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Hwa Kang, Sang-Wan Nam, Donghyuk Chae, ChiWeon Yoon
  • Patent number: 9240243
    Abstract: A method for managing a flash memory device including pages of memory cells is described. The memory device may be erasable at the page level, and the pages may include operative pages for storing operative values and service pages for storing information relating to the erasing of the operative pages. In response to a request to erase selected operative pages, the method may include determining a service page in use among the service pages according to service information stored in the service pages, verifying the presence a service page to be erased, and applying an erasing pulse to each service page to be erased. The method may also include writing an address of the operative pages into the service page in use, erasing the selected operative pages, and writing a completion indication of the erasing of the selected operative pages into the service page in use.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: January 19, 2016
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Giovanni Matranga, Mario Micciche, Rosario Roberto Grasso
  • Patent number: 9230681
    Abstract: A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: January 5, 2016
    Assignee: Apple Inc.
    Inventors: Dotan Sokolov, Naftali Sommer, Uri Perlmutter, Ofir Shalvi
  • Patent number: 9218242
    Abstract: Data that is stored in a higher error rate format in a nonvolatile memory is backed up in a lower error rate format. Data to be stored may be transferred once to on-chip data latches where it is maintained while it is programmed in both the high error rate format and the low error rate format without being resent to the nonvolatile memory.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: December 22, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Chris Nga Yee Avila, Gautam Ashok Dusija, Jian Chen, Mrinal Kochar, Abhijeet Manohar
  • Patent number: 9218277
    Abstract: A method for operating a computer memory. The memory is organized to store data in units of such memory. For each unit of a set of units a wear level of the unit is determined. A maximum wear level among the wear levels is determined. A suggestion of a subset of one or more units for being selected for data erasure is received and at least one unit in the subset is identified for subsequent data erasure, a wear level (c(i)) of which units (i) is less than the maximum wear level (c_max).
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: December 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: Giovanni Cherubini, Ilias Iliadis
  • Patent number: 9218853
    Abstract: A control method for a nonvolatile memory device with a vertically stacked structure is provided. The nonvolatile memory device includes a substrate, a common source line formed on the substrate, and plural memory blocks disposed over the substrate. Each memory block includes a cell string connected between a bit line and the common source line. Firstly, a first memory block of the plural memory blocks is selected as an active memory block, and one of the remaining memory blocks is selected as a second memory block. Then, a ground voltage is provided to the bit line of the second memory block, and the cell string of the second memory block is conducted, so that the ground voltage is transmitted from the bit line to the common source line through the cell string.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: December 22, 2015
    Assignee: LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chrong-Jung Lin, Hsin-Wei Pan
  • Patent number: 9218890
    Abstract: When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: December 22, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Chris Nga Yee Avila, Gautam Ashok Dusija, Jian Chen, Yingda Dong, Man Lung Mui, Seungpil Lee, Alexander Kwok-Tung Mak
  • Patent number: 9214210
    Abstract: A block decoder including a first selection unit configured to receive a block address signal and output a block select signal to any one of a plurality of blocks, and a second selection unit configured to receive a high voltage and control a potential level of the block select signal according to the block address signal.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: December 15, 2015
    Assignee: SK Hynix Inc.
    Inventor: Gyo Soo Chu
  • Patent number: 9208833
    Abstract: Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: December 8, 2015
    Assignee: Micron Technology
    Inventors: Koji Sakui, Peter Sean Feeley
  • Patent number: 9202874
    Abstract: A gallium nitride (GaN) device with leakage current-based over-voltage protection is disclosed. The GaN device includes a drain and a source disposed on a semiconductor substrate. The GaN device also includes a first channel region within the semiconductor substrate and between the drain and the source. The GaN device further includes a second channel region within the semiconductor substrate and between the drain and the source. The second channel region has an enhanced drain induced barrier lowering (DIBL) that is greater than the DIBL of the first channel region. As a result, a drain voltage will be safely clamped below a destructive breakdown voltage once a substantial drain current begins to flow through the second channel region.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: December 1, 2015
    Assignee: RF Micro Devices, Inc.
    Inventor: Andrew P. Ritenour
  • Patent number: 9196367
    Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: November 24, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Yu-Hsiung Tsai, Chun-Yuan Lo
  • Patent number: 9196317
    Abstract: A semiconductor device includes a first memory block including first vertical strings, a second memory block including second vertical strings coupled in series with the first vertical strings, wherein the second memory block is stacked on the first memory block, first bit lines located between the first memory block and the second memory block and electrically coupled to the first and second vertical strings, first source lines located under the first memory block and electrically coupled to the first vertical strings, and second source lines located above the second memory block and electrically coupled to the second vertical strings.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: November 24, 2015
    Assignee: SK Hynix Inc.
    Inventor: Seiichi Aritome
  • Patent number: 9190151
    Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: November 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Won-Taeck Jung
  • Patent number: 9183945
    Abstract: In a nonvolatile NAND memory array, a NAND block may be falsely determined to be in an erased condition because of the effect of unwritten cells prior to the erase operation. Such cells may be programmed with dummy data prior to erase, or parameters used for a verify operation may be modified to compensate for such cells. Read operations may be similarly modified to compensate for unwritten cells.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 10, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Chris Nga Yee Avila, Yingda Dong, Man Lung Mui
  • Patent number: 9177651
    Abstract: Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: November 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, William H. Radke, Frankie F. Roohparvar
  • Patent number: 9177613
    Abstract: Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: November 3, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wookhyoung Lee, Jongsik Chun, Sunil Shim, Jaeyoung Ahn, Juyul Lee, Kihyun Hwang, Hansoo Kim, Woonkyung Lee, Jaehoon Jang, Wonseok Cho
  • Patent number: 9171634
    Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column has an active mode of operation where a read operation may be performed on an activated memory cell within that column group, and a non-active mode of operation where the read operation is not performable. Precharge circuitry is used, for each column group, to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell includes coupling circuitry connected between the associated read bit line and a reference line associated with the column group containing that memory cell.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 27, 2015
    Assignee: ARM Limited
    Inventors: Bo Zheng, Gus Yeung, Fakhruddin ali Bohra
  • Patent number: 9171611
    Abstract: A method operates a nonvolatile memory apparatus. The method includes performing a first write operation to store first data in first to third memory cells; and performing a second write operation to store second data in the first to third memory cells in which the first data has been stored, wherein, as a result of the first write operation and the second write operation, each of the first to third memory cells has one of first to third states.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: October 27, 2015
    Assignee: SK HYNIX INC.
    Inventor: Jun Rye Rho
  • Patent number: 9165660
    Abstract: Non-volatile memory devices and related methods are provided.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: October 20, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Jun Lee, Sungsu Moon, Jaihyuk Song, Changsub Lee
  • Patent number: 9159432
    Abstract: In method of programming a nonvolatile memory device including first and second cell strings that are coupled to one bitline, a first channel of the first cell string and a second channel of the second cell string are precharged by applying a first voltage to the bitline, one cell string is selected from the first and second cell strings, and a memory cell included in the selected cell string is programmed by applying a second voltage greater than a ground voltage and less than the first voltage to the bitline.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: October 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Hyun Lee, Jee-Yeon Kang, Dong-Hoon Jang, Jung-Dal Choi
  • Patent number: 9153330
    Abstract: A semiconductor system includes a data storage unit including memory blocks, a circuit group and a control circuit, wherein the memory blocks store data therein and are arranged in a longitudinal direction and a vertical direction. The circuit group is suitable for performing a program, read or erase operation on the memory blocks, and the control circuit controls the circuit group. A memory control unit is suitable for controlling the data storage unit, wherein each of the memory blocks includes a plurality of sub-memory blocks. The sub-memory blocks arranged in the longitudinal direction share bit lines and do not share word lines and source lines. Further, the sub-memory arranged in the vertical direction share the bit lines or the source lines.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: October 6, 2015
    Assignee: SK Hynix Inc.
    Inventor: Seiichi Aritome
  • Patent number: 9147476
    Abstract: Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: September 29, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, William H. Radke, Frankie F. Roohparvar
  • Patent number: 9142313
    Abstract: A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of operation of the nonvolatile memory device is a pre-pulse mode; when the mode of operation is determined to be the pre-pulse mode, applying a pre-pulse having a predetermined level to a string selection line connected with a gate of a string selection transistor of at least one unselected vertical string of the plurality of vertical strings for a particular time period; and performing a verification operation on the programmed memory cell.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: September 22, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Won Shim, Sang-Wan Nam, Kitae Park
  • Patent number: 9142297
    Abstract: A nonvolatile memory device includes a plurality of memory blocks, and a pass transistor array transmitting a plurality of drive signals to a selected memory block among the plurality of memory blocks in response to a block select signal. The pass transistor array includes high voltage transistors including one common drain and two sources formed in one active region and one of the plurality of drive signals transmitted to the common drain is transmitted to different memory blocks through the two sources.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: September 22, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Young Kim, Myung-Hoon Choi
  • Patent number: 9136008
    Abstract: A flash memory apparatus and a data reading method thereof are provided. A boost voltage greater than a pre-charge voltage is provided to a gate of a source discharge transistor when a data reading operation is performed on a memory unit, so as to enhance discharge capability of the source discharge transistor.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: September 15, 2015
    Assignee: Winbond Electronics Corp.
    Inventors: Jun-Lin Yeh, Shang-Wen Chang
  • Patent number: 9135134
    Abstract: A semiconductor device includes a controller configured to control a first memory device to process a request for the first memory device. The controller receives the request for the first memory device, determines a data damage risk of cells connected to one or more second signal lines adjacent to a first signal line of the first memory device corresponding to a requested address by referring to information indicating a data damage risk, and restore data in one or more cells of the cells connected to the second signal line when determining that there is the data damage risk.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: September 15, 2015
    Assignee: SK Hynix Inc.
    Inventors: Young-Suk Moon, Hyung-Dong Lee, Yong-Kee Kwon, Hong-Sik Kim
  • Patent number: 9129704
    Abstract: The semiconductor memory device includes an internal flag signal generator and an active information generator. The internal flag signal generator generates a plurality of internal flag signals which are selectively enabled when combination signals of bank address signals and row address signals supplied are inputted from an external device at least a predetermined number of times. The active information generator outputs a flag signal enabled when at least one of the plurality of internal flag signals is enabled in response to a start signal for extracting information on a number of times that a word line is activated and outputs a plurality of bank information signals according to the plurality of internal flag signals. The active information generator generates internal bank address signals and internal row address signals according to the plurality of internal flag signals to refresh a bank.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: September 8, 2015
    Assignee: SK Hynix Inc.
    Inventor: Sang Kwon Lee
  • Patent number: 9116830
    Abstract: This invention is a method to extend data retention for FLASH based storage in a real time device embodied in generic semiconductor technology. This invention provides a manner to re-energize the Flash memory array to improve the retention characteristics of the memory without altering the clock cycle determinism of the system. Under certain conditions the Flash memory bit cells will lose their charge/non-charge over time. In this particular FLASH technology, an ECC is used to correct single bit errors within a 32 bit word. If there is time before multiple errors occur within a word, the single error cases are identified and “ReFlashed” to bring the value of the cell back to its “newly” programmed levels. This dramatically improves the long term retention characteristics of the memory while requiring some control logic and an area of non-volatile scratch/status information.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: August 25, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gregory A. North, Thomas A. Fedorko, Thomas Hegedus
  • Patent number: 9117504
    Abstract: Apparatuses and methods of operating memory are described. One such method can include receiving a select command at a plurality of memory volumes of a memory device, the select command indicating a targeted memory volume of the plurality of memory volumes. In response to the select command, the method can include selecting the targeted memory volume of the memory volumes and putting at least a portion of a non-selected memory volume of the memory volumes in a particular state based, at least in part, on a previous state of the non-selected memory volume and/or a portion of an address associated with the select command.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: August 25, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Terry M. Grunzke
  • Patent number: 9111591
    Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: August 18, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 9110813
    Abstract: Methods and structure are provided for cache load balancing in storage controllers that utilize Solid State Drive (SSD) caches. One embodiment is a storage controller of a storage system. The storage controller includes a host interface operable to receive Input and Output (I/O) operations from a host computer. The storage controller also includes a cache memory that includes an SSD. Further, the storage controller includes a cache manager that is distinct from the cache memory. The cache manager is able to determine physical locations in the multiple SSDs that are unused, to identify an unused location that was written to a longer period of time ago than other unused locations, and to store a received I/O operation in the identified physical location. Further, the cache manager is able to trigger transmission of the stored I/O operations to storage devices of the storage system for processing.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: August 18, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte Ltd
    Inventors: Parag R. Maharana, Kishore K. Sampathkumar
  • Patent number: 9105349
    Abstract: When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: August 11, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Chris Avila, Gautam Dusija, Jian Chen, Yingda Dong, Man Mui, Seungpil Lee, Alex Mak
  • Patent number: 9090207
    Abstract: A vehicle includes a wheel and a vehicle body that is supported by the wheel for travelling on a riding surface. The vehicle also includes a light emitting device that is mounted to one of the wheel and the vehicle body. The light emitting device is operable to emit light toward the riding surface to create a defined image on the riding surface.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: July 28, 2015
    Assignee: BOXX CORP.
    Inventor: Eric Vaughn Meyers
  • Patent number: 9087688
    Abstract: In a semiconductor memory device, a plurality of control gates is stacked in a first region and a second region of a substrate. A plurality of interlayer insulating layers is stacked in a portion of the second region of the substrate. Each interlayer insulating layer is formed at the same level as a corresponding one of the control gates. A plurality of sub-control gates is stacked in the first and second regions region of the substrate and interposed between the control gates and the interlayer insulating layers. A common node penetrates the interlayer insulating layers and the sub-control gates.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: July 21, 2015
    Assignee: SK HYNIX INC.
    Inventor: Young Soo Ahn
  • Patent number: 9082491
    Abstract: The invention provides a data writing method and device for a flash memory. According to the method, the flash memory obtains write data to be written to the flash memory, directs the flash memory to write a data page of the write data to a strong page of a target pair page of a target block, and directs the flash memory to write first predetermined data to a weak page of the target pair page for extending the data duration of the strong page of the target pair page.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: July 14, 2015
    Assignee: SILICON MOTION, INC.
    Inventor: Cheng-Wei Lin
  • Patent number: 9075751
    Abstract: Generally, this disclosure provides methods and systems for secure data protection with improved read-only memory locking during system pre-boot including protection of Advanced Configuration and Power Interface (ACPI) tables. The methods may include selecting a region of system memory to be protected, the selection occurring in response to a system reset state and performed by a trusted control block (TCB) comprising a trusted basic input/output system (BIOS); programming an address decoder circuit to configure the selected region as read-write; moving data to be secured to the selected region; programming the address decoder circuit to configure the selected region as read-only; and locking the read-only configuration in the address decoder circuit.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventors: Palsamy Sakthikumar, Vincent J. Zimmer, Robert C. Swanson, Eswaramoorthi Nallusamy
  • Patent number: 9063876
    Abstract: A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. This allows the memory system to both store and read data in the same cycle with no conflicts.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: June 23, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Sundar Iyer, Shang-Tse Chuang
  • Patent number: 9059401
    Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: June 16, 2015
    Assignee: SanDisk 3D LLC
    Inventor: Roy E. Scheuerlein