Abstract: A semiconductor memory device which is able to perform a power sequence with high reliability is provided. When a power from an external device is supplied, the controller of the flash memory of the invention is configured to read codes stored in a read-only memory in synchronization with a clock signal to perform a power-on sequence. In addition, the controller is further configured to deactivate the clock signal so as to pause the power-on sequence when it has been detected during the power-on sequence that the voltage of the power is not greater than a threshold, and to activate the clock signal to resume the power-on sequence when it is detected that the voltage of the supplied power exceeds the threshold again.

Abstract: A radiation hardened NAND flash memory data storage device suitable for space flight having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count. Methods of operating the data storage device are also described.

Abstract: A memory device, as provided herein, may include an invalidation bit circuit and a cell array. In methods for controlling such memory devices, the invalidation bit circuit may receive an invalid control command from a memory controller to update the invalid bit data to one of first and second states different from each other, the invalidation bit circuit may receive a read control command from the memory controller and may provide an invalid signal when the invalid bit data is in the first state, the invalidation bit circuit may transmit a data request when the invalid bit data is in the second state, and the cell array may receive the data request and provide data.

Abstract: A first memory film and a sacrificial fill structure are formed within each first-tier memory opening through a first alternating stack of first insulating layers and first spacer material layers. A second alternating stack of second insulating layers and second spacer material layers is formed over the first alternating stack, and a second-tier memory opening is formed over each sacrificial fill structure. A second memory film is formed in each upper opening, and the sacrificial fill structures are removed from underneath the second-tier memory openings to form memory openings. A semiconductor channel is formed on each vertically neighboring pair of a first memory film and a second memory film as a continuous layer. The first memory film is protected by the sacrificial fill structure during formation of the second-tier memory openings.

Abstract: A management device is configured to control reading and writing of data as performed by a processing circuit with respect to a nonvolatile memory. The management device includes circuitry configured to: in response to a request from the processing circuit, perform writing or reading with respect to the nonvolatile memory; in response to writing with respect to the nonvolatile memory, update a table indicating a rewriting count for each area in the nonvolatile memory; detect writing having a high degree of locality representing rewriting operation performed to an extent equal to or greater than a reference value, with respect to the same area in the nonvolatile memory by refer to the table; and identify an area under attack in which the writing having the high degree of locality is performed.

Abstract: Wiper device for blown glass or plastic container, including a hollow body having a first and a second end defining respectively a first and a second opening, a flange extending from an outer surface of the hollow body at the first end, and a wiper element extending from an inner surface of the hollow body, the wiper element defining a passage with a smaller section than the first and second openings, the hollow body featuring at least one first row and one second row of flexible fins extending from the outer surface of the hollow body, near the second end The second row of flexible fins, which is closer to the second end in respect to the first row has, in a non-flexed configuration, a diameter greater than the diameter of the first row of fins in a non-flexed configuration.

Abstract: Embodiments of three-dimensional memory device architectures and methods of operating the devices therefore are disclosed. A method of erasing memory cells of a memory device includes applying a first voltage greater than 10 V to a first semiconductor layer of one or more first vertical structures. The method further includes applying a second voltage greater than 10 V to a second semiconductor layer of one or more second vertical structures stacked over the one or more first vertical structures. The method also includes grounding each of a plurality of word lines. The plurality of word lines are arranged in an alternating stack with insulating layers over a substrate, and the one or more first vertical structures and the one or more second vertical structures extend through the alternating stack.

Abstract: A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.

Abstract: To minimize failures in data writing in a semiconductor storage device in which a transistor is provided for each memory cell. A first transistor has a gate connected to a gate signal line and a source connected to a first source signal line. A second transistor has a gate connected to the gate signal line and a source connected to a second source signal line. A storage element is connected to drains of the first transistor and the second transistor. A gate signal line potential control unit controls a potential of the gate signal line such that the potential becomes a predetermined high potential that is higher than a predetermined reference potential in a case in which the storage element is caused to store data. A source signal line potential control unit causes one of the potentials of the first source signal line and the second signal line to drop such that the one of the potentials becomes lower than the predetermined reference potential, on a basis of the data.

Abstract: A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.

Abstract: An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters.

Abstract: According to one embodiment, a semiconductor storage device includes: a memory cell array including a plurality of bit lines; a sense amplifier; a first circuit including a plurality of transistors respectively connected to the plurality of bit lines and the sense amplifier; and a plurality of interconnects which are provided at a position higher than the bit lines in the first circuit and are not directly connected to the first circuit. The semiconductor storage device does not include, at a position higher than the plurality of interconnects, an interconnect which electrically connects two positions in the semiconductor storage device.

Abstract: Disclosed includes a memory device and a method of operating the memory device. A voltage is applied to a word line coupled to first memory transistors of a first plurality of strings of transistors and second memory transistors of a second plurality of strings of transistors. A current flow through one or more of the first plurality of strings of transistors is enabled, while applying the voltage to the word line. A current flow through the second plurality of strings of transistors is disabled by floating source terminals and drain terminals of the second memory transistors, while enabling the current flow through the one or more of the first plurality of strings of transistors.

Abstract: Provided herein may be a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to apply an erase voltage to a source line and a plurality of select lines of a selected memory block among the plurality of memory blocks during an erase operation; and a control logic configured to control the peripheral circuit to form a trap in an area below at least one of a plurality of source select transistors included in the selected memory block, before the erase voltage is applied to the selected memory block.

Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array having a plurality of memory cells, a plurality of bit lines, each bit line being connected to one of the memory cells in the plurality of memory cells, and a word line commonly connected to the plurality of memory cells. A control circuit is configured to apply a program voltage to the word line and to change a voltage applied to a first bit line in the plurality of bit lines within a first period in which the program voltage is being applied to the word line.

Abstract: A semiconductor memory device includes a plurality of pass transistors disposed along a first direction over a substrate, and configured to transfer operating voltages to a memory cell array; and a plurality of global lines formed in a first wire layer over the pass transistors, extending in a second direction intersecting with the first direction, and configured to transfer the operating voltages to the corresponding pass transistors respectively. The global lines are disposed in first direction pitches of some pass transistors among the pass transistors.

Abstract: A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.

Abstract: An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.

Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.

Abstract: Provided is a semiconductor device that can operate stably. All transistors included in the semiconductor device are transistors each of which contains an oxide semiconductor in a channel formation region. The transistor includes a front gate and a back gate. The threshold voltage of the transistor can be shifted in the positive direction or the negative direction depending on a potential applied to the back gate. To make the transistor in a conducting state, the threshold voltage is shifted in the negative direction to increase the amount of current flowing in the transistor, and to make the transistor in a non-conducting state, the threshold voltage is shifted in the positive direction to decrease the amount of current flowing in the transistor. A circuit of the semiconductor device that utilizes this effect and includes transistors all having the same polarity is formed.

Abstract: A non-volatile memory cell and array structure is disclosed situated within a high voltage region of an integrated circuit. The cell utilizes capacitive coupling based on an overlap between a gate and a drift region to impart a programming voltage. Programming is effectuated using a drain extension which can act to inject hot electrons. The cell can be operated as a one-time programmable (OTP) or multiple-time programmable (MTP) device. The fabrication of the cell relies on processing steps associated with high voltage devices, thus avoiding the need for additional masks, manufacturing steps, etc.

Abstract: A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.

Abstract: Aspects of the disclosure provide a method and an apparatus that perform a background media scan (BGMS) with improved efficiency. In particular, the disclosed BGMS processes can monitor data retention performance of a large capacity solid state drive (SSD) without significantly increasing scanning overhead by scanning only some sample pages of a memory block.

Abstract: Provided herein may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a memory string including memory cells coupled to each other in series via a channel layer, the memory string coupled between a bit line and a second source line. The semiconductor device may include a first source line electrically coupled to the second source line through the channel layer.

Abstract: In a semiconductor memory device, first insulating films are arranged along a first direction and a second direction and extend in a third direction. Interconnect is disposed between the first insulating films in the first direction and extends in the third direction. Electrodes are disposed between the first insulating films in the first direction on a second direction side of the interconnect, and is arranged along the third direction. Second insulating film is disposed between the interconnect and the electrodes. Semiconductor members are arranged along the third direction between the first insulating films in the second direction and extend in the first direction. The electrode is disposed between the interconnect and the semiconductor members. Third insulating film is disposed between the electrodes and the semiconductor member and is thicker than the second insulating film.

Abstract: A disturb management technique for a non-volatile memory including first and second memory cells includes programming the first memory cell by applying a first voltage to a first word line coupled to the first memory cell and a second voltage to a terminal, such as a source terminal, shared by the first memory cell and the second memory cell. A non-zero third voltage having the same sign as the second voltage is applied to a second word line coupled to the second memory cell. The applied non-zero third voltage reduces a tunnel current across a gate oxide that insulates the second word line from a substrate of the second memory cell. This results in the second memory cell having a lower likelihood of being disturbed when programming the first memory cell.

Abstract: Technology is described herein for performing multiplication using non-volatile memory cells. A multiplicand may be stored a node that includes multiple non-volatile memory cells. A multiplicand is stored a node that includes multiple non-volatile memory cells. Each memory cell in the node is connected to the same bit line, in one aspect. A multiply voltage may be applied to each memory cell in the node. Each memory cell in the node responds to the multiply voltage by passing a memory cell current to a bit line. The multiply voltage(s) are simultaneously applied to each memory cell in the node, such that the memory cell current of each memory cell flows in the bit line. The magnitude of the bit line current represents a product of the multiplier and the multiplicand. Vector/vector multiplication may be performed using “n” nodes of memory cells connected to the same bit line.

Abstract: Exemplary methods, apparatuses, and systems include a memory controller detecting that an asynchronous power loss event has occurred. Upon determining that a write operation is in progress to a first type of non-volatile memory element, the memory controller cancels the write operation and retrieves data associated with the write operation. The memory controller sends a request for a second physical address pointing to a second type of non-volatile memory element. Upon receiving a second physical address corresponding to a logical address, the memory controller stores the data at the second physical address.

Abstract: A flash memory controller for a flash memory system includes an ECC circuit that receives first page data and second page data read from the flash memory, and respectively counts a first number of fail bits in the first page data and a second number of fail bits in the second page data, an abnormal wordline detector configured to compare the first number of fail bits and second number of fail bits to derive a fail bit change rate between the first page data and the second page data, and generate an abnormal wordline detection signal in response to the fail bit change rate, and a control unit that controls operation of the flash memory in response to the abnormal wordline detection signal.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

Abstract: A toner container installable in an image forming device having a controller according to one example embodiment includes a housing having a reservoir for storing toner. A chip is positioned on the housing and configured to receive a first write command from the controller of the image forming device. The chip is further configured to determine whether a transmission cycle bit of the first write command matches a transmission cycle bit of a second write command received by the chip from the controller of the image forming device previous to the first write command. The chip is further configured to resend to the controller of the image forming device a response to the second write command if the transmission cycle bit of the first write command matches the transmission cycle bit of the second write command.

Abstract: Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. The second memory cell type is different from the first memory cell type.

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.

Abstract: Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device having improved reliability includes a memory cell array including memory cells coupled to a plurality of word lines, a peripheral circuit configured to perform a program operation on a word line selected from among the plurality of word lines, and control logic configured to control the peripheral circuit so that, when the selected word line is a reference word line during the program operation, a partial erase operation is performed on memory cells included in a memory cell group corresponding to the reference word line.

Abstract: A method for reading memory cells from a memory is stated, inter alia, in which physical values are determined from a number of n memory cells, wherein n is at least three, in which the physical values are at least partially compared with one another, in which K different digital memory cell values are assigned to the n memory cells on the basis of the compared physical values, and in which a code word of an n1-, . . . , nK-out-of-n code is assigned to the digital memory cell values obtained in this manner. In particular, the following apply in this case: n?3, n1?1 to nK?1, K?2 and m?1.

Abstract: A memory controller manages memory access operations through a flash memory interface of a memory array of a solid-state storage device connected to a host. The memory controller executes a first memory access operation in the memory array. The first memory access operation has a first priority. The memory controller detects a suspending memory access operation available for execution in the memory array and having a higher priority than the first priority. The detection operation distinguishes between suspending memory access operations and non-suspending memory access operations. The memory controller suspends execution of the first memory access operation in the memory array and executes one or more memory access operations having higher priorities than the first priority and being available for execution in the memory array. The memory controller resumes the execution of the first memory access operation in the memory array.

Abstract: A semiconductor storage device with a smaller chip size than prior art and a readout method are provided. The semiconductor storage device includes a memory cell array; a page buffer/sense circuit having a sensing node for sensing readout data from a selected page of the memory cell array and a latch circuit for holding data sensed by the sensing node; and a controller controls operations on the memory cell array. The sensing node includes an NMOS capacitor.

Abstract: Apparatus and methods are disclosed, including an apparatus having first and second units of vertically arranged strings of memory cells, each unit including multiple tiers of a semiconductor material, including multiple tiers of memory cells, each tier of memory cells including an access line of at least one memory cell. The access line of a first tier of the first unit can be selectively coupled to a first drive transistor through a first decoder transistor, the access line of a first tier of the second unit can be selectively coupled to the first drive transistor through a second decoder transistor, and the access line of the first tier of the first unit can be selectively coupled to the access line of the first tier of the second unit through the first and second decoder transistors.

Abstract: A non-volatile semiconductor storage device includes a memory cell array and a control circuit configured to control a data write operation for the memory cell array in a first or second write mode in response to a write command sequence. In the first write mode, the control circuit performs a first write operation, which includes an operation in which one or more bit lines are charged according to write data and an operation in which a write voltage is applied to a selected word line according to address data included in the write command sequence. In the second write mode, the control circuit performs a second write operation, which includes the operation in which the one or more bit lines are charged according to the write data and does not include the operation in which the write voltage is applied to the selected word line.

Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.

Abstract: A method of using flash storage devices with different sized erase blocks is provided. The method includes allocating a plurality of erase blocks of heterogeneous erase block sizes to a RAID stripe, to form a tile pattern having the heterogeneous erase block sizes in the RAID stripe. The method includes writing the RAID stripe across the flash storage devices in accordance with the allocating, and stopping the writing the RAID stripe, responsive to contents of the RAID stripe reaching a threshold.

Abstract: Page-level reference voltage parameterization techniques are provided for solid state memory devices. A method comprises obtaining a bit error count for a plurality of page numbers across a plurality of blocks of a solid state memory device; determining a substantially optimal reference voltage for each page number that substantially minimizes a corresponding bit error count; collecting, for each reference voltage, page numbers and corresponding substantially optimal reference voltages; and determining, for each reference voltage, a non-linear function that substantially fits a distribution of the collected page numbers and corresponding substantially optimal reference voltages, wherein a given page having a given page number is read using a plurality of parameters of the non-linear function to generate the substantially optimal reference voltage for the given page number.

Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. The method includes: performing a single-layer erasing operation on one of physical erasing units; performing a multi-layer erasing operation on another one of the physical erasing units; and performing a wear leveling operation based on the one and the another one of the physical erasing units, wherein the another one of the physical erasing units is performed the wear leveling operation first than the one of the physical erasing units.

Abstract: A data storage system includes a non-volatile memory array controlled by a controller that records a number of a plurality of like operations targeting a first block among a plurality of blocks in the non-volatile memory array. In response to the number of the plurality of like operations satisfying a threshold, the controller initiates a mitigation read request by recording an identifier of a second block in a high priority request in a mitigation data structure. The controller initiates other mitigation read requests by recording identifiers of other blocks of the non-volatile memory in low priority requests in the mitigation data structure. The controller preferentially services the high priority request from the mitigation data structure over the low priority requests, where servicing the high priority request includes performing a mitigation read to the second block.

Abstract: According to one embodiment, a semiconductor memory device comprises a first memory cell array including a first block and a second block, the first block including a first memory cell, and the second block including a second memory cell; and a controller that performs, in a first period of time in writing, a first program in the first memory cell and the second memory cell.

Abstract: A memory system includes a memory device including a plurality of memory arrays, each of which includes a plurality of memory blocks, and a controller suitable for setting super blocks each including respective memory blocks that belong to two or more memory arrays among the plurality of the memory arrays and performing a garbage collection operation on the super blocks based on a valid page information and a wearing level of each super block.

Abstract: An apparatus includes a first serial port having a first number of lanes usable to form a first multi-lane link to a solid state drive (SSD) and a second serial port having a second number of lanes that is at least twice the first number of lanes. A first subset of the second number of lanes constitutes a first logical serial port and is usable to form a second multi-lane link to a first transport fabric and a second subset of the second number of lanes constitutes a second logical serial port and is usable to form a third multi-lane link to a second transport fabric. The apparatus further includes a controller and a multiplexer to connect the first serial port to one of the first logical serial port or the second logical serial port.

Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.