Abstract: Provided herein is a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of pages; a voltage supply unit configured to provide operating voltages to the plurality of pages; a plurality of page buffers coupled to a plurality of bit lines of the memory cell array and configured to control and sense currents flowing through the plurality of bit lines in response to a page buffer sensing signal; and a control logic configured to control the voltage supply unit and the plurality of page buffers such that the plurality of pages are successively programmed, and to control a potential level of the page buffer sensing signal depending on a program sequence of the plurality of pages during a program verify operation of a program operation.

Abstract: Memory device having a tile architecture are disclosed. The memory device may include a first plane having multiple pairs of tiles, wherein at least some of the pairs of tiles of the first plane include a distributed block select circuit and page buffer circuitry. Another memory device may include a memory array, and a CMOS under array region. At least some tile regions may include portions of a total amount of block select circuitry distributed throughout the CUA region, vertical string drivers located outside of the memory array, and page buffer circuitry coupled with the memory array. Another memory device may include a first tile pair including a first tile, a second tile, a first vertical string driver therebetween, a first page buffer region that is greater than 50% of area for the first tile pair, and a first portion of a distributed block select circuitry.

Abstract: A semiconductor memory device includes a memory structural body including first and second planes each of which includes memory cells coupled to word lines extending in a first direction and bit lines extending in a second direction and which are disposed along the first direction; and a logic structural body disposed between a substrate and the memory structural body, and including a row decoder. The row decoder includes a pass transistor circuit which is coupled in common to the first and second planes and a block switch circuit which controls the pass transistor circuit. The block switch circuit is disposed in first and second plane regions of the logic structural body which overlap with the first and second planes in a third direction perpendicular to the first and second directions, and the pass transistor circuit is disposed in an interval region between the first and second plane regions.

Abstract: A memory system, architecture, and method for storing data in response to commands received from a host is disclosed. The memory system includes a memory control circuit configured to receive commands from the host; at least one memory device configured to store data; and at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register. The system preferably includes communication links between the host, the at least one memory control circuit, the at least one data buffer circuit, and the at least one memory device. The system preferably is configured so that register access commands are sent by the host to the memory control circuit over the communication links between the host and the memory control circuit.

Abstract: Methods of operating a memory include receiving a plurality of digits of data for programming to a plurality of memory cells of the memory, redistributing the received plurality of digits of data in a reversible manner to generate a plurality of digits of redistributed data each corresponding to a respective memory cell of the plurality of memory cells, and for each memory cell of the plurality of memory cells, programming the corresponding digit of redistributed data for that memory cell to a first digit position of a respective data state of that memory cell, programming a second digit of data having a first data value to a second digit position of the respective data state of that memory cell, and programming a third digit of data having a second data value to a third digit position of the respective data state of that memory cell.

Abstract: A memory management method for a storage device having a rewritable non-volatile memory module is provided, wherein the rewritable non-volatile memory module has a plurality of physical units, and each of the physical units has a plurality of word-lines. The method includes: performing a first checking operation on a target physical unit among the physical units according to an occurrence of a specific event; and determining whether a first operation needs to be performed on valid data in the target physical unit according to a checking result of the first checking operation that corresponds to the target physical unit.

Abstract: A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least eight threshold voltages, a first bit line connected to the first memory cell, a word line connected to a gate of the first memory cell, a sense amplifier connected to the first bit line, wherein the sense amplifier has at least four data latch circuits, and an extra data latch circuit connected to the sense amplifier through a data bus. A verification operation for verifying the threshold voltage of the first memory cell is performed after a programming operation is performed on the first memory cell, and the verification operation includes seven verification operations during which the four data latch circuits, but not the extra data latch circuit, are accessed.

Abstract: An erase voltage is applied to channels of a selected string group to erase only the selected string group. A size and a number of the spare blocks for storing meta data are reduced and thus a size of the nonvolatile memory device is reduced by reducing unit capacity of the erase operation through grouping of the cell strings. Lifetime of the nonvolatile memory device is extended by having control over erasing some cell strings and not others. Control of cell strings for erasure includes allowing some control lines to float, in some embodiments. In some embodiments, ground select transistors with different thresholds and appropriately applied voltages are used to control erasure of particular cell strings. In some embodiments, biasing of word lines is applied differently to portions of a particular cell string to only erase a portion of the particular cell string.

Abstract: A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.

Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.

Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.

Abstract: A program circuit may two-dimensionally program data into cells by applying different selected bit line or channel voltages to different bit lines or channels located in different bit line zones of a block during a program operation. The block may be further separated or divided into word line zones. The program circuit may adjust the different bit line or channel voltages as it programs in different word line zones of the block. In accordance with the two-dimensional programming, the program circuit may perform single-pulse program-only SLC program operations.

Abstract: Programming methods include programming first and second data in first and second memory cells, reading the first data from the first memory cell by applying a read voltage to an access line connected to the first and second memory cells while the first memory cell is electrically connected to a data line and while the second memory cell is electrically disconnected from the data line, reading the second data from the second memory cell by electrically disconnecting the first memory cell from the data line and electrically connecting the second memory cell to the data line while the read voltage remains applied to the access line, and programming the read first data and the read second data in a single memory cell connected to a different access line.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a column selection circuit, a sensing circuit, an output circuit, and a verification circuit. The column selection circuit selects n-bit data from data read from a memory cell array according to a column selection signal and outputs the selected n-bit data to an n-bit data bus. The sensing circuit senses the n-bit data on the data bus in response to an activation signal. The output circuit selects m-bit data from the n-bit data sensed by the sensing circuit in response to an internal clock signal synchronized with a serial clock signal applied from outside and outputs the selected m-bit data from output terminals. The verification circuit compares the data sensed by the sensing circuit with the data output by the output circuit to verifying the correctness of read-out data.

Abstract: A NAND flash memory suppresses an influence caused by FG coupling and has high reliability. The flash memory of the invention includes: a memory array formed with a plurality of NAND strings; a row selection unit selecting rows of the memory array; and a bit line selection circuit (200) selecting even-numbered pages or odd-numbered pages of the selected row. The even-numbered pages (BL0, BL1, BL4, BL5) include a plurality of pairs of adjacent bit line pairs, the odd-numbered pages (BL2, BL3, BL6, BL7) include a plurality of pairs of adjacent bit line pairs, and the bit lines of the even-numbered page and the bit lines of the odd-numbered page are arranged alternately.

Abstract: According to one embodiment, a semiconductor memory device includes a memory string including first and second selection transistors, a first transistor, and first and second memory cell transistors, first and second selection gate lines, first to third word lines, and a row decoder. A write operation includes a first mode to write one-bit data and a second mode to write two-bit data. In a case of writing the one-bit data to the first memory cell transistor in the first mode, the row decoder applies a first voltage to the first word line. In a case of writing the two-bit data to the first memory cell transistor in the second mode, the row decoder applies, to the first word line, a second voltage that is higher than the first voltage.

Abstract: A system is described for identifying key lock contention issues in computing devices. A computing device is executed and lock contention information relating to operations during execution of the computing device is recorded. The data is parsed and analyzed to determine blocking relationships between operations due to lock contention. Algorithms are implemented to analyze dependencies between operations based on the data and to identify key areas of optimization for performance improvement. Algorithms can be based on the Hyperlink-Induced Topic Search algorithm or the PageRank algorithm.

Abstract: A controller includes: a first buffer suitable for buffering data read from a memory device; a second buffer suitable for buffering data to be written into the memory device; a processor suitable for, in response to a read command, controlling the memory device to read data therefrom and the first buffer to buffer the read data; and a buffer management unit suitable for, in response to the read command, providing the buffered data of the first buffer when the second buffer does not currently buffer data to be read.

Abstract: A non-volatile memory device includes a memory cell array region in which memory cells are vertically stacked on a substrate and a page buffer region in which first and second page buffers are arranged. A first distance between the memory cell array region and the first page buffer is shorter than a second distance between the memory cell array region and the second page buffer. The first page buffer includes a first transistor driven in response to a first control signal. The second page buffer includes a second transistor driven in response to a second control signal corresponding to the first control signal. At least one of design constraints and processing constraints with respect to the first and second transistors is different.

Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.

Abstract: A memory device includes a memory cell array; bit lines including even and odd bit lines extending in a first direction and alternately disposed; cache latches including even cache latches which exchange data with the memory cell array through the even bit lines and odd cache latches which exchange data with the memory cell array through the odd bit lines; 2^k data lines, where k is a natural number equal to or greater than 2, respectively corresponding to 2^k input/output pins; and column merge units respectively allocated to the input/output pins, and each suitable for coupling any one of the even cache latches or any one of the odd cache latches to a data line corresponding to an input/output pin to which it is allocated. A pitch of the column merge units in a second direction intersecting the first direction is greater than a pitch of the cache latches.

Abstract: An apparatus for controlling a memory device may include: a table storing information of a plurality of read voltages; an error correction unit suitable for correcting an error of read data; and a processor functionally coupled to the RR table and the error correction unit. The processor selects a default read voltage among the plurality of read voltages from the table when a read fail for the memory device is recognized, sets a shift direction of the default read voltage based on the number of read cells of the memory device read by the default read voltage, and controls a read retry operation of the memory device based on at least one read voltage in the set shift direction in the table.

Abstract: A method of managing a message transmission flow and a storage device using the method are provided. The method of managing a message transmission flow includes receiving, at a storage device, response transmission type information in at least one of a command phase and a data phase, and transmitting response information to a host in at least one of a normal mode and a fast mode based on the received response transmission type information. The normal mode and the fast mode have different latencies.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation.

Abstract: According to one embodiment, a memory system is configured to operate as one of semiconductor storage devices in a storage array. The memory system includes a nonvolatile memory and a controller. The controller executes a write operation of writing data, received from a host, to the nonvolatile memory. The controller receives, from the host or another semiconductor storage device in the storage array, a notification indicative of a value related to an amount of reduction in write performance of the another semiconductor device. The controller reduces performance of the write operation based on the value notified by the received notification.

Abstract: A page buffer includes a first precharge circuit, a second precharge circuit, and a sense amplifying circuit. The first precharge circuit includes a first path for precharging a bitline connected to a nonvolatile memory cell. The second precharge circuit includes a second path for precharging a sensing node connected to the bitline. The second path is electrically separated from the first path. The sensing node is used to detect a state of the nonvolatile memory cell. The sense amplifying circuit is connected to the sensing node and the second precharge circuit, and stores state information representing the state of the nonvolatile memory cell. The second precharge circuit is configured to perform a first precharge operation for the sensing node and configured to selectively perform a second precharge operation for the sensing node based on the state of the nonvolatile memory cell after the first precharge operation.

Abstract: A method for improving a program speed of a memory includes acquiring a program level of the memory, comparing the program level of the memory with a valid level and a target level for generating a comparison result, and entering a first loop and/or a second loop for setting a program voltage of the memory according to the comparison result.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: A memory device has a memory cell array with memory cells. A page buffer group generates page buffer signals according to a verify read result of the memory cells. A page buffer decoding unit generates a decoder output signal corresponding to the number of fail bits from the page buffer signals based on a first reference current. A slow bit counter outputs a count result corresponding to the number of fail bits from the decoder output signal based on a second reference current corresponding to M times the first reference current, where M is a positive integer. A pass/fail checking unit determines a program outcome with respect to the memory cells based on the count result and outputs a pass signal or a fail signal based on the determined program outcome.

Abstract: Provided herein may be a control circuit, peripheral circuit, semiconductor memory device and methods of operating the device and circuits. The method of operating a semiconductor memory device may include applying a control signal having a form, in which a step pulse is combined with a ramp signal, to a gate electrode of a transistor for setting up a voltage of a bit line of the selected memory cell. The method of operating a semiconductor memory device may include applying a program pulse to a word line of the selected memory cell.

Abstract: A resistive processing unit (RPU) circuit for use in a neural network application includes at least one floating gate storage device, the floating gate storage device including a floating gate, a control gate and an inject/erase gate. The RPU circuit further includes a feedback circuit connected with the floating gate storage device. The feedback circuit is configured to maintain a substantially constant floating gate potential of the floating gate storage device during an update mode of operation of the RPU circuit, and is disabled during a readout mode of operation of the RPU circuit.

Abstract: A data storage system includes a non-volatile memory array controlled by a controller. In response to receipt of write data to be written to the non-volatile memory array, the controller determines whether a read count of an unfinalized candidate block of storage within the non-volatile memory array satisfies a read count threshold applicable to the block. In response to determining that the read count of the unfinalized candidate block satisfies the read count threshold, the controller finalizing programming of the candidate block and programming an alternative block with the write data.

Abstract: Systems and methods for immediate physical erasure of data in a memory system in response to a user command are disclosed. In one implementation, a memory system includes a non-volatile memory and a controller in communication with the non-volatile memory. The controller comprises a processor that is configured to receive from a host in communication with the memory system, a destruct command that indicates a user request to make the memory system inoperable. The processor is further configured to perform one or more operations to render the memory system inoperable in response to the destruct command received from the host.

Abstract: A data encoding method, a memory control circuit unit and a memory storage device are provided. The method includes: writing a first data into a first physical programming unit of a first physical programming unit group among a plurality of physical programming unit groups; writing a second data into a second physical programming unit of a second physical programming unit group among the plurality of physical programming unit groups; encoding the first data and the second data to generate an encoded data; and writing the encoded data into a third physical programming unit group among the plurality of physical programming unit groups.

Abstract: Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.

Abstract: An OTP (One-Time Programmable) memory cell in an array has a programming MOSFET and symmetrically placed access transistors on either side of the programming MOSFET. The balanced layout of the memory cell improves photolithographic effects with a resulting improved process results. Results of programming the memory cell is also improved.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array having memory cell capable of holding N-bit data; and a sense amplifier comprising a first latch holding information on a threshold distribution, a second latch holding write data, and a third latch holding lower information of the N-bit data, and supplying a first to a fourth voltages to the memory cell to write the data to the memory cell using the first to fourth voltages. The sense amplifier supplies the first to third voltages to the memory cell based on information in the second and the third latches, and based on a result of transfer of the information held by the first latch to the second latch, supplies the fourth voltage or the first voltage to the memory cell.

Abstract: A control method for a solid state storage device is provided. Firstly, an elapsed time period of the solid state storage device is counted when the solid state storage device is in a normal working state. Then, a read refresh operation is performed on a memory array of the solid state storage device at a first time interval.

Abstract: An apparatus for mapping user data into a selective underlying exposure address (SUE) space includes a memory that stores machine instructions and a processor that executes the instructions to combine first user data from a plurality of logically-addressed blocks to create a SUE page. The SUE page corresponds to a respective physical page of a respective physical block on each of a plurality of dies for which corresponding physical blocks of memory cells are jointly managed as a unit in a storage device. The processor further executes the instructions to store mapping information associating the first user data with the SUE page in a logical address space in the storage device.

Abstract: An operating method of a data storage device includes setting a first page access unit using a first page electrically coupled with a first word line of a first plane and a second page electrically coupled with a second word line of a second plane; and setting a second page access unit using a third page electrically coupled with a second word line of the first plane and a fourth page electrically coupled with a first word line of the second plane.

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Abstract: Some embodiments include apparatuses and methods having memory cells and a control unit. The control unit can retrieve information from a first portion of the memory cells. The information can include bits organized into a first bit group and second bit group. The information can be associated with management information. The control unit can store the first and second bits in the second group in a second portion of the memory cells. The control unit can update the first and second management information after the second bit group is stored.

Abstract: Method and apparatus for managing data in a data storage device. In some embodiments, a non-volatile cache memory stores a sequence of pages from a host device. A non-volatile main memory has a plurality of n-level cells arranged on m separate integrated circuit dies each simultaneously accessible during programming and read operations using an associated transfer circuit, where m and n are plural numbers. A control circuit writes first and second pages from the sequence of pages to a selected set of the n-level cells coupled to a common word line on a selected integrated circuit die. The second page is separated from the first page in the sequence of pages by a logical offset comprising a plurality of intervening pages in the sequence of pages. The logical offset is selected responsive to the m number of integrated circuit dies and a delay time associated with the transfer circuits.

Abstract: A read voltage tracking method, a memory storage device and a memory control circuit unit are provided. The method includes obtaining a plurality of test read voltages corresponding to a plurality of voltage adjustment values, and obtaining an optimal read voltage according to the voltage adjustment values. The step of obtaining the test read voltages includes obtaining a second test read voltage by adjusting a first test read voltage according to a first voltage adjustment value, and obtaining a third test read voltage by adjusting the second test read voltage according to a second voltage adjustment value, and the first test read voltage is a preset test read voltage, the first voltage adjustment value is a preset voltage adjustment value, and the first voltage adjustment value is different from the second voltage adjustment value.

Abstract: The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines for selecting a row according to a particular address given on the address input lines. Additional address mask input lines are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line. The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously.

Abstract: Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.

Abstract: An erasing method of a nonvolatile semiconductor memory device of the disclosure includes erasing data of a selected memory cell (step S100); immediately applying a programming voltage lower than a programming voltage in a programming time to all control gates of the selected memory cell after the erasing step, thereby performing a week programming (step S110); performing a erasing verification of the selected memory cell (step S120).

Abstract: A memory device has a memory cell array with memory cells. A page buffer group generates page buffer signals according to a verify read result of the memory cells. A page buffer decoding unit generates a decoder output signal corresponding to the number of fail bits from the page buffer signals based on a first reference current. A slow bit counter outputs a count result corresponding to the number of fail bits from the decoder output signal based on a second reference current corresponding to M times the first reference current, where M is a positive integer. A pass/fail checking unit determines a program outcome with respect to the memory cells based on the count result and outputs a pass signal or a fail signal based on the determined program outcome.

Abstract: All-printed paper-based substrate memory devices are described. In an embodiment, a paper-based memory device is prepared by coating one or more areas of a paper substrate with a conductor material such as a carbon paste, to form a first electrode of a memory, depositing a layer of insulator material, such as titanium dioxide, over one or more areas of the conductor material, and depositing a layer of metal over one or more areas of the insulator material to form a second electrode of the memory. In an embodiment, the device can further include diodes printed between the insulator material and the second electrode, and the first electrode and the second electrodes can be formed as a crossbar structure to provide a WORM memory. The various layers and the diodes can be printed onto the paper substrate by, for example, an ink jet printer.

Abstract: A memory device of an embodiment includes a memory cell array and a controller. In the memory cell, data is written per page unit and is erased per block which is a multiple the page unit of a natural number of two or more. The block includes memory strings, each including memory cells capable of storing data of one or more bits with a threshold voltage indicative of an erase state in which data is erased and one or more threshold voltages which are higher than the voltage indicative of the erase state and indicate written states in which data is written. The controller selects one of adjustment values of positive and negative values based on data read from a first memory cell of the memory cells, and reads data from a second memory cell of the memory cells using the selected adjustment value and a first read voltage.