Abstract: A memory system includes: a memory device; a host interface suitable for receiving write commands and queueing the received write commands in an interface queue; a workload manager suitable for detecting, in a cache program mode, a mixed workload when a read count is greater than a first threshold value, the read count representing a number of read commands queued in the interface queue and the mixed workload representing receipt of a mix of read and write commands; a mode manager suitable for switching from the cache program mode to a normal program mode when the mixed workload is detected; and a processor suitable for processing write commands queued in a command queue in the cache program mode and processing write commands queued in the interface queue in the normal program mode when the mixed workload is detected.

Abstract: A processing device performs a multi-pass programming operation on the memory device resulting in first pass programming distributions and second pass programming distributions. One or more read level thresholds between the second pass programming distributions are changed. Responsive to changing the one or more read level thresholds between the second pass programming distributions, one or more read level thresholds between the first pass programming distributions are adjusted based on the changes to the one or more read level thresholds between the second pass programming distributions.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device may include: a memory block including upper pages, a center page, and lower pages; a peripheral circuit configured to perform a read operation on the memory block; and a control logic configured to control the peripheral circuit to perform the read operation and control the peripheral circuit such that, during the read operation, based on a location of a selected page among the plurality of pages, a pass voltage to be applied to first adjacent pages disposed adjacent to the selected page in a first direction differs from a pass voltage to be applied to second adjacent pages disposed adjacent to the selected page in a second direction.

Abstract: An operation method of a memory device may include performing a program operation on a memory block in response to a program command from a controller, and applying a program voltage to a dummy word line coupled to dummy cells within the memory block such that the dummy cells have an indication threshold voltage higher than a normal pass voltage and providing a program fail signal to the controller when the program operation fails.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a page buffer group configured to include a plurality of page buffers respectively coupled to a plurality of memory areas through a plurality of bit lines, a row decoder configured to select a memory area, on which an operation corresponding to a command is to be performed, from among the plurality of memory areas, based on a row address included in an address, a column decoder configured to transfer data to a page buffer of the plurality of page buffers according to a column address included in the address and an address controller configured to control the row decoder and the column decoder so that the data is stored in another memory area other than the selected memory area.

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

Abstract: Memory devices are disclosed. A memory device may include multiple pairs of tiles. At least some of the pairs of tiles may include a block select circuit. At least one portion of the block select circuit within a first pair of tiles of the multiple pairs of tiles is offset from at least one other portion of the block select circuit within a second pair of tiles of the multiple pairs of tiles. Also, at least one pair of tiles of the multiple pair of tiles may include an associated vertical string driver offset from each of a first tile and a second tile of an associated pair of tiles.

Abstract: A nonvolatile memory device including: a first semiconductor layer comprising a plurality of first word lines extending in a first direction, a first upper substrate and a first memory cell array, a second semiconductor layer including a plurality of second word lines extending in the first direction, second and third upper substrates adjacent to each other in the first direction and a second memory cell array, wherein the second memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, wherein the first semiconductor layer and the second semiconductor layer share a plurality of bit lines extending in a second direction, and a third semiconductor layer under the second semiconductor layer in a third direction perpendicular to the first and second directions, wherein the third semiconductor layer includes a lower substrate that includes a plurality of row decoder circuits and a plurality of page buffer circuits, wherein the

Abstract: A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells, and one or more dummy word lines respectively coupled to gate terminals of the one or more dummy memory cells. The memory device further includes a control circuit configured to program a target memory cell coupled to a selected word line of the plurality of word lines. To program the target memory cell, the control circuit is configured to apply a biased dummy word line pre-pulse signal to the one or more dummy word lines in a pre-charge period prior to a programming period.

Abstract: Host data can be written to a first portion of a memory sub-system in a first write mode. An indication can be received that a data block of a second portion of the memory sub-system is available to be written to in a second write mode. In response to receiving the indication, it is determined to write a second portion of the host data to the data block of the second portion. In response to determining to write the second portion of the host data to the data block of the second portion, the second portion of the host data is written to the second available data block in the second write mode prior to closing the first available data block in the first write mode.

Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.

Abstract: A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.

Abstract: A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.

Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include memory cells for storing data, page buffers coupled to the memory cells, the page buffers including first latches for temporarily storing original data during a program operation and second latches for storing verification data during a verify operation, and a command execution component for controlling the page buffers, in response to a normal command signal, a suspend command signal, or a resume command signal, to store the original data and the verification data in the first and second latches in response to the normal command signal, to provide the verification data to the first latches in response to the suspend command signal, and to transfer the verification data from the first latches to the second latches in response to the resume command signal.

Abstract: A memory device includes a first page buffer supplying a first bias voltage to a selected bitline in a bitline precharge phase; and a second page buffer supplying a second bias voltage to an unselected bitline, adjacent to the selected bitline, in the bitline precharge phase, wherein the first page buffer includes a first bitline precharge circuit supplying the first bias voltage to the selected bitline, the second page buffer includes a second bitline precharge circuit supplying the second bias voltage to the unselected bitline, wherein the second page buffer floats the unselected bitline in a sensing phase for detecting data of a selected memory cell connected to the selected to bitline.

Abstract: A memory sub-system configured to generate or update a model for reading memory cells in a memory device. For example, in response to a processing device of a memory sub-system transmitting to a memory device read commands that are configured to instruct the memory device to retrieve data from a group of memory cells formed on an integrated circuit die in the memory device, the memory device may measure signal and noise characteristics of the group of memory cells during execution of the read commands. Based on the signal and noise characteristics the memory sub-system can generate or update, measured during the execution of the read commands a model of changes relevant to reading data from the group of memory cells. The changes can be a result of damage, charge loss, read disturb, cross-temperature effect, etc.

Abstract: A memory system includes: a memory device including a three dimensional (3D) cell array, in which memory cells having the same height are coupled to a component word line by units of rows and component word lines having the same height are coupled to a group word line; and a controller suitable for controlling the memory device to perform a program operation with a program data into memory cells coupled to a data component word line selected from a plurality of component word line included in a single group word line and to perform a dummy program operation with dummy data into memory cells coupled to remaining dummy component word lines among the plurality of component word lines.

Abstract: A semiconductor memory device includes a memory transistor, a word line, a peripheral circuit, and electrodes connected to the peripheral circuit. In response to a write command via the electrodes, the peripheral circuit can execute a first program operation of applying a first program voltage to the word line one time when the write command is one of an n1-th write command to an n2-th write command corresponding to the memory transistor; and execute a second program operation of applying a second program voltage to the first word line at least one time when the write command is one of an (n2+1)-th write command to an n3-th write command corresponding to the memory transistor. The second program voltage in a k-th second program operation is less than the first program voltage in a k-th first program operation.

Abstract: An integrated circuit and a computing method thereof are provided. The integrated circuit includes a memory array, word lines, bit lines and a page buffer. The memory array includes memory cells, each configured to be programmed with a weight. The word lines respectively connect a row of the memory cells. The bit lines are respectively connected with a column of the memory cells that are connected in series. More than one of the bit lines in a block of the memory array or more than one of the word lines in multiple blocks of the memory array are configured to receive input voltages. The memory cells receiving the input voltages are configured to multiply the weights stored therein and the received input voltages. The page buffer is coupled to the memory array, and configured to sense products of the weights and the input voltages.

Abstract: Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.

Abstract: The present disclosure provides a semiconductor structure, including a transistor layer, a memory region over the transistor layer, and a logic region adjacent to the memory region. The memory region includes a first Nth metal line, a magnetic tunneling junction (MTJ) over the first Nth metal line, a cap over the MTJ, a first stop layer on the cap; and a first (N+1)th metal via over the MTJ. The first (N+1)th metal via is laterally surrounded by the cap and the first stop layer. The logic region includes a second Nth metal line, a second stop layer being disposed over an (N+1)th metal line, and a second (N+1)th metal via over the (N+1)th metal line. N is an integer greater than or equal to 1. A method of manufacturing the semiconductor structure is also disclosed.

Abstract: A memory device, in accordance with a method of operation, may include: a plurality of pages coupled to a common word line and configured to be sequentially selected by different select lines; a program operation controller configured to perform a program operation on a first page that is to be programmed first, among the plurality of pages; and a start loop manager configured to generate start loop information about a program loop in which program verification corresponding to each of a plurality of program states to be formed by threshold voltages of memory cells included in the first page starts, during the program operation on the first page. The program operation controller is further configured to perform a program operation on a second page to be programmed subsequent to the first page, among the plurality of pages, based on the start loop information.

Abstract: A read retry method for a solid state storage device is provided. The solid state storage device is in communication with a host. The solid state storage device includes a non-volatile memory. The read retry method includes the following steps. Firstly, the solid state storage device judges whether a specified read block of the non-volatile memory is in a specified failure mode. If the specified read block of the non-volatile memory is in the specified failure mode, a failure mode read retry process corresponding to the specified failure mode is performed. If an accurate read data is acquired in the failure mode read retry process, the accurate read data is transmitted to the host. If the accurate read data is not acquired in the failure mode read retry process, a read fail message is sent to the host.

Abstract: A semiconductor storage device includes a plurality of memory cells and a plurality of bit lines connected thereto, a plurality of sense amplifier units respectively connected to the plurality of bit lines, and a cache memory connected to the plurality of sense amplifier units. Each sense amplifier unit includes a sense node and a latch in which data transferred onto the sense node from a corresponding bit line is latched. First data latched in a first sense amplifier unit among the plurality of sense amplifier units is transferred to the cache memory, and second data latched in a second sense amplifier unit among the plurality of sense amplifier units is transferred to the sense node of the first second sense amplifier unit. Thereafter, the second data is latched in the first sense amplifier unit and transferred to the cache memory.

Abstract: A data storage system performs operations including determining an endurance level of a block of memory cells; adjusting a read performance profile for the block of memory cells based on the determined endurance level; receiving a data read command specifying data to be read from a particular memory cell of the block of memory cells; and in response to the data read command, performing a read operation on the particular memory cell using the adjusted read performance profile.

Abstract: A memory device includes: a memory block including a plurality of main pages and a dummy page; a peripheral circuit for performing a normal program operation on the plurality of main pages and a dummy program operation on the dummy page in a program operation, and reading data stored in the dummy page and the plurality of main pages in a read operation; and control logic for controlling the peripheral circuit to program, to the dummy page, the same data as first logical page data of a first main page among the plurality of main pages in the program operation.

Abstract: A memory system, a memory controller and a memory device. In a set operation, by applying different pass voltages to at least one first word line and at least one second word line among the plurality of word lines excluding a selected target word line, an operation error of the memory device may be prevented.

Abstract: A memory device such as a page mode NAND flash is operated, using a first pipeline stage, to clear a page buffer to a second buffer level, and transfer a page to the page buffer; a second pipeline stage to clear the second buffer level to the third buffer level and transfer the page from the page buffer to the second buffer level; a third pipeline stage to move the page to the third buffer level and execute in an interleaved fashion a first ECC function over data in a first part of the page and output the first part of the page while performing an second ECC function, and to execute the first ECC function over data in a second part of the page in the third buffer level, and to output the second part while performing the second ECC function.

Abstract: A method for accessing a storage system, the method may include receiving a block call, from a processor that executes an application and by a storage engine of a computer that is coupled to a storage system; generating, by the storage engine and based on the block call, a key value call; and sending the key value call to a key value frontend of the storage system.

Abstract: A memory device such as a page mode NAND flash, including a page buffer with first and second-level buffer latches is operated using a first pipeline stage, to transfer a page to the first-level buffer latches; a second pipeline stage, to clear the second-level buffer latches to a third buffer level and transfer the page from the first-level buffer latches to the second-level buffer latches; and a third pipeline stage to move the page to the third buffer level and execute in an interleaved fashion a first ECC function over data in a first part of the page and output the first part of the page while performing a second ECC function, and to execute the first ECC function over data in a second part of the page in the third buffer level, and to output the second part while performing the second ECC function.

Abstract: Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.

Abstract: Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices.

Abstract: A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.

Abstract: Techniques are provided for mitigating issues of memory hole mis-shape. In one aspect, one or more control circuits are configured to program a group of non-volatile memory cells from an erase state to a plurality of programmed states using a first program parameter. The one or more control circuits measure threshold voltages of the group to determine a severity of memory hole mis-shape in the group. The one or more control circuits program the group from the erase state to the plurality of programmed states using a second program parameter selected based on the severity of the memory hole mis-shape in the group.

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.

Abstract: A memory system includes a memory device configured to store data, and read and output the stored data in a read operation, and a memory controller configured to perform an error correction operation on the data received from the memory device in the read operation and control the memory device to perform a read retry operation, based on the result of the error correction operation. The memory device outputs the data read in the read retry operation to the memory controller when the number of specific data, among data read in the read retry operation, is in a set range. Only reliability-ensured data in the read retry operation is output to the memory controller. Thus, the number of times of outputting data to the memory controller can be decreased, and the number of times where the memory controller performs an error correction operation can be decreased.

Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.

Abstract: A partial page sensing method and system are provided in which, while a bit line voltage (VBLC) is applied to first bit lines of a first partial page of a memory cell array, second bit lines, of a second partial page are floated. The second bit lines of the second partial page are bit lines which are interleaved with the first bit lines of the first partial page. Bit lines associated with one or more additional partial pages may be grounded or floated. A bit line associated with an additional partial page which is adjacent to one of the first bit lines may be floated.

Abstract: A memory device includes an array of memory cells that has a first sub array and a second sub array. A plurality of bit lines are connected to the memory cells, and an IO block is situated between the first sub array and the second sub array. The bit lines extend from the first and second memory sub arrays of the memory device directly to the IO block. The IO block further includes data input and output terminals configured to receive data to be written to the array of memory cells and output data read from the array of memory cells via the plurality of bit lines.

Abstract: According to one embodiment, a memory system includes a memory and a controller electrically connected to the memory. The memory includes blocks. Each of the blocks includes one or more sub-blocks. Each of the one or more sub-blocks includes nonvolatile memory cells. The controller is configured to obtain read frequency of at least one of the sub-blocks, and move data stored in the at least one of the sub-blocks so that data having substantially the same read frequency are written into one block.

Abstract: A semiconductor integrated circuit includes a first power supply line, a second power supply line, and a voltage supplied circuit. The first power supply line is connected to a voltage supply source. The second power supply line is connected to the first power supply line at a connection point connecting a first point of the first power supply line and a second point of the second power supply line. The second point is included in a portion of the second power supply line excluding end portions of the second power supply line. The voltage supplied circuit is connected to the second power supply line.

Abstract: A memory system includes a plurality of memory cells and a controller. During a write operation to write data to the memory cells, the controller encodes first data to be written at a first code rate. During a read operation to read data from the memory cells, the controller decodes second data read from the memory cells at the first code rate. The controller changes the first code rate to a second code rate that is less than the first code rate upon determining that the number of error bits during the read operation of the second data is above a threshold number for error bits or upon determining that the number of memory cells having a threshold voltage that is in a voltage range that includes a read voltage is above a threshold number for memory cells.

Abstract: A semiconductor memory device comprises a first memory cell array including a first memory cell and a second memory cell array including a second memory cell, a first transistor electrically connectable to a first end of the first memory cell via a first source line, a second transistor connectable to a first end of the second memory cell via a second source line, a pad supplied with a reference voltage from outside, a first wiring that electrically connects the first transistor and the pad, and a second wiring that is different from the first wiring and electrically connects the second transistor and the pad.

Abstract: According to an embodiment, a semiconductor storage device includes a first memory cell and a control circuit. The first memory cell is configured to store first data. The control circuit is configured to apply a first voltage to a source of the first memory cell in a read operation of the first data in the first memory cell, and to apply a second voltage to the source of the first memory cell in a verify operation of the first data in the first memory cell. The second voltage is lower than the first voltage.

Abstract: A method for operating a memory system includes: detecting a first erase page of a super block, which is formed of memory blocks, by scanning the super block according to a binary search scheme based on a program order in which pages in the super block are programmed; and performing a Sudden Power Off Recovery (SPOR) based on the detected first erase page.

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.

Abstract: A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage.

Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.