Abstract: A nonvolatile memory device includes a nonvolatile memory cell and a variable resistive load portion. The variable resistive load portion is coupled between a bit line of the nonvolatile memory cell and a supply voltage line. The variable resistive load portion is suitable for changing a resistance value between the bit line and the supply voltage line according to a level of a supply voltage applied to the supply voltage line.

Abstract: Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.

Abstract: A semiconductor memory device may include a memory cell array including a plurality of memory cells, and a plurality of page buffers respectively coupled to a plurality of bit lines of the memory cell array, the page buffers being supplied with internal voltages to precharge the plurality of bit lines or to sense an amount of current flowing through the plurality of bit lines, during a sensing operation, wherein each of the page buffers converts the internal voltages into supply voltages having constant potential levels.

Abstract: Systems and methods for sampling data at a non-volatile memory system are disclosed. In one implementation, a controller of a non-volatile memory system that is coupled with a host device acquires a read level voltage of a first word line of a memory block of a non-volatile memory of the non-volatile memory system. The controller accesses one or more lookup tables to determine an offset voltage for a second word line of the memory block based on a program/erase count and a read/disturb count associated with the memory block; applies the read level voltage and the offset voltage to the second word line to sample data stored at the memory block; and determines whether the data sampled from the memory block contains errors.

Abstract: A sensing buffer, or peripheral circuit or memory device may be provided. The sensing buffer may be configured to maintain a predetermined current according to a first current regardless of an external power supply and/or a temperature.

Abstract: In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.

Abstract: Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing row of the corresponding tables for each of the different memory planes, with each code corresponding to a data state of one of the memory cells.

Abstract: Disclosed herein is a NAND flash memory comprising a bit-line and a page buffer, the page buffer comprising: a first switching circuit arranged between a first node and the bit-line; a third switching circuit arranged between the first node and a sensing node and configured to discharge the sensing node during an evaluation period, a pre-charging period preceding the evaluation period; and a fourth switching circuit configured to provide a first pre-charging path to the bit-line through the first node and the first switching circuit from a first voltage source during the pre-charging period, wherein the sensing node is configured to be charged through a second pre-charging path during the pre-charging period, and the second pre-charging path is separated from the first pre-charging path by the third switching circuit during the pre-charging period.

Abstract: A method includes storing data in memory cells by programming the memory cells with respective values. The memory cells are read in multiple readout operations that each compares the programmed values to at least first and second read thresholds, while keeping the first read threshold fixed throughout the readout operations and perturbing only the second read threshold between the readout operations. A preferred value for the second read threshold is estimated based on the multiple readout operations.

Abstract: An operation method of a semiconductor memory system includes performing a first error correction code (ECC) decoding on a first data stored in the semiconductor memory system, wherein the first data includes user data, an ECC data for the user data and a status data for the user data; and performing a second ECC decoding on the user data by changing a read voltage based on the status data of the first data when the first ECC decoding on the user data fails.

Abstract: A method for storing data in a storage system having solid-state memory is provided. The method includes determining portions of the solid-state memory that have a faster access rate and portions of the solid-state memory that have a slower access rate, relative to each other or to a threshold. The method includes writing data bits of erasure coded data to the portions of the solid-state memory having the faster access rate, and writing one or more parity bits of the erasure coded data to the portions of the solid-state memory having the slower access rate. A storage system is also provided.

Abstract: A semiconductor memory apparatus and a data processing method are provided. The semiconductor memory apparatus gives consideration to partial page programming and data scrambling, and improves the reliability. In the flash memory of the present invention, when data is programmed to a page n times consecutively, identification information and program information are generated. A scrambled data, the location information and the flag information are programmed to a selected page in a memory array. The location information indicates a storage location for a data scrambling in the page selected based on an input address information. The flag information is used to identify a storage region specified by the location information is programmed.

Abstract: A semiconductor device, including: interlayer insulating patterns and conductive patterns alternately stacked on a substrate; a channel structure passing through the interlayer insulating patterns and the conductive patterns; and tapered patterns interposed between the channel structure and the interlayer insulating patterns, spaced apart with any one of the conductive patterns interposed therebetween, and having widths decreased toward the substrate.

Abstract: A program method of a nonvolatile memory device includes loading first word line data to be stored in first memory cells connected to a first word line and second word line data to be stored in second memory cells connected to a second word line; setting up upper bit lines according to the first word line data; turning off bit line sharing transistors after the upper bit lines are set up; setting up lower bit lines according to the second word line data; performing a first program operation on the first memory cells using the upper bit lines; turning on the bit line sharing transistors; and performing a second program operation on the second memory cells using the lower bit lines. The bit line sharing transistors electrically connect the upper bit lines and the lower bit lines in response to a bit line sharing signal.

Abstract: A semiconductor memory device may include a memory cell array, two or more global word lines, and two or more path circuits. The two or more global word lines may be coupled to word lines in parallel. At least one of the two or more path circuits may be coupled between portions of each word line portions of each word line. Each path circuit may couple one of the global word lines to one of the word lines.

Abstract: Disclosed herein are techniques for sensing multiple reference levels in non-volatile storage elements without changing the voltage on the selected word line. One aspect includes determining a first condition of a selected non-volatile storage element with respect to a first reference level based on whether a sensing transistor conducts in response to a sense voltage on a sense node. Then, a voltage on the source terminal of the sensing transistor is modified after determining the first condition with respect to the first reference level. A second condition of the selected non-volatile storage element is then determined with respect to a second reference level based on whether the sensing transistor conducts in response to the sense voltage on the sense node. This allows two different reference levels to be efficiently sensed. Dynamic power is saved due low capacitance of the sensing transistor relative to the sense node.

Abstract: An array of programmable non-volatile devices, such as a nominal OTP cell, is operated such that a Vt representing a particular binary logic state is changed over time. This allows for re-programming and emulating a few times or multi-time programmable device.

Abstract: Provided are a nonvolatile memory and a data reading method of reading data from a nonvolatile memory by the memory controller. The data reading method includes reading data from memory cells of the nonvolatile memory, storing the read data in the internal memory, overwriting some of the read data stored in the internal memory with backup data, performing an error correction operation using the backup data stored in the internal memory, and overwriting the backup data stored in the internal memory with data corrected by the error correction operation.

Abstract: A memory system includes: a bit counter and a regression analyzer. The bit counter is configured to generate a plurality of count values based on data read from selected memory cells using a plurality of different read voltages, each of the plurality of count values being indicative of a number of memory cells of a memory device having threshold voltages between pairs of the plurality of different read voltages. The regression analyzer is configured to determine read voltage for the selected memory cells based on the plurality of count values using regression analysis.

Abstract: An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit lines connected thereto, respectively. First and second latch nodes of the first page buffer are charged to have a voltage having a first level according to data stored in a first latch of the first page buffer. After the charging of the first latch node is started, a sensing node of the second page buffer is pre-charged. The sensing node is connected to the second bit line. Data stored in the first latch is dumped into a second latch of the first page buffer during the pre-charging of the sensing node of the second page buffer.

Abstract: Apparatuses and methods involving accessing memory cells are described. In one such method, chunks of memory cells in a memory array are enabled to be accessed and then one or more of the chunks are disabled from being accessed. In one such apparatus, an array includes chunks of memory cells and a chunk selector circuit coupled to each chunk to enable the memory cells in the respective chunk to be accessed. Additional embodiments are described.

Abstract: A nonvolatile memory device, including a first latch unit and a nonvolatile memory cell, and a method of writing data in a nonvolatile memory device are provided. The method includes receiving a first writing command or a second writing command from outside of the nonvolatile memory device, and writing first data stored in the first latch unit in the nonvolatile memory cell in response to the first or second writing command. The first data is retained in the first latch unit until the writing of the first data stored in the first latch unit in the nonvolatile memory cell is completed.

Abstract: A method for programming a memory device comprises the following steps: performing an interleaving programming, including: programming a first memory cell during a first time interval and correspondingly verifying the first memory cell during a second time interval; programming a second memory cell during a third time interval and correspondingly verifying the second memory cell during a fourth time interval between the first and second time intervals; and inserting at least one dummy cycle between the first and second time intervals to ensure that a resistance change per unit of time of the first memory cell is less than a threshold.

Abstract: Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

Abstract: A field effect transistor having a diamond gate electrode and a process for forming the same. In some embodiments, the device is an AlGaN/GaN high-electron-mobility transistor (HEMT). The diamond gate electrode is formed so that it directly contacts the barrier layer. In some embodiments, the diamond gate electrode is formed from boron-doped nanocrystalline diamond (NCD), while in other embodiments, the diamond gate electrode is formed from single crystal diamond.

Abstract: This invention discloses a HiNAND array scheme with multiple-level of bit lines (BLs) including metal3 global bit lines (GBLs), divided metal2 Segment bit lines (SBLs), and divided metal1 block bit lines (BBLs) laid out in parallel to each other respectively for a plurality of NAND Strings. All other source lines or power lines connected to bottoms of corresponding String capacitances of GBLs, SBLs, and BBLs are associated with metal0 line laid out perpendicular to those BLs. Under the HiNAND array scheme, conventional one-WL Read and Program-Verify operations are replaced by multiple-WL and All-BL Read and Program-Verify operations executed with charge capacitance of SBLs being reduced to 1/10- 1/20 of capacitance of GBLs to achieve DRAM-like faster operation, less operation stress, and lower power consumption. A preferred set of program biased voltages on the selected WL and remaining non-selected WLs associated with a Multiplier and a DRAM-like charge-sharing Latch Sensing Amplifier is proposed.

Abstract: A nonvolatile memory apparatus includes: a memory cell coupled to a bit line and a source line; a word line configured to select the memory cell; and a local switch block configured to apply a write voltage, a read voltage, and a source line voltage to the bit line and the source line in response to a local switch select signal. In a write or read operation of the nonvolatile memory apparatus, the word line has a first voltage level, and the local switch select signal has a second voltage level higher than the first voltage level.

Abstract: A programming method is for programming a nonvolatile memory device including a plurality of strings disposed perpendicular to a substrate and connected between bitlines and a common source line. The programming method includes setting up the common source line to a predetermined voltage, floating the setup common source line, performing a program operation on memory cells connected to a selected wordline, and performing a verify operation on the memory cells.

Abstract: A program verification method is for a nonvolatile memory device which programs a plurality of memory cells. The program verification method includes applying a plurality of verification voltages, and determining whether programming of memory cells, having different target threshold voltage distributions, from among the plurality of memory cells is completed based on one of the plurality of verification voltages.

Abstract: A program method of a nonvolatile memory device includes loading first word line data to be stored in first memory cells connected to a first word line and second word line data to be stored in second memory cells connected to a second word line; setting up upper bit lines according to the first word line data; turning off bit line sharing transistors after the upper bit lines are set up; setting up lower bit lines according to the second word line data; performing a first program operation on the first memory cells using the upper bit lines; turning on the bit line sharing transistors; and performing a second program operation on the second memory cells using the lower bit lines. The bit line sharing transistors electrically connect the upper bit lines and the lower bit lines in response to a bit line sharing signal.

Abstract: According to one embodiment, a memory system includes a NAND-type flash memory and a memory controller. The memory controller includes a monitoring module and a determination module. The monitoring module acquires an elapsed time from the start of data erase of a first block in the NAND-type flash memory. The determination module determines whether the elapsed time has exceeded a reference time before completion of the data write in the first block.

Abstract: An EPROM cell array includes a cell array including multiple unit cells, each of which includes a MOSFET having a floating gate, and which are disposed in an array with a plurality of rows and a plurality of columns; multiple first selection lines each coupled with drains of unit cells, which are disposed on the same row among the multiple unit cells; and multiple second selection lines each coupled with sources of unit cells, which are disposed on the same column among the unit cells, wherein a selected unit cell to be programmed or read is selected by one of the multiple first selection lines, and one of the multiple second selection lines.

Abstract: A one-time programmable (OTP) memory includes an OTP cell array including a plurality of OTP cells that each include a programming transistor configured to change irreversibly when programmed; a temperature compensation reference voltage generating unit configured to sense a temperature of the OTP cell memory and generate a reference voltage such that as the sensed temperature changes, the reference voltage generated by the temperature compensation reference voltage generating unit changes in a manner that is inversely proportional the change in the sensed temperature; and a temperature compensation operating voltage generating unit configured to receive the reference voltage to generate an operating voltage that is proportional to the reference voltage and is applied to the OTP cell array.

Abstract: A split-gate flash memory cell (cell) includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second floating gate (FG) are on the semiconductor surface. A common source or common drain is between the first and second FG. A first select gate and a second select gate on a select gate dielectric layer is between a first BL source or drain (S/D) and the first FG and between a second BL S/D and the second FG, respectively. The first select gate has a first pocket region that has a first doping distribution different from a second doping distribution in a second pocket region associated with the second select gate which reduces a variation in read current (Ir) for the cell between measuring Ir using the first select gate and measuring Ir using the second select gate.

Abstract: A field effect transistor having a diamond gate electrode and a process for forming the same. In some embodiments, the device is an AlGaN/GaN high-electron-mobility transistor (HEMT). The diamond gate electrode is formed so that it directly contacts the barrier layer. In some embodiments, the diamond gate electrode is formed from boron-doped nanocrystalline diamond (NCD), while in other embodiments, the diamond gate electrode is formed from single crystal diamond.

Abstract: The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status of a page of memory cells without using input/output (I/O) circuitry, and outputting the status through the I/O circuitry.

Abstract: Methods and systems for determining system lifetime characteristics are described. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using a number of trim parameters at a testing level, and determine a system lifetime characteristic based, at least partially, on the number of operations performed on the number of memory devices using the number of trim parameters at the testing level.

Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a control unit, in a data write, determining at least one of: a first requirement that the number of times of a data read on first through n1-th pages (where n1 is an integer of 1 to N?1) of a target block executed after the most recent data erase on the target block, is less than a reference number of times; and a second requirement that the number of memory cells whose threshold voltage is higher than a reference voltage, of a plurality of memory cells of a reference page of n1+1-th through N-th pages of the target block, is less than a reference number, and when the determined requirement is satisfied, writing additional data to the n1+1-th through N-th pages of the target block.

Abstract: A p-channel flash memory device including a 3D NAND array has excellent performance characteristics. Techniques for operating 3D, p-channel NAND arrays include selective programming, selective (bit) erase, and block erase. Selective programming bias arrangements induce band-to-band tunneling current hot electron injection to increase threshold voltages in selected cells. Selective erase biasing arrangements induce ?FN hole tunneling to decrease threshold voltages in selected cells. Also, block erase bias arrangements induce ?FN hole tunneling in selected blocks of cells.

Abstract: Methods and apparatus are disclosed related to a memory device, such as a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data.

Abstract: A method for testing an integrated circuit having memory comprises performing a structural test on the integrated circuit using data obtained from operating the memory in a functional mode. In another embodiment, an integrated circuit comprises a memory mode selection module, a memory module, and an output selection module. The memory mode selection module is configured to receive a functional mode signal and a test mode signal, and selectively transmit either the functional mode signal or the test mode signal based on a state of a control signal. The memory module is configured to receive the signal from the memory mode selection module and store data corresponding to signal to memory cells. The output selection module is configured to receive the data from the memory cells, and transmit the data to downstream circuitry, which may use the data to perform a structural test, such as a logic built-in self-test.

Abstract: This invention discloses a low-voltage fast-write 12T or 14T PMOS NVSRAM cell structure which comprises a 6T LV SRAM cell and one pairs of two 3T or 4T HV PMOS Flash strings. Due to reverse threshold voltage definition of PMOS and NMOS flash cell, this PMOS NVSRAM cell has the advantage over the NMOS NVSRAM cell to have the same data polarity between SRAM and Flash pairs during the data writing operation. In addition, this PMOS NVSRAM's PMOS Flash cell uses similar low-current FN-tunneling scheme as NMOS NVSRAM, thus the fast data program and erase can be achieved in a big density up to 100 Mb simultaneously. As a result, low power voltage operation of NVSRAM with 1.2V VDD can be much easier to be designed without coupling the FSL line to any VDD level during the flash data loading into SRAM cell during a power-on period.

Abstract: According to one embodiment, a semiconductor memory device reads data in units of page. The device includes: a memory cell array; a plurality of latch circuits; and an arithmetic operation circuit. The memory cell array holds data multiplexed in at least three pages. The latch circuits read and hold the multiplexed data at a startup. The arithmetic operation circuit performs operations by use of the multiplexed data.

Abstract: A nonvolatile memory device is provided which includes a cell array including a plurality of memory cells; a page buffer unit including a plurality of page buffers and configured to sense whether programming of selected memory cells is completed, at a program verification operation; and a control logic configured to provide a set pulse for setting data latches of each of the page buffers to a program inhibit state according to the sensing result, wherein the control logic provides the set pulse to at least two different page buffers such that data latches of the at least two different page buffers are set.

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

Abstract: A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programming operation performed on the memory device is performed and before a subsequent portion of the particular programming operation performed on the memory device is performed. The controller is configured to determine the program window responsive to an amount of program disturb experienced by a particular state of a memory cell. The controller is configured to perform the subsequent portion of the particular programming operation performed on the memory device using the determined program window.

Abstract: A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.

Abstract: A method of operation of an electronic system includes: forming a superblock by organizing an erase block according to a wear attribute; detecting a trigger count of the wear attribute of the superblock; updating a metadata table with the trigger count; and triggering a recycling event of the superblock based on the metadata table.

Abstract: It is possible to accurately detect a physical block which has caused a fixture defect in a flash memory so as to limit the use of the physical block. By recording a history of generation of a physical block error and a history of physical erasing in an ECC error record, it is judged whether the error which has occurred is accidental or caused by a fixture defect. When no error is caused in the data written by physical erasing after a first read error occurrence, the first error is accidental and if another error is caused, the error is judged to be caused by a fixture defect. By using such an ECC error record, it is possible to accurately judge whether the error is accidental or caused by a fixture defect. By eliminating use of the physical block judged to have a fixture defect, it is possible to reduce read errors.

Abstract: Systems, computer readable media and methods for updating a flash memory device involve procedures for transferring, from a flash memory device to an external controller, only a portion of a data entity; and determining, by the external controller, based upon the portion of the data entity, whether to complete a copy back operation of the data entity or to correct errors of the data entity. If it is determined to correct errors of the data entity, then the procedure includes (a) completing a transfer of the data entity to the external controller; (b) error correcting the data entity to provide an amended data entity; and (c) writing the amended data entity to the flash memory device. If, however, it is determined to complete the copy back operation then the procedures includes completing the copy back operation of the data entity by transferring the data entity within the flash memory device.