Abstract: A memory control apparatus includes a randomizer configured to: randomize write data output from an arithmetic processing apparatus, and output the randomized write data to a memory; a derandomizer configured to: derandomize data read from the memory, and generate derandomized read data when a flag included in the data read from the memory indicates the randomized write data; and a selector configured to: select the derandomized read data and output the selected derandomized read data to the arithmetic processing apparatus when the flag indicates the randomized write data, and select the data read from the memory and output the selected read data to the arithmetic processing apparatus when the flag indicates deleted data.

Abstract: A semiconductor storage device includes a source line, a first selection line, word lines, a dummy word line, and a second selection line. A first pillar having a first semiconductor layer extends through the first selection line, the word lines, and the first dummy word line and is connected to the source line. Memory cells are at intersections of the word lines and the first pillar. A conductive layer is on the first semiconductor layer and extends into the first dummy word line. A second pillar with a second semiconductor layer extends through the second selection line and contacts the conductive layer. A bit line is electrically connected to the second semiconductor layer. A control circuit is configured to apply voltages to the various lines during an erasing of the memory cells. A voltage between a source line voltage and a world line voltage is applied to dummy word line.

Abstract: The present disclosure relates to examples of reducing memory write operations using coalescing memory buffers. In one example implementation according to aspects of the present disclosure, a method comprises computing a difference between a current state of data of at least one block of a storage device to which data is to be written and a state that would result from a write operation. The method further comprises populating at least one coalescing memory buffer with difference information associated with the difference and to be used to update an associated block of the storage device.

Abstract: A 3D memory device includes a multi-layers stacking structure having a plurality of conductive layers and insulating layers stacked in a staggered manner, at least one trench passing through the conductive layers and a plurality of recess regions extending into the conductive layers from the trench; a dielectric blocking strip lining sidewalls of the trench and the recess regions; a plurality of floating gates disposed in the recess regions and isolated from the conductive layers by the dielectric blocking strip; a dielectric strip overlies sidewalls of the floating gates exposed from the recess regions; a semiconductor strip disposed in the trench, insulated from the floating gates by the dielectric strip, and includes a first doping region, a second doping region and a channel region disposed between and connects to the first doping region and the second doping region, and overlapping with the floating gates.

Abstract: A method of erasing a memory device, the method of erasing the memory device including: performing, in a first erase period, a first erase operation on memory cells respectively connected to a plurality of word lines, wherein at least one of the memory cells, which is included in a memory block, is not erase-passed; determining, after the first erase period, an erase operation speed by applying a verify voltage to at least one of the plurality of word lines, and determining an effective erasing time for each word line based on the determined erase operation speed; and performing, in a second erase period, a second erase operation on the memory cells respectively connected to the plurality of word lines based on the determined effective erasing times.

Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.

Abstract: A storage system according to one aspect of the present invention includes a plurality of storage devices using flash memory as a storage medium. The flash memory used for the storage device may include flash memory configured to operate each cell as a cell capable of storing n-bit information or a cell capable of storing m-bit information (where n<m). The storage system may periodically acquire a number of remaining erasures from the storage device and predict the lifetime of the storage device by using the acquired number of remaining erasures and the storage device operation time. If the predicted lifetime is less than a predetermined value (service life) a predetermined number of cells may be changed to cells capable of storing n-bit information.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.

Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.

Abstract: A method for programming memory blocks in a memory system includes identifying, using at least one memory block characteristic, candidate memory blocks of the memory blocks in the memory system. The method also includes performing a pre-erase operation, using a pre-erase verify level, on the candidate memory blocks. The method also includes storing, on a pre-erase table, pre-erase information for each memory block of the candidate memory blocks. The method also includes identifying, using the pre-erase table, at least one memory block to be programmed. The method also includes programming the at least one memory block by performing a preprogram erase operation on the at least one memory block using the pre-erase verify level, and performing a write operation on the at least one memory block.

Abstract: A semiconductor memory device improving a high-temperature data retention is provided. Here, a flash memory includes an erasing element erasing a selected storage cell in a storage cell array. The erasing element further includes an applying element, a verifying element, and a decision element. The applying element applies a monitoring erasing pulse to a monitoring storage cell before starting an erasing operation for selecting the storage cell. The verifying element performs a verification of the monitoring storage cell to which the monitoring erasing pulse is applied. The decision element determines ISPE conditions based on a verification result of the verifying element. The erasing element erases the storage cell according to the determined ISPE conditions.

Abstract: A method of manufacturing three-dimensional semiconductor device, comprising the steps of: a) forming a device unit on a substrate, the said device includes a plurality of stack structures composed of the first material layer and the second material layer stacked along a direction perpendicular to the substrate surface; b) forming a contact lead-out region around the said device unit, the contact lead-out region comprises a plurality of sub-partitions, each of the sub-partitions respectively exposes a different second material layer; c) forming a photoresist on said substrate, covering said plurality of sub-partitions, exposing a portion of said second material layer; d) using the photoresist as a mask, simultaneously etching the portion of the second material layer exposed by said plurality of sub-partitions, until another second material layer beneath said second material layer is exposed; e) slimming the size of the photoresist to expose a portion of said another second material layer; f) repeating said st

Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.

Abstract: Techniques for reducing read disturb of memory cells in a two-tier stack having a lower tier and an upper tier separated by an interface. In a read operation, the channels of NAND strings are discharged before reading the selected memory cells. The discharge involves ramping up the word line voltages and grounding the ends of the NAND strings. To increase the discharge, a ramp up rate may be greater for the selected word line and for dummy memory cells adjacent to the interface, compared to the ramp up rate for the unselected word lines. In an option, the greater ramp up rate is also used for the word lines between the selected word line and the interface. In another option, the greater ramp up rate is used for the word lines in the same tier as the selected word line.

Abstract: A non-volatile memory and its reading method are provided. The reading method includes: erasing a plurality of memory cells in a memory cell string; setting a target memory cell of the memory cells, setting an initial voltage, generating a plurality of programming voltages by gradually increasing the initial voltage based on a step value, sequentially performing a plurality of programming operations by the target memory cell according to the programming voltages, and verifying the target memory cell to obtain a first verifying current during the programming operations; setting a corresponding programming voltage as a target voltage through determining the first verifying current and a first reference current; and performing the programming operations on the memory cells other than the target memory cell according to the target voltage and setting the memory cell string as a reading reference memory cell string.

Abstract: Apparatus, systems, methods, and computer program products for managing refresh operations in memory devices are disclosed. An apparatus includes a memory device including a plurality of memory cells comprising an associated set of counters and a controller for the memory device. A controller is configured to randomly increment a counter associated with a memory cell in response to write disturbances for the memory cell. A controller is configured, in response to a counter being randomly incremented to a predetermined count, perform a refresh operation on a memory cell.

Abstract: A memory device includes gate electrode layers stacked on an upper surface of a substrate and each including a plurality of unit electrodes extending in a first direction, and a plurality of connecting electrodes connecting the unit electrodes to each other. The memory device also includes channel structures extending through the gate electrode layers in a direction perpendicular to the upper surface of the substrate, first common source lines extending in the first direction and interposed between the unit electrodes, and second common source lines extending in the first direction between the first common source lines and each having a first line and a second line separated from each other in the first direction by the connecting electrodes.

Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.

Abstract: An operating method of the soft-verify write assist circuit of the resistive memory provides a voltage level applying step, a write operating step and a write voltage controlling step. The voltage level applying step is for applying a plurality of voltage levels to the reference voltage, the word line and the switching signal, respectively. The write operating step is for driving the memory cell to perform in a set process or a reset process via the first three-terminal switching element, the second three-terminal switching element and the soft-verify controlling unit during a write operation. The write voltage controlling step is for controlling the write voltage to be increased in the ramping cycle and decreased in the soft-verify cycle.

Abstract: According to an embodiment, element models include a first transistor model, a second transistor model, and a variable resistor model. The first transistor model simulates a characteristic of a selection gate transistor whose channel resistance is changed by a selection gate voltage applied to a selection gate. The second transistor model simulates a characteristic of a memory gate transistor whose channel resistance is changed by a memory gate voltage applied to a memory gate. The variable resistor model has a resistance value which is changed in accordance with the selection gate voltage and the memory gate voltage and which is set to correspond to a gap region formed in a lower part of an insulating film insulating between the selection gate and the memory gate. The variable resistor model is provided between the first transistor model and the second transistor model.

Abstract: Techniques for reducing program disturb of memory cells which are formed in a two-tier stack, when a selected word line is in the upper tier. In one approach, at the start of the program phase of a program loop, voltages of word lines adjacent to the interface are increased to a pass voltage before voltages of remaining word lines are increased to a pass voltage. This delay provides time for residue electrons in the lower tier to move toward the drain end of a NAND string to reduce the likelihood of program disturb. In another approach, the voltages of the word lines adjacent to the interface are maintained at 0 V or other turn-off voltage during the program phase to block the passage of residue electrons from the lower tier to the upper tier.

Abstract: A controller includes a calculation unit suitable for calculating a first criteria value, a second criteria value, and a valid page ratio of each of a plurality of first memory blocks included in a first memory block group a memory device of the memory system, a decision unit suitable for deciding as a copy candidate a first memory block having a valid page ratio equal to or smaller than the first criteria value; and a processor suitable for controlling the memory device to copy data of the copy candidate to a second memory block in the memory device when the valid page ratio of the copy candidate is equal to or smaller than the second criteria value.

Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

Abstract: A memory system includes: a nonvolatile memory device including a plurality of memory blocks; and a controller suitable for dividing the plurality of memory blocks into a first group and a second group, and controlling the memory blocks included the first group and the second group, respectively, wherein the controller is further suitable for: managing all operations except for an erase operation to the memory blocks of the first group through a first operation task; managing all operations except for an erase operation to the memory blocks of the second group through a second operation task; and managing the erase operation to the memory blocks of the first group and the memory blocks of the second group through an erase operation task.

Abstract: A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).

Abstract: Methods and apparatus are described for partitioning and reordering block-based matrix multiplications for high-speed data streaming in general matrix multiplication (GEMM), which may be implemented by a programmable integrated circuit (IC). By preloading and hierarchically caching the blocks, examples of the present disclosure reduce the double data rate (DDR) memory intake bandwidth for software-defined GEMM accelerators.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a voltage generator suitable for applying an erase voltage to a source line of at least one memory block selected from among the plurality of memory blocks during an erase operation, a read and write circuit suitable for applying an initial setting voltage, to bit lines of at least one memory block during the erase operation, and a control logic suitable for controlling the voltage generator and the read and write circuit to apply the initial setting voltage to the bit lines before applying the erase voltage to the source line.

Abstract: A method of providing, by a controller, a log likelihood ratio (LLR) to a low-density parity check (LDPC) decoder, the method comprising storing, in a non-volatile memory controller, a look-up table for storing LLR values of at least one bit representing a charge state of a cell of the plurality of cells in the memory. The controller determines a cell charge state of the target cell, calculates a value representative of the difference in charge states of the target cell and at least one of a plurality of neighboring cells. The controller compares the calculated value with at least one predetermined threshold value, and sets at least one address bit of an address to the look-up table if the calculated value exceeds the at least one threshold value. The controller extracts a new LLR value from the look-up table, and provides the new LLR value to the LDPC decoder.

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

Abstract: A method for managing data using a number of non-volatile memory arrays is described. The method includes writing data from a volatile memory region to a first non-volatile memory array. The method also includes writing a remaining portion of the data from the volatile memory region to a second non-volatile memory array in response to detecting that an event has occurred. The second non-volatile memory array has a lower write latency than the first non-volatile memory array.

Abstract: In one embodiment, the method includes buffering, under control of a memory controller, received data and an associated program entity in a buffer. The program entity includes first address information and second address information, the first address information indicates an address of the buffer storing the received data, and the second address information indicates an address in the memory to store the received data. The method further includes storing, at the memory controller, management information. The management information includes program information, and the program information includes a pointer to the program entity in the buffer. The method also includes transferring the received data from the buffer to the memory based on the management information and the program entity.

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

Abstract: This disclosure is directed at least partly to a kiosk that provides high speed data transfer of content to a user device associated with the user. The kiosk may be located in frequently visited locations such as travel terminals or public spaces. The kiosks may provide instructions to users about how to receive some of the content on user devices via a high speed data transfer. The kiosk may detect and prepare a user device for receipt of electronic content by wirelessly exchanging information with the user device, such as consent information, memory allocation information, and/or other relevant data. The high speed data transfer may use high speed data transfer protocols that enable download of full-length movies in a matter of a few seconds.

Abstract: A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.

Abstract: Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.

Abstract: Subject matter disclosed herein relates to memory management, and more particularly to partitioning a memory based on memory attributes.

Abstract: A method for operating a memory system includes determining at least one erased memory cell among a plurality of erased memory cells as an unstable memory cell based on read data read from the at least one erased memory cell; determining the unstable memory cell as an unwritable memory cell based on write data to be written in the unstable memory cell; and prohibiting the plurality of erased memory cells from being used, depending on the number of erased memory cells as the unwritable memory cell among the plurality of erased memory cells.

Abstract: Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.

Abstract: A non-volatile memory device includes: a memory cell array including a memory cell string including a ground selection transistor and a plurality of serially connected non-volatile memory cells; a ground selection line connected to the ground selection transistor and a plurality of word lines connected to the plurality of memory cells; a voltage generator configured to generate a program verification voltage and a read voltage applied to the plurality of word lines; and a control circuit configured to control a compensation for the program verification voltage based on a program verification temperature offset, and control a to compensation for the read voltage based on a read temperature offset.

Abstract: A semiconductor device and or method of operating the same may be provided. The semiconductor device may include a pass circuit unit configured to connect global signal lines to signal lines to set voltage levels of the signal lines.

Abstract: A nonvolatile memory controller and a method for erase suspend management are disclosed. The nonvolatile memory controller includes an erase suspend circuit configured for determining a pre-suspend time each time that an erase operation of the nonvolatile memory device is suspended and for determining whether an erase-suspend limit has been reached using the determined pre-suspend time. The erase suspend circuit is further configured for incrementing the number of program and erase cycles when the erase-suspend limit has been reached.

Abstract: The invention provides a semiconductor memory device and a reading method thereof, which are capable of suppressing a peak current when pre-charging a bit line are provided. The reading method of a flash memory of the present invention includes steps of: pre-charging a selected bit line; and reading a voltage or a current of the pre-charged selected bit line. The step of pre-charging is performed by pre-charging a sense node SNS to Vcc?Vth at a time t1, pre-charging a node TOBL to VCLAMP2 at a time t2, pre-charging the node TOBL to VCLAMP1 at a time t5, and pre-charging the sense node SNS to Vcc at a time t6.

Abstract: Several embodiments include a host computer coupled to a solid state drive (SSD). The filesystem of the host computer can receive a write pointer from the firmware of the SSD. The write pointer can reference a next available page to an erase block in the SSD. In response to a file write request to store a target file, the filesystem can determine a logical address range to store at least a portion of the target file based on the file write request and the write pointer. The filesystem can then generate a sector write command to send to the SSD. The sector write command can specify the determined logical address range.

Abstract: An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line.

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Abstract: A system configures a mobile device. The system includes a battery and a mobile device. The battery includes at least one power storage cell and a memory arrangement, the memory arrangement storing staging profile data, the staging profile data including configuration data. The mobile device is configured to be coupled to the battery, the mobile device being powered by the at least one power storage cell, the mobile device receiving the staging profile data from the memory arrangement, the mobile device being automatically configured for communication with a communication network as a function of the configuration data.

Abstract: A memory system may include: a memory device comprising a plurality of memory blocks each having N word line groups; and a controller suitable for: selecting bad memory blocks among the plurality of memory blocks, arranging normal word line groups of the selected bad memory blocks into one or more memory-block-word-line groups each including non-conflicting N normal word line groups, and managing each of the memory-block-word-line groups as a reused memory block.