Abstract: A semiconductor memory apparatus includes a data input enable signal generation block configured to sequentially delay a data strobe signal to generate a first delayed data strobe signal, a second delayed data strobe signal, a third delayed data strobe signal and a fourth delayed data strobe signal, and generate a data strobe enable signal in response to a CAS write signal, a CAS write latency signal and the first to fourth delayed data strobe signals, a latch control signal generation block configured to output the data strobe signal as a latch control signal during an enable period of the data strobe enable signal, and a data latch block configured to latch data in response to the latch control signal and output latched data.

Abstract: A circuit for a semiconductor memory device includes: a filtering control signal generation unit configured to synchronize a seed signal activated in a pre-amble period of a data strobe signal with the data strobe signal and sequentially generate a plurality of filtering control signals in response to the seed signal; and a filtering signal output unit configured to generate a filtering signal for filtering the data strobe signal in response to the plurality of filtering control signals and a plurality of burst length (BL) control signals.

Abstract: A data strobe signal generation circuit includes: an enable signal generation unit configured to decode a test signal and generate an enable signal; an internal clock generation unit configured to generate a rising clock signal and a falling clock signal in response to the test signal; and a data strobe signal output unit configured to selectively buffer first and second powers in response to the rising clock signal and the falling clock signal, and output a data strobe signal.

Abstract: An address latch circuit of a semiconductor memory apparatus includes a control signal generating section configured to generate a control signal in response to an external command signal and a RAS idle signal, a clock control section configured to output a clock signal as a control clock signal when the control signal is enabled and to fix the control clock signal to a predetermined level when the control signal is disabled, and an address latch section configured to latch an address signal in response to the control clock signal.

Abstract: A strobe signal is received in a device and execution of an operation in the device is delayed when the strobe signal includes a preamble. Additional apparatus, systems, and methods are disclosed.

Abstract: A semiconductor memory device includes: a first strobe signal generation unit configured to generate a first rising strobe signal in response to a rising DLL clock signal; a second strobe signal generation unit configured to generate a second rising strobe signal in response to a falling DLL clock signal, the second rising strobe signal having an opposite phase to the first rising strobe signal and being activated at the same timing as the first rising strobe signal; a third strobe signal generation unit configured to generate a first falling strobe signal in response to the falling DLL clock signal; and a fourth strobe signal generation unit configured to generate a second falling strobe signal in response to the rising DLL clock signal, the second falling strobe signal having an opposite phase to the first falling strobe signal and being activated at the same timing as the first falling strobe signal.

Abstract: Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs from the first set. Either the first set of periodic signals or the second set of periodic signals may be selected and used to generate a set of data capture signals. The selection of either the first set or the second set may be made on the basis of the number of serial data digits in a previously captured burst of data. The data capture signals may then be used to capture a burst of serial data digits.

Abstract: A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.

Abstract: A memory circuit includes a delay module receiving a strobe signal and producing a delayed strobe signal therefrom. The memory circuit also includes a calibration module that initiates recalibration of the delay module when the calibration module discerns that the delayed strobe signal is within a predetermined proximity of an edge of a reference signal. The memory circuit can be included in a memory interface. Furthermore, in some embodiments, a strobe signal can be used as the reference signal.

Abstract: A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according to a local clock signal 71/73. Based on the results of the sampling, the data strobe and local clock signal are synchronized. In this manner, the data is synchronized to the local clock signal so that sampling of data at the data destination can be performed according to the local clock signal rather than the data strobe.

Abstract: A method for compensating for variations in timing of data sent to a processor on data bit lines relative to a strobe clock sent to the processor on a strobe clock line that can be used in a dual data rate (DDR) memory identifies discrete minimum and maximum time offset values for test data in selected data bit patterns for the data bit lines. The discrete minimum time offset value is the minimum timing adjustment required to allow the processor to receive the data in a steady-state condition during a data valid window of the strobe clock and the discrete maximum time offset value is a maximum timing adjustment required to allow the processor to receive the data in a steady-state condition during a data valid window of the strobe clock. The discrete minimum and maximum time offset values identify a valid range when the data bit lines supply data in a steady-state condition for latching into the processor by the strobe clock.

Abstract: A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.

Abstract: Embodiments of the invention are described for driving data onto a data bus. The embodiments include a data driver circuit having a data capture circuit coupled to the data bus. The data capture circuit receives a data signal relative to a write strobe signal and captures a first data digit of the data signal responsive to a first edge of the write strobe signal and at least a second data digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each of the data digits of the data signal in substantially the same manner as the data capture circuit, and also generates a latch control signal indicative of when each data bits is latched. The latch control signal is provided to a write control circuit coupled to the feedback capture circuit and the data capture circuit.

Abstract: Various embodiments of a nonvolatile memory apparatus configured to operate in a first operation mode and a second operation mode are disclosed. In one exemplary embodiment, the apparatus may include: a controller configured to enable complementary signal input/output buffers in response to a command for entry into the first operation mode and disable the complementary signal input/output buffers in response to a command for transition to the second operation mode while operating under the first operation mode.

Abstract: A semiconductor memory device includes a reset signal generating unit configured to generate a reset control signal by delaying a column command signal by an amount of time varying proportional to an operational frequency. A pulse width determination unit is configured to determine a pulse width of a column selection signal in response to the column command signal and the reset control signal. An address decoding unit is configured to generate the column selection signal corresponding to a corresponding column address in response to an output signal of the pulse width determination unit.

Abstract: To include a plurality of pad groups each including a first data I/O pad, a first power supply pad, a second data I/O pad, and a second power supply pad arranged in order in an X direction. The first data I/O pad is connected to a first data I/O buffer, and the second data I/O pad is connected to a second data I/O buffer. The first power supply pad supplies a first power supply potential to the first and second data I/O buffers, and the second power supply pad supplies a second power supply potential to the first and second data I/O buffers. The first data I/O pad included in each of the pad groups is adjacent to the second power supply pad included in other pad group or any one of a plurality of power supply pads not included in any one of the pad groups.

Abstract: A semiconductor memory device includes: a data multiplexing unit configured to output one of a data training pattern and data transferred through a first global input/output line in response to a training control signal; and a latch unit configured to latch an output of the data multiplexing unit to apply and maintain the latched output to a second global input/output line.

Abstract: In an embodiment, a memory device comprises memory, a first data link, a first input, a second input, a second data link, a first output and a second output. The first data link is configured to input one or more packets into the memory device. The first input is configured to input command strobe signals into the memory device that delineate command packets that are input into the memory device via the first data link. The second input is configured to input data strobe signals into the memory device that delineate data packets that are input into the memory device via the first data link. The first and second outputs are configured to output the command strobe signal and data strobe signal, respectively. The second data link is configured to output packets from the memory device.

Abstract: A controller includes a set of first terminals to be coupled to a device that is under control of the controller, and a control circuit configured to generate and output onto the set of first terminals synchronous mode information including a selected one of selection and non-selection modes, the selection mode causing the device to return to the controller a first data signal while activating a first data strobe signal that is synchronous in phase with a system clock, the non-selection mode causing the device to return to the controller a second data signal while activating a second data strobe signal that is asynchronous in phase with the system clock signal, and edge specifying information including a selected one of first and second states, the first state causing the device to activate the first data strobe signal at a first timing.

Abstract: An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control signal having enable timing according to a DLL on/off mode, and an output enable signal output unit configured to receive the output control signal and to output an output enable signal in response to a read command and a DLL clock signal.

Abstract: One aspect of the present invention is a memory controller which controls a memory device including two or more memory access units and includes a data control circuit and an adjusting circuit that performs at least one of a first processing and a second processing. In the first processing, a timing of the write strobe signal generated by the data control circuit in a write operation is adjusted for each memory access unit and a write strobe adjusting signal specifying a timing for each memory access unit to load write data is generated, and in the second processing, a timing of the read strobe signal generated by the memory device in a read operation is adjusted for each memory access unit and a read strobe adjusting signal specifying a timing for the data control unit to read data read out from each memory access unit is generated.

Abstract: A semiconductor memory device includes: a strobe signal reception unit configured to receive a strobe signal and generate a tracking clock signal; a clock reception unit configured to receive a clock signal and generate an internal clock signal; a plurality of data reception units configured to receive parallel data in accordance with the internal clock signal and generate internal data; and a phase control unit configured to control the phase of the internal clock signal to track the tracking clock signal and to compensate for a variation in the phase of the internal clock signal while the data is received.

Abstract: A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.

Abstract: Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The first signal buffer is configured to be operative responsive to a first data strobe signal and further configured to be operative responsive to a non-data signal. The second signal buffer is configured to be operative responsive to a second data strobe signal. An example first data strobe signal is a read data strobe signal provided by the memory. In another example, the first data strobe signal is a write data strobe signal received by the memory. Examples of non-data signals include a data mask signal, data valid signal, error correction signal, as well as other signals.

Abstract: A semiconductor memory device having a bank including a redundancy cell block and a plurality of normal cell blocks includes a plurality of normal data inputting/outputting units configured to respectively input/output data from the normal cell blocks in response to a first input/output strobe signal, a redundancy data inputting/outputting unit configured to input/output data from the redundancy cell block in response to the first input/output strobe signal, and a connection selecting unit configured to selectively connect the normal data inputting/outputting units and the redundancy data inputting/outputting unit to a plurality of local data lines in response to a address.

Abstract: An apparatus for generating an output data strobe signal include a timing control unit configured to detect a specific data pattern and to generate a plurality of timing control signals corresponding to the detected data pattern in response to a clock signal; and a strobe signal generating unit configured to generate at least one strobe signal in response to the clock signal, and to adjust transition timings of the strobe signal in response to the timing control signals.

Abstract: A delay locked loop circuit includes a delay locked loop receiving an external clock, a frequency detector delaying an input frequency signal to generate a plurality of strobe signals and outputting a check signal indicating that the frequency of the input frequency signal is equal to or lower than a reference frequency when all of the strobe signals are positioned within a first-status section of one cycle of the input frequency signal, a delay lock reset unit generating a reset signal to reset the frequency detector and an activation signal to enable the delay locked loop to perform a delay lock process, and a direct phase detector controlling a coarse locking window on the basis of the check signal and generating a pair of phase detection signals indicating logic levels of the external clock. According to this configuration, since the coarse locking window is controlled as per a frequency band, it is possible to prevent a failure of a coarse locking and to achieve an improved circuit performance.

Abstract: An integrated circuit device includes a delay circuit, sampling circuit and delay control circuit that cooperate to carry out adaptive timing calibration. The delay circuit generates a timing signal by delaying an aperiodic input signal for a first interval. The sampling circuit samples a data signal in response to the timing signal to generate a sequence of data samples, and also samples the data signal in response to a phase-shifted version of the timing signal to generate a sequence of edge samples. The delay control circuit adjusts the first interval based, at least in part, on a phase error indicated by the sequence of data samples and the sequence of edge samples.

Abstract: A self-test module for use in an electronic device includes a test controller and a memory. The memory is configured to receive test vectors from the test controller. A comparator is configured to receive the test data from the memory via an output data path. A strobing buffer is located in the output data path between an output from the memory and an input to the comparator. The strobing buffer is configured to selectively enable the test vectors to propagate from the memory output to the comparator input.

Abstract: A plurality of control signals are asserted within an asynchronous integrated circuit memory device in response to each transition of a memory access initiation signal to effect pipelined memory access operations.

Abstract: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

Abstract: An apparatus for measuring data setup/hold time is capable of effectively measuring a setup/hold time of data, and includes a data generating unit for delaying an external clock signal according to counting signals and generating an internal clock signal and data signals from the delayed external clock signal in response to test signals, a data latch unit for latching buffered data signals in synchronization with the internal clock signal, wherein the buffered data signals are produced by buffering the data signals, a flag signal generating unit for generating flag signals from the latched data signals latched in the data latch unit in response to the test signals, and a counter for producing the counting signals in response to the flag signals.

Abstract: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.

Abstract: An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read commands are issued once per burst access eliminating toggling Read control line at cycle frequency. Control line transition terminates access and initializes another burst access.

Abstract: A memory interface includes a first delaying circuit configured to delay write data to be supplied to an input buffer; a second delaying circuit configured to delay read data read out from an output buffer; a data write circuit configured to supply said write data to a memory through said first delaying circuit; and a data read circuit configured to read said write data written in said memory, as said read data through said second delaying circuit. A control circuit is configured to detect positions of a start edge and end edge of an eye opening which is formed based on fluctuation of said write data or said read data, to specify an intermediate position of the start edge and the end edge, and to determine a phase of a data strobe signal based on a difference between the intermediate position and one of the start edge and the end edge.

Abstract: A data input circuit includes a valid strobe signal generation circuit and a data strobe signal counter. The valid strobe signal generation circuit is configured to remove a pulse of an internal strobe signal generated and generate a valid strobe signal. The pulse may have been generated during a preamble period. The data strobe signal counter is configured to count the valid strobe signal according to burst length information and generate a write latch signal for aligning data at a time of a write operation.

Abstract: A data strobe signal generating device includes a preamble controller configured to generate a preamble signal enabled in synchronization with a first dock signal and disabled in synchronization with a second clock signal after an output enable signal is enabled, and a data strobe signal output unit configured to generate a data strobe signal in response to the preamble signal.

Abstract: A memory system with delay locked loop (DLL) bypass control including a method for accessing memory that includes receiving a memory read command at a memory device. The memory device is configured to operate in a DLL off-mode to bypass a DLL clock as input to generating a read clock. A DLL power-on command is received at the memory device and in response to receiving the DLL power-on command a DLL initialization process is performed at the memory device. The memory read command is serviced at the memory device operating in the DLL off-mode, the servicing overlapping in time with performing the DLL initialization process. The memory device is configured to operate in a DLL on-mode to utilize the DLL clock as input to generating the read clock in response to a specified period of time elapsing. The specified period of time is relative to receiving the DLL power-on command.

Abstract: An invention is provided for gate training in memory interfaces. The invention includes adding a coarse delay to a gate assert time, where the coarse delay is a predefined period of time and the gate assert time is a time when a data strobe gate signal is asserted. Next, the a data strobe signal is repeatedly sampled at the gate assert time until a rising edge of the data strobe signal is found, wherein a fine delay is added to the gate assert time between sampling of the data strobe signal. The fine delay is a period of time shorter than the coarse delay. Once the rising edge is found, the coarse delay is removed from the gate assert time, thus setting the gate assert time centrally within the preamble of the data strobe signal.

Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

Abstract: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.

Abstract: A conventional semiconductor memory device may be in need of a special refresh sequence if it is desired to reduce the current consumption in connection with a refresh operation. With this in view, there is disclosed a semiconductor memory device 1 that has a recording area 30 formed by a plurality of memory banks 31 to 3n. The refreshing operation for this semiconductor memory device 1 may be performed on the memory bank basis. The semiconductor memory device 1 includes refresh control circuits 21 to 2n and holding circuits 11 to 1n in association individually with the memory banks 31 to 3n. The holding circuits 11 to 1n are set when data has been written in associated ones of the memory banks 31 to 3n following resetting of the semiconductor memory device. The refresh control circuits 21 to 2n set the associated memory banks 31 to 3n to a refresh enabling state in case the associated holding circuits 11 to 1n are in a set state (FIG. 1).

Abstract: A semiconductor IC device which includes a common column signal generating block and a column strobe signal generating block. The common signal generating block can provide precolumn strobe signals by using external command signals and a first group of bank addresses among a plurality of bank addresses. The column strobe signal generating block can provide a plurality of column strobe signals to selectively activate a plurality of banks by using the precolumn strobe signals and a second group of bank addresses among the plurality of bank addresses that are not used when the precolumn strobe signals are generated.

Abstract: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.

Abstract: A signal adjusting system includes: a signal generating apparatus for transmitting a first driving signal and a second driving signal, a plurality of signal transmitting paths coupled to the signal generating apparatus, and a controlling apparatus coupled to the plurality of signal transmitting paths for receiving a first transmitted signal corresponding to the first driving signal and a second transmitted signal corresponding to the second driving signal, and detecting a phase difference between the first transmitted signal and the second transmitted signal to generate a detected result for the signal generating apparatus, wherein the signal generating apparatus adjusts a first driving ability of the first driving signal and a second driving ability of the second driving signal according to the detected result.

Abstract: A memory controller may implement variable delay elements, on a per-bit basis, in both the read and write paths. The memory controller may include multiple adjustable delay circuits associated with data lines and a strobe line, each of the adjustable delay circuits inserting an adjustable amount of delay into a signal destined to or received from one of the data lines or the strobe line. The memory controller may additionally include control logic to determine the delay amount for each of the adjustable delay circuits, the delay amount being determined to reduce static skew between each of the data lines and the strobe line.

Abstract: A method of processing a strobe signal can include oversampling a strobe signal received from a source synchronous device and determining an amount of time between sending a read request to the source synchronous device and detecting a first pulse of the strobe signal according to the oversampling. The method also can include squelching the strobe signal for the amount of time responsive to at least one subsequent read request.

Abstract: A semiconductor memory device includes a write control signal generating circuit and a write enable signal generating unit. The write control signal generating circuit is configured to generate a write control signal activated during a time period from an input time point of a read command to an end time point of a data output time period. The write enable signal generating unit is configured to output a write command as a write enable signal in response to the write control signal.

Abstract: An apparatus includes an interface circuit coupled to an electronic device. The interface circuit provides source synchronous communication with the electronic device using a strobe signal. The interface circuit is configured to gate the strobe signal in order to successfully communicate with the electronic device.

Abstract: An operation guarantee system includes a decoder circuit, a comparison circuit, a CPU circuit, a frequency adjustment circuit and a DQ adjustment circuit. The comparison circuit compares a test data signal input from the decoder circuit with an expected value data signal input from the exterior, and detects the presence or absence of an output error in the decoder circuit. The CPU circuit controls the frequency adjustment circuit and the DQ adjustment circuit to vary a frequency of a clock signal input to an external memory and a delay amount of the data signal. In addition, the CPU circuit acquires a result of detection of the comparison circuit under various conditions. Then, the CPU circuit determines an appropriate frequency of the clock signal input to the external memory based on a relationship between the various conditions and the presence or absence of the output error.