Abstract: The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.

Abstract: A semiconductor IC device includes a core strobe signal generator configured to latch a read command signal according to an internal clock signal to generate a core strobe signal, a core block configured to output data stored in a memory cell in response to the core strobe signal, a data output unit configured to latch data output from the core block according to a plurality of control signals and output the latched data in a predetermined order, and a controller configured to generate the plurality of control signals by using both the core strobe signal and the internal clock signal.

Abstract: A semiconductor apparatus having a plurality of chips stacked therein is disclosed. At least two of the plurality of chips are configured to receive a column command and generate a column control signal based on the column command. Generation timing of the column control signal generated based on a column command in one of the at least two of the plurality of chips substantially coincide with the generation timing in the other of the at least two of the plurality of chips.

Abstract: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

Abstract: A data strobe signal noise prevention apparatus and semiconductor integrated circuit includes a transition protection unit configured to protect a transition of a data strobe signal in response to a control signal and a controller configured to determine when a burst operation completes and to generate the control signal.

Abstract: A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data generation circuits to each transmit a data signal to the memory on a data line, the write data generation circuits being controlled by write enable signals. A write strobe generation circuit generates the strobe signal and the write enable signals, the strobe signal including a preamble window to signal the beginning of the data burst, a data transfer window, and a postamble window to signal the end of the data burst, the write strobe generation circuit generating the write enable signals a half memory cycle early and terminating the write enable signals a half memory cycle late with respect to the data signals generated by the write data generation circuits.

Abstract: Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A logic circuit, which may be referred to as a one-half period circuit, shortens enable pulses at their front end by one-half a period. The shortened enable signal is passed to a storage element such as a register. Active pulses of the shortened enable signal clear the register, which provides a control signal closing a switch, such as an AND gate. The switch passes the DQS signal to the input register when closed and isolates the input register from the DQS signal when open. The shortened enable signal prevents the switch from opening early and passing spurious transitions on the DQS signal, for example during back-to-back non-consecutive read cycles.

Abstract: A memory buffer selecting between a parallel test mode and a mode register control mode, and a memory module and memory system having the memory buffer are disclosed. The memory buffer includes a control circuit and a mode selecting circuit. The control circuit generates a mode control signal based on a first chip selecting signal, a second chip selecting signal, a row address signal, a column address signal, and a write enable signal. The mode selecting circuit selects one of a parallel test mode and a mode register control mode in response to the mode control signal.

Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal.

Abstract: A method for generating a read enable signal which is for controlling reading of a pair of data strobe signals and a data signal in a memory system is provided. The method comprises: detecting whether the pair of data strobe signals are both high or low; and generating the read enable signal if the pair of data strobe signals are detected being both high or low. Because the read enable signal is generated using the pair of strobe signals, DLL can be turned off, thus the power consumption of the memory system can be reduced. In addition, the read enable signal is self-aligned with a certain point of the pair of strobe signals, this may enhance precision of the transmission of the pair of strobe signals and the data signal.

Abstract: A semiconductor device in the present invention includes a DLL circuit which determines a phase shift amount, an arithmetic circuit which shifts the phase shift amount by a predetermined phase at test mode time, registers which set the phase shift amount, and a transmission circuit which shifts a phase to the set phase to transmit or receive a signal. The transmission circuit has a first phase shifter which shifts a first signal to the set phase, a first bidirectional buffer which loops back the first signal at the test mode time, a second phase shifter which phase-shifts the signal outputted from the first bidirectional buffer, a third phase shifter which phase-shifts a third signal, a second bidirectional buffer which loops back the third signal at the test mode time, a fourth phase shifter which phase-shifts the signal outputted from the second bidirectional buffer, and a FIFO which takes out an output signal of the second phase shifter or the fourth phase shifter.

Abstract: Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.

Abstract: The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.

Abstract: A circuit for generating a data I/O control signal used in a semiconductor memory apparatus comprises a delay block for generating a delay signal having a relatively short delay value and a delay signal having a relatively long delay values, and a selection block for selecting any one of the delay signals according to an operational mode. The selection block selects an output signal of the first delay unit in a high-speed operation mode and selects an output signal of the second delay unit in a low-speed operation mode.

Abstract: A memory controller, a PCB and a computer system employing the memory controller, and a memory adjusting method using the memory controller. The memory controller interfaces data reading from and writing to a memory and includes: a characteristic estimating part estimating a characteristic of a memory output signal outputted from the memory for the data reading and writing; and a characteristic adjusting part controlling the memory so that the characteristic of the memory output signal is within a predetermined reference range if the characteristic of the memory output signal estimated by the characteristic estimating part is beyond the predetermined reference range.

Abstract: A semiconductor device includes: first and second input/output terminals; a first input/output line connected to the first input/output terminal; a second input/output line connected to the second input/output terminal; and a first by-path route that connects the first input/output line and the second input/output line. When in normal operation mode, the first by-path route is set in a non-conductive state. When in a test mode, the first by-path route is set into a conductive state so that a first data inputted to the first input/output terminal is outputted as a first data to the second input/output line, in correspondence with a transition of a clock signal in the first direction, and so that a second data inputted to said first input/output terminal is outputted as a second input data for said first input/output line, in correspondence with a transition of said clock signal in the second direction.

Abstract: A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal.

Abstract: The memory system, memory device, memory controller and method may have a reduced power consumption. The memory system, memory device, memory controller and method may transition a data strobe signal to a valid logic level during a standby state. The valid logic level may be less than a logic level associated with a higher impedance level, such as when a bus may be turned off or connected to a ground voltage. A delay locked circuit need not be used in the memory device.

Abstract: An apparatus for generating an output data strobe signal include a timing control unit configured to detect a specific data pattern and to generate a plurality of timing control signals corresponding to the detected data pattern in response to a clock signal; and a strobe signal generating unit configured to generate at least one strobe signal in response to the clock signal, and to adjust transition timings of the strobe signal in response to the timing control signals.

Abstract: The data access apparatus comprises a phase locked loop (PLL) and a data receiving circuit. The PLL provides a plurality of internal clocks and selecting a strobe clock from the plurality of internal clocks according to a phase selection signal. The data receiving circuit comprises a latching module, for latching of the data signal according to trigger of the strobe clock and a calibrating circuit, for generating the phase selection signal for matching the data with a predetermined data at the plurality of internal clocks in a training mode and finally determining the phase selection signal corresponding to a preferred clock used in a normal mode.

Abstract: A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate an internal data strobe clock signal, a timing discriminating block configured to discriminate toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal to generate a timing discrimination signal, and an enable controlling block configured to generate the buffer enable signal in response to the timing discrimination signal.

Abstract: A data input circuit includes a first data input unit, a second data input unit, and a clock unit. The first data input unit is configured to receive external data at rising edges of a data strobe signal and output the external data as first internal data in response to an internal clock. The second data input unit is configured to receive the external data at falling edges of the data strobe signal and output the external data as second internal data in response to the internal clock. The clock unit is configured to generate the internal clock using an external clock signal.

Abstract: Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) and a second device (such as a memory component) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops, for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system.

Abstract: In a DDR memory controller, a clock control circuit is configured to output a clock signal selected from among a plurality of clock signals with different frequencies based on a frequency selection signal, to a DDR memory as an operation clock signal. A master DLL circuit is configured to receive one of the plurality of clock signals which has a maximum frequency as a reference clock signal to determine a delay code. A slave delay circuit is configured to delay a strobe signal from the DDR memory based on the determined delay code to generate an internal strobe signal for a data signal from the DDR memory.

Abstract: A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a source line, and the cells are configured to read and write data according to a cell driving voltage. Each switching element of a plurality of switching elements are connected in parallel with a single cell of the plurality of cells, and the plurality of switching elements are controlled selectively by a plurality of bit lines.

Abstract: Methods and apparatus for aligning a clock signal and a set of strobe signals are disclosed. In one embodiment, a memory controller includes a clock generator configured to generate the clock signal, and a respective strobe signal generator configured to generate each strobe signal. The memory controller further includes a phase recovery engine configured to receive an error signal from a corresponding memory device, wherein the error signal conveys an error indication indicative of an alignment of the strobe signal relative to the clock signal for each of a plurality of cycles of the strobe signal. The phase recovery engine includes an accumulator configured to maintain an accumulation value that depends upon the error indications for the plurality of cycles of the strobe signal. The strobe signal generator is configured to control a delay associated with generation of the strobe signal depending upon the accumulation value.

Abstract: A memory module can include a data buffer having a data bus interface and a dynamic random access memory (DRAM) coupled to the data buffer. The memory module may also include a switch connected in parallel with the data buffer, wherein the switch can selectively bypass the data buffer. In one example, the memory module also includes a registered buffer having an address bus interface, where the switch may selectively bypass the data buffer based on a program signal obtained from an address bus via the address bus interface.

Abstract: A memory control circuit includes a data sample circuit, a first delay control circuit, a second delay control circuit and a data circuit. The data sample circuit is used for generating a first data strobe signal and a second data strobe signal. The first delay control circuit is coupled to the data sample circuit, for receiving the first data strobe signal and delaying the first data strobe signal to generate a first delayed data strobe signal. The second delay control circuit is coupled to the data sample circuit, for receiving the second data strobe signal and delaying the second data strobe signal to generate a second delayed data strobe signal. The data circuit is coupled to the first delay control circuit and the second delay control circuit, for transferring data signals according to the first delayed data strobe signal and the second delayed data strobe signal.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a x4 mode, a x8 mode, and a x16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.

Abstract: A dual data rate (DDR) memory controller and method are provided. The method includes: receiving a first data strobe at a first terminal from a first memory having a first rank; receiving a first data signal at a second terminal from the first memory having the first rank; calibrating the first data signal with the first data strobe to produce a first calibration value; receiving a second data strobe at the first terminal from a second memory having a second rank; receiving a second data signal at the second terminal from the second memory having the second rank; calibrating the second data signal with the second data strobe to produce a second calibration value; determining a final calibration value using the first and second calibration values; and using the final calibration value to time the first data signal and the second data signal during a read operation of the memories.

Abstract: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated

Abstract: A memory controller, such as a memory controller for reading data received from a DDR SDRAM memory, may detect the beginning and end of a read cycle. The memory controller may include a preamble detection circuit to receive a strobe signal and output a first control signal indicating detection of a preamble window in the strobe signal that indicates a beginning of the read cycle, where the first control signal is delayed based on a selectable delay period applied to the first control signal. The memory controller may further include a first gate to, based on the first control signal, either output the strobe signal for reading of the data lines or block the strobe signal, and the control logic to set an amount of the selectable delay period for the preamble detection circuit.

Abstract: A semiconductor memory device includes: a first strobe signal generation unit configured to generate a first rising strobe signal in response to a rising DLL clock signal; a second strobe signal generation unit configured to generate a second rising strobe signal in response to a falling DLL clock signal, the second rising strobe signal having an opposite phase to the first rising strobe signal and being activated at the same timing as the first rising strobe signal; a third strobe signal generation unit configured to generate a first falling strobe signal in response to the falling DLL clock signal; and a fourth strobe signal generation unit configured to generate a second falling strobe signal in response to the rising DLL clock signal, the second falling strobe signal having an opposite phase to the first falling strobe signal and being activated at the same timing as the first falling strobe signal.

Abstract: A circuit for generating a read end signal includes a clock transferring unit which receives a clock signal, a write/read status signal and an all bank precharge signal and outputs a delayed clock signal, a read signal detecting unit which receives a read pulse signal and the delayed clock signal and generates a read detection signal having a pulse width corresponding to a certain clock, and a read end signal generating unit which receives a first signal, the delayed clock signal and the read detection signal and generates a read end signal.

Abstract: An invention is provided for determining write leveling delay for a plurality of memory devices having command signals lines connected in series to each memory device is disclosed. The invention includes determining a device delay value for each memory device. Each device delay value indicates a period of time to delay a DQS signal when accessing a related memory device. Once these delay values are determined, the delay values are examined sequentially and a prior device delay value is set to a lower value, for example zero, when a subsequent device delay value of a memory device connected subsequently along the command signal lines is greater than the prior device delay value.

Abstract: A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is transmitted to the memory device to instruct the memory device to drive data onto the data/IO bus. The read enable signal is fed back to the controller circuit that then uses the fed back signal to read the data from the data/IO bus.

Abstract: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write strobe to compensate for timing drift at the memory device. The memory controller uses the read strobe as a measure of the drift.

Abstract: Provided is a receiving method and a receiving apparatus comprising a multi-strobe generating section that generates a multi-strobe including a plurality of strobes having different phases with respect to a reception signal; an acquiring section that acquires the reception signal using each of the strobes; a detecting section that detects a change position at which a value of the reception signal changes, based on the acquisition result of the acquiring section; and a selecting section that selects, as a reception data value, the value of the reception signal acquired using a strobe at a position shifted by a predetermined phase from the change position. The receiving apparatus may further comprise a reference clock generating section that generates a reference clock having a preset period, and the multi-strobe generating section generates the multi-strobe for each pulse of the reference clock.

Abstract: A semiconductor memory device includes a DLL for detecting a phase difference between an external clock signal and a feedback clock signal to generate a delay control signal corresponding to the phase difference, and delaying the external clock signal by a delay amount corresponding to the delay control signal to generate a DLL clock signal; a clock counter reset signal generator for synchronizing an output enable reset signal with the external clock signal, delaying the synchronized signal by a delay amount corresponding to the delay control signal, and latching the delayed signal in response to the DLL clock signal to output a clock counter reset signal; and an output enable signal generator, reset in response to the clock counter reset signal, for counting the external clock signal and the DLL clock signal to generate an output enable signal corresponding to a read command and a CAS latency.

Abstract: A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device and transfer output data from the memory device. The write strobe transceivers transfer timing information of the input data. The read strobe transceivers transfer timing information of the output data. The memory device also has an auxiliary circuit for generating auxiliary information. The auxiliary information includes information different from the timing information of the input data and the output data. The auxiliary circuit uses the write and read transceivers to transfer the auxiliary information to and from the memory device.

Abstract: Receiver for receiving a data stream via a data bus, which receiver samples the bits of the data stream in an over-sampling process, in which n bit strobe offsets are used and n data sets with i bits are sampled,—applies a decision criterion for identifying those data sets with correct bit values. This decision uses checksum CRC,—selects one of the identified data sets with correct bit values and—uses the bit strobe offset, which was used for receiving the selected data streams, for receiving the data stream. In this way the multiphase clock with optimal phase shifts is selected.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: A semiconductor memory device includes: a modulation controller for generating a modulation control signal for controlling a frequency modulation operation; a delay locked loop (DLL) circuit for performing a delay locking operation to generate first and second DLL clocks and outputting a frequency-modulated DLL clock in response to the modulation control signal; and a data strobe signal generator for outputting the frequency-modulated DLL clock as a data strobe signal.

Abstract: A semiconductor device includes a plurality of first output terminals 1-13 and a plurality of first output circuits 203,204 provided corresponding to each of the plurality of first output terminals and coupled to a corresponding first output terminal. The semiconductor device further includes a second output circuit 201 coupled to a second output terminal DQS. The second output circuit automatically adjusts a slew rate based on the state transitions of the plurality of first output circuits. The second output circuit adjusts the slew rate from a first state to a second state based on a transition from first data outputted from the first output circuit to second data following said first data. The second output circuit outputs data in synchronization with the second data with a slew rate in said second state.

Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.

Abstract: A transceiver (222) includes a receive circuit (320), a transmit circuit (340), a shared delay locked loop (DLL) (360), and a controller (210). The receive circuit (320) has a first input coupled to an external data terminal, a second input coupled to an external data strobe terminal, and an output coupled to an internal data terminal. The transmit circuit (340) has a first input coupled to the internal data terminal, a second input for receiving an internal clock signal, a first output coupled to the external data terminal, and a second output coupled to the external data strobe terminal. The controller (210) enables the shared DLL (360) for use by the receive circuit (320) during a receive cycle, and enables the shared DLL (360) for use by the transmit circuit (340) during a transmit cycle.

Abstract: A semiconductor memory apparatus includes: a first bit line of to a first memory bank; a first middle input/output line configured to be electrically connected to the first bit line; a second bit line of a second memory bank; a second middle input/output line configured to be electrically connected to the second bit line; and a shared local input/output line configured to be electrically connected to the first and second middle input/output lines. A bank selection signal controls both the electrical connection between the shared local input/output line and the first middle input/output line and the electrical connection between the shared local input/output line and the second middle input/output line.

Abstract: A semiconductor memory apparatus includes an internal tuning unit configured to tune a generation timing of a data input strobe signal according to a phase difference between an external clock signal and a data strobe clock signal, and a data input sense amplifier configured to transmit data bits to a global line in response to the data input strobe signal.

Abstract: A method is provided for writing data to a memory array operating in synchronization with a clock signal having a transition edge. A data strobe signal having a transition edge corresponding to the transition edge of the clock signal is provided. The transition edge of the clock signal is used to relay the data corresponding to the transition edge of the data strobe signal if the transition edge of the data strobe signal is coming in earlier than the transition edge of the clock signal, wherein the clock signal has a rising edge and a falling edge, the data strobe signal has a rising edge and a falling edge respectively corresponding to the rising and the falling edges of the clock signal, and the transition edge of the clock signal is one of the rising and the falling edges of the clock signal.

Abstract: An internal source voltage generation circuit includes main source voltage driving means configured to drive an internal source voltage terminal to a predetermined voltage level; and additional source voltage driving means configured to additionally drive the internal source voltage terminal in response to a data strobe signal.