Abstract: A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.

Abstract: The present disclosure generally relates to searching an overlap table for data requested to be read in a plurality of read commands received. Rather than searching the table for data corresponding to each command individually, the searching occurs for the plurality of commands in parallel. Furthermore, the overlap table can comprise multiple data entries for each line. The number of read commands can be accumulated prior to searching, with the accumulating being a function of a queue depth permitted by the host device. Parallel searching of the overlap table reduces the average search time.

Abstract: A method of operating an integrated circuit includes writing data to each memory cell in a first memory cell array, powering off the integrated circuit, powering on the integrated circuit, reading data from each memory cell in the first memory cell array in response to powering on the integrated circuit, and determining whether to allow an authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array. The integrated circuit includes a first memory cell array.

Abstract: According to one embodiment, the memory system includes a nonvolatile semiconductor memory, a data buffer, a volatile memory for storing a management table uniquely associates the user data with an address of the physical storage region of nonvolatile semiconductor memory, a controller that carries out a force quit process for writing the user data stored in a data buffer, the management table stored in volatile memory into the nonvolatile semiconductor memory, and a storage battery. The controller starts the force quit process prior to the power supply of the internal power supply regulator is switched from an external power supply to the storage battery.

Abstract: A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells and a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank. The memory also comprises a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank, and wherein a write verification operation associated with a data word of the second plurality of data words is performed a predetermined period of time after the data word is written into the memory.

Abstract: A power/data transmission extender system includes a power/data transmission extender device that is coupled to a powering device and a powered device. The power/data transmission extender device receives power and data from the powering device via a first power/data cable that is connected to the power/data transmission extender device, and stores at least a portion of the power that was received from the powering device via the first power/data cable in a power storage subsystem that is included in the power/data transmission extender device. The power/data transmission extender device may then transmit the data that was received from the powering device, at least a portion of the power that was received from the powering device, and at least a portion of power that is stored in the power storage subsystem, to the powered device via a second power/data cable that is connected to the power/data transmission extender device.

Abstract: Systems, apparatuses, and methods related to hierarchical memory are described herein. A hierarchical memory apparatus can be part of a memory system that can leverage persistent memory to store data that is generally stored in a non-persistent memory. An example apparatus includes logic circuitry configured to receive a command indicating that an access to a base address register coupled to the logic circuitry has occurred. The command can be indicative of a data access involving a persistent memory device and/or a non-persistent memory device. The logic circuitry can determine that the access command corresponds to an operation to divert data from the non-persistent memory device to the persistent memory device, generate an interrupt signal, and cause the interrupt signal to be asserted on a host coupleable to the logic circuitry as part of the operation to divert data from the non-persistent memory device to the persistent memory device.

Abstract: A flash memory device according to an embodiment of the inventive concept includes a selection transistor for selecting a cell string; and a plurality of memory cells connected in series to the selection transistor, and the selection transistor is programmed such that a threshold voltage of the selection transistor is higher than a non-selection read voltage Vread, for protecting data stored in at least one of the plurality of memory cells. The flash memory according to an embodiment of the inventive concept adjusts the threshold value of the selection transistor or a dummy memory, thus protecting data permanently or temporarily within a short time and recovering original data easily without data loss if necessary.

Abstract: A method of masking data includes disabling, by one or more processors of a computer system, operation of a data structure that includes at least one data index. The method includes masking, by the one or more processors of the computer system, the data structure in a table with an isomorphic function, and enabling, by the one or more processors of the computer system, operation of the data structure.

Abstract: A memory system is configured to convert multiple programmable memory or a portion thereof to one-time programmable (OTP) memory. The system is configured to repetitively perform memory operations (such as program and erase procedures) on a portion of memory in order to induce accelerated degradation (aging) of select memory cells, thereby permanently changing the select cells, such that a pattern of the cells with degraded performance indicate a data value that has been permanently encoded into the memory.

Abstract: A semiconductor device may include a delay locked loop (DLL) control circuit coupled to an update trigger generator and a DLL update circuit. The DLL control circuit may receive an update trigger signal and an internal refresh signal and configured to activate the DLL update circuit responsive to an update trigger in the update trigger signal and deactivate the DLL update circuit responsive to an active internal refresh signal. The DLL update circuit may perform DLL update to one or more memory cell arrays when activated and not perform DLL update to the memory cell arrays when deactivated. The DLL control circuit may reactivate the DLL update circuit once the internal refresh signal becomes inactive. In other scenarios, once the DLL update circuit is deactivated, the DLL update circuit stays deactivated until the next update trigger in the update trigger signal.

Abstract: The present disclosure relates to a computer-implemented method for controlling operation of multiple computational engines of a physical computing device. The computer-implemented method includes providing a multiplexer module in the device, the multiplexer module including a first and second memory region. The multiplexer module may receive from a first driver at the multiplexer module a data processing request to be processed by a first set of one or more computational engines of the computational engines. Subsequent to receiving the data processing request, the multiplexer module may assign a request sub-region of the first region and a response sub-region of the second region to the first driver. Data indicative of the request sub-region and the response sub-region may be submitted to the first driver. Results of processing the request may be received at the response sub-region.

Abstract: Provided herein may be an electronic device, a memory system having the electronic device, and an operating method thereof. The electronic device may include a voltage manager configured to determine whether a voltage abnormality occurs by monitoring a voltage to be supplied to a target device, and an operation manager configured to perform an operation control of the target device, and re-perform, when the voltage manager determines that the voltage abnormality has occurred, the operation control being performed at a time of the occurrence of the voltage abnormality.

Abstract: A one-time programmable (OTP) memory device includes a memory array having multiple memory elements. The memory array includes a plurality of anti-fuse FinFETs and a plurality of access FinFETs. Each anti-fuse device has a first terminal for receiving a programming voltage and a second terminal. The anti-fuse FinFETs are located in a first region of an integrated circuit. At least one anti-fuse FinFET of the plurality of anti-fuse FinFETs and at least one access FinFET of the plurality of access FinFETs form a memory element of the plurality of memory elements of the memory array. Each access FinFET is configured to selectively couple one of a program inhibit voltage and a program enable voltage to the second terminal of a corresponding anti-fuse FinFET in a programming operation. The access FinFETs are located in a second region of the integrated circuit, different than the first region of the integrated circuit.

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a plurality of memory cells arranged in a plurality of memory regions and (ii) inhibit circuitry. In some embodiments, the inhibit circuitry is configured to disable one or more memory regions of the plurality of memory regions from receiving refresh commands such that memory cells of the one or more memory regions are not refreshed during refresh operations of the memory device. In these and other embodiments, the memory controller is configured to track memory regions that include utilized memory cells and/or to write data to the memory regions in accordance with a programming sequence of the memory device.

Abstract: A system includes a processing device and a personal communication device. The dash camera may be configured to be removably mounted in a vehicle with a view of a direction ahead of the vehicle and no further installation to said vehicle. The personal communication device is generally separate from the dash camera and the vehicle. The dash camera generally comprises a processing device and one or more sensors configured to generate data related to motion of the vehicle. The processing device generally collects (i) the data related to motion of the vehicle and (ii) video, and, in response to the data being indicative of an accident, automatically communicates collected data and a video sequence recorded prior to the data being indicative of the accident to the personal communication device and automatically initiates an emergency call using the personal communication device.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for instrumentation and control of workloads in a massively parallel processing database. Deployment is in a cluster which mirrors the cluster of the database to be controlled. The system includes data publishing modules, action agents, rules processing modules, deployment managers, rule compilation and management tools. Together these provide a distributed, fault tolerant system for the automated rules-based control of work in a database cluster. For example, in deploying an update, a deployment manager pushes the update to one or more nodes and instructs each of the one or more nodes to restart in a bootstrap mode. The deployment manager generates a respective configuration package for each of the one or more nodes, and restarts each of the one or more nodes in a production mode.

Abstract: A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.

Abstract: Circuits, devices and methods are provided to manage modifications to protected registers within an implantable medical device (IMD). The circuit comprises a bus controller that includes an address register, an unlock register and a protected register (PR) enable unit. The PR enable unit sets a protect enable signal to an access state based on content loaded into the unlock register. A peripheral block includes a protected register that retains content for operating the IMD. The peripheral block includes a register access input to receive the protected enable signal. A PR write control unit is provided to enable an attempted write of the content from a data interface to the protected register when the protected enable signal has an access state.

Abstract: Methods, systems, and computer-readable and executable instructions are provided for checkpointing using a field programmable gate array (FPGA). Checkpointing using FPGA can include checkpointing data within a region of a server's contents to memory and monitoring the checkpointed data using the FPGA.

Abstract: A method for generating a reprogramming file for reprogramming a target electronic control unit (ECU) in a target vehicle converts high-to-low level command conversions specific for the target ECU to generate Unified Diagnostic Services (UDS) operation transactions. The method converts high-level language diagnostic sequence commands into imperative language instructions that are compiled into binary code corresponding to handling routines. A binary image of the target ECU is segmented into a plurality of data blocks that are compiled along with respective the UDS operation transactions to provide a plurality of UDS stages. The plurality of UDS stages and the handling routines are assembled into the reprogramming file.

Abstract: In an aspect, the disclosure is directed to a circuit which includes not limited to a memory circuit which includes a first memory element outputting a first memory output voltage and a second memory element outputting a second memory output voltage; a logical comparator circuit which is connected to the memory circuit and includes a first logical comparator which compares the first memory output voltage with a first power supply voltage to generate a first logical comparator output voltage and a second logical comparator which compares the second memory output voltage with a second power supply voltage to generate a second logical comparator output voltage; and a logical circuit which is electronically connected to the logical comparator circuit and receives a first logical comparator output voltage and a second logical comparator output voltage to perform a first logical operation which is used at least in part to generate a power on reset voltage.

Abstract: A semiconductor memory device may include a memory cell array. The semiconductor memory device may include a peripheral circuit coupled to the memory cell array through word lines. The semiconductor memory device may include an overdrive setting unit configured for determining an overdrive set parameter of an overdrive operation using an operation voltage applied to the word lines.

Abstract: Direct data transfer between devices having a shared bus may be implemented with reduced involvement from a controller associated with the devices. A controller, a source memory device, and a target memory device may be coupled with a shared bus. The controller may identify a source address at the source memory device for data to be transferred to the target memory device. The controller also may identify a target address in the target memory device, and initiate a data transfer directly from the source to the target through a command that is received at both the source and the target memory device. In response to the command, the source memory device may read data out to the bus, and the target memory may read the data from the bus and store the data starting at the target address without further commands from the controller.

Abstract: A CRUM unit which is mountable/dismountable on an image forming apparatus is disclosed. The CRUM unit includes a power extracting circuit to, when a clock signal is received from an image forming apparatus, extract power from a high value of the clock signal and store in a capacitive element and a controller to operate using the extracted power, wherein the clock signal has a first pulse width in a data section where a data signal is received and transmitted, and has a second pulse width which is different from the first pulse width in an pause section where a data signal is not received.

Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.

Abstract: According to embodiments of the present invention, a flip-flop circuit is provided. The flip-flop circuit includes a first stage circuit and a second stage circuit, wherein each of the first stage circuit and the second stage circuit is operable in two modes of operation, and a driver arrangement, wherein the first stage circuit includes a first transistor and a first non-volatile memory cell connected to each other, wherein the second stage circuit includes a second transistor and a second non-volatile memory cell connected to each other, and wherein the driver arrangement is configured, at a clock level, to drive the first stage circuit in one of the two modes of operation to access the first non-volatile memory cell and, at the clock level, to drive the second stage circuit in the other of the two modes of operation to access the second non-volatile memory cell.

Abstract: A semiconductor memory device includes memory cells, a sense amplifier unit including a first latch circuit, and a control unit configured to execute read and write operations on the memory cells. The control unit, while executing the write operation on the memory cells, responsive to a write suspend command followed by a read command, performs a data saving operation, the read operation, and a data restoring operation prior to resuming the write operation. The data saving operation includes transferring first data stored in the first latch circuit to an external device, the first data including at least a result of verify operation performed on the memory cells. The data restoring operation includes transferring the first data to the first latch circuit.

Abstract: Data may be transferred from a communication subsystem of a first device to a communication subsystem of a second device contactlessly, at high speed, and without intervention by host processors of either device. Devices may be programmed or personalized at the factory or warehouse, and may personalized at a warehouse or at a point of sale while in the box. Various modes of operation and use scenarios are described. Portions of the devices themselves, or a transmission path between the devices may be shielded against snooping by a material which degrades an EHF signal passing therethrough.

Abstract: A memory is provided in which the word line assertion during a write operation is delayed until the discharge of a dummy bit line is detected.

Abstract: A storage device is configured to communicate with a host device over a Bluetooth connection. The storage device includes a flash memory, a processor, and a Bluetooth controller. The memory stores at least one permission for determining access to the memory. The processor manages access to the memory, independently of the host device, based on a comparison of a request at the removable storage device to access the memory to at least one permission. The comparison is independent, requiring no management by an operating system of the host device, such that if the at least one permission includes a particular access type that matches the access requested in the request, the processor provides access to the memory.

Abstract: Information can be stored in a cochlear stimulation system by determining an item of patient specific information, transferring the item of patient specific information to an implantable portion of the cochlear stimulation system, and permanently storing the item of patient specific information in the implantable portion of the cochlear stimulation system. The item of patient specific information can comprise a parameter for use in generating a stimulation current. The implantable portion of the cochlear stimulation system also can be configured to permanently store one or more items of patient specific information in an alterable fashion. Further, an item of patient specific information can be retrieved from the implantable portion of the cochlear stimulation system. Additionally, an item of non-patient specific information for use in processing a received acoustic signal can be determined and permanently stored in an external portion of the cochlear stimulation system.

Abstract: A memory controller and/or memory device control termination of a communication link in order to achieve power savings while reducing or eliminating unwanted reflections in the channel. Following transmission of data over the communication channel, termination is left enabled for a programmable time period beginning immediately following completion of the transmission. The time period is sufficiently long to allow the unwanted reflections to be absorbed by the termination. Following the time period, the termination is disabled for power savings.

Abstract: A semiconductor device including: a first slave device; a first master device outputting a first request control signal and a first access address signal; a second master device outputting a second request control signal and a second access address signal; a system bus connected to the first slave device, the first master device and the second master device, and selecting and outputting either the first request control signal or the second request control signal when the first request control signal is outputted from the first master device and the second request control signal is outputted from the second master device; and a range setting register holding an address range of which an access of the first master device is permitted, wherein the system bus blocks the first request control signal if the first access address signal is out of the address range.

Abstract: A semiconductor apparatus includes a plurality of memory banks configured to perform a refresh operation in response to an address count value and row active signals; a refresh control block configured to update refresh bank informations which define a bank designated to perform the refresh operation in response to a refresh command and bank addresses, and activate a count control signal in response to the refresh bank informations; and a counter configured to change the address count value in response to activation of the count control signal.

Abstract: Systems and methods for immediate physical erasure of data in a memory system in response to a user command are disclosed. In one implementation, a memory system includes a non-volatile memory and a controller in communication with the non-volatile memory. The controller comprises a processor that is configured to receive from a host in communication with the memory system, a destruct command that indicates a user request to make the memory system inoperable. The processor is further configured to perform one or more operations to render the memory system inoperable in response to the destruct command received from the host.

Abstract: The disclosure provides an internal power supply voltage auxiliary circuit for an internal power supply voltage generating circuit, wherein the internal power supply voltage generating circuit includes: a differential amplifier, comparing an internal power voltage supplied to a loading circuit with a predetermined reference voltage, and outputting a control voltage from an output terminal; and a driving transistor, driving an external power voltage according to the control voltage. The internal power supply voltage auxiliary circuit includes: a time sequence detecting circuit, detecting a transition of a data signal, generating and outputting a detecting signal; and an internal power voltage auxiliary supplying circuit, auxiliary supplying a current for the loading circuit based on the detecting signal. Therefore, it is possible to output an internal power voltage stably, while power consumption would not increase greatly, even when being used in the semiconductor memory device with the DDR.

Abstract: In a repair of a random access memory (RAM), an error information is received, a fail address of the RAM identified, and a one-time programming applied to a portion of the redundancy circuit while a content of the RAM is valid. Optionally, the RAM is a dynamic access RAM (DRAM), a refresh burst is applied to the DRAM, followed by a non-refresh interval, and the one-time programming is performed during the non-refresh interval.

Abstract: A semiconductor apparatus includes a plurality of unit memory blocks and a plurality of sense amplifier arrays configured to be shared with two or more unit memory blocks among the plurality of unit memory blocks, and amplify data of the unit memory blocks. When a unit memory block corresponding to an external address and a unit memory block corresponding to a refresh address among the plurality of unit memory blocks are coupled in common to one of the plurality of sense simplifier arrays, the semiconductor apparatus stores the refresh address and executes a normal operation command corresponding to the external address.

Abstract: Apparatuses and methods for improving retention performance of hierarchical digit lines are disclosed herein. An example apparatus may include a first digit line portion and a second digit line portion. The apparatus may further include a first selector configured to selectively couple the first digit line portion to the second digit line portion based, at least in part, on a first control signal. The apparatus may further include a second selector configured to selectively couple the second digit line portion to a voltage based, at least in part, on a second control signal.

Abstract: A static random access memory includes a memory cell array, a control logic configured to generate a first write clock signal and a second write clock signal each of which having a pulse width shorter than a pulse width of a clock signal in response to the clock signal, a row decoder configured to select a word line in response to the second write clock signal during a write operation, a column selector configured to select a bit line and an inverted bit line, a sense amplifier configured to sense states of the selected bit line and the selected inverted bit line during a read operation and a write driver configured to bias the selected bit line and the selected inverted bit line in response to the first write clock signal during the write operation.

Abstract: A reprogramming device is used for reprogramming embedded systems. The reprogramming device comprises a microprocessor, a memory programmed with software to accomplish the reprogramming of distinctly different embedded systems architectures, and one or more hardware devices that facilitate communication over multiple protocols contained in a portable package designed for both one-time and multi-occurrence use scenarios. In some embodiments, the reprogramming device is able to be used to enhance one or more attributes of performance of existing embedded systems through the reconfiguration of internally stored parameters. In some embodiments, the reprogramming device is also to be used to extract and receive information and instruction from existing embedded systems and enable useful presentation of this information. As a result, the reprogramming device is able to be used to adjust and/or monitor the parameters of the on-board diagnostics computer of a vehicle to ensure peak performance and detect errors.

Abstract: A method includes mounting a persistent volume of a data storage device of an electronic device. The persistent volume is based on a protected volume stored at the data storage device. The method also includes accessing the persistent volume to enable servicing access to the data storage device of the electronic device.

Abstract: Described is an apparatus of a non-volatile logic (NVL), the apparatus comprises: a sensing circuit to sense differential resistance; a first magnetic-tunneling-junction (MTJ) device coupled to the sensing circuit; a second MTJ device coupled to the sensing circuit, the first and second MTJ devices operable to provide differential resistance; and a buffer to drive complementary signals to the first and second MTJ devices respectively.

Abstract: A memory includes a DRAM array having memory cells, wordlines and bitlines coupled to the memory cells, and sense amplifiers. The memory can be configured to perform a method in which a wordline of the DRAM array is set to an active state. While the wordline is active, signals develop on the respective bitlines according to the flows of charge between the memory cells coupled to the wordline and the respective bitlines. The sense amplifiers connected to the respective bitlines can remain inactive such that the sense amplifiers do not amplify the signals to storable signal levels. Then, when the wordline is set again to the inactive state, insufficient charge remains in the memory cells coupled to the wordline such that the data stored in memory cells coupled to the wordline are erased. These steps can be repeated using each of a remaining number of wordlines of all or a selected range of the DRAM array so as to erase the data stored in all of the DRAM array or a selected range.

Abstract: A method and apparatus are disclosed for management of linked lists within a dynamic queue system. In a dynamic queue system where a central memory is shared amongst a set of queues, the method organizes the linked list structures of the queues. The linked list pointers of the queues are organized over a set of single port memories. Memory for the queue entries is allocated in an alternating fashion, which allows the method to provide per-cycle access to queues while reducing the footprint of the memory elements used for maintaining the linked list structures. The method disclosed reduces the overall memory requirements for the design and implementation of queue systems with multiple queues sharing a common pool of memory.

Abstract: In order to reduce occurrence of a fetching error of a digital signal, caused by a power-source noise, there is provided a semiconductor device provided with a switching circuit for executing a switching operation according to a pulse control signal and a digital signal hold circuit for fetching a digital signal. The digital signal hold circuit includes a mask signal generation circuit for generating a mask signal from the pulse control signal, the mask signal being for use in keeping the digital signal from being fetched during a time period of power-source noise occurrence caused by the switching operation, and the digital signal is not fetched during the time period of power-source noise occurrence while the digital signal is fetched during a time period of power-source noise nonoccurrence.

Abstract: A microcomputer includes a CPU, a protection information storage configured to store memory protection information specifying an access permission or a prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information, and a reset apparatus configured to invalidate the memory protection information stored in the protection information storage according to a reset request signal output from the CPU to a switching of programs executed by the CPU, the reset request signal being based on a state of execution of the program by the CPU. The reset apparatus sets all valid bit storing fields of a plurality of protection setting registers of the protection information storage to invalid state in response to the reset request signal output by the CPU.

Abstract: Methods and devices for charging unselected bit lines are disclosed. The rate at which inhibited (or unselected) bit lines are charged may depend on a program condition. The program condition may be completion of a program loop. As another example, the program condition may be a certain program state completing or nearly completing programming. As one example, the bit lines may be charged at a faster rate prior to the program condition occurring than after the program condition. As another example, the bit lines may be charged at a slower rate prior to the program condition than after the program condition. Charging the unselected bit lines at a slower rate may reduce current consumption. Charging the unselected bit lines at a faster rate may allow for faster programming.

Abstract: A semiconductor memory device and a method of operating a semiconductor memory device includes connecting selected even bit lines to selected even cell strings, programming memory cells in the selected even cell strings by using a second program permission voltage higher than a first program permission voltage, connecting selected odd bit lines to selected odd cell strings when programming of the memory cells is finished, and programming memory cells in the selected odd cell strings by using the first program permission voltage.