Abstract: Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch.

Abstract: A method and apparatus for extracting a time constant from a time series of values of a signal that varies in accordance with multiple charge carrier trap defects that cause Random Telegraph Noise (RTN), using transition-based assignment of states.

Abstract: A non-volatile memory comprising a NOR block with a first sub-block independently addressable from a second sub-block, the two sub-blocks sharing a physical substrate of the NOR block, and a first memory to store execution status information to reflect an erase status of the first sub-block. A method to selectively erase the first sub-block while inhibiting the second sub-block from erasing, comprising updating execution status information associated with the first sub-block and resuming erasing upon an occurrence of an interruption event depending on the indication of the execution status information.

Abstract: A memory circuit includes a plurality of memory cells and a plurality of bit lines and row lines connected to the memory cells for accessing selected memory cells. The memory circuit includes a programmable voltage source adapted for connection to at least one bit line and operative to precharge the bit line to a prescribed voltage level prior to accessing a selected one of the memory cells coupled to the bit line. A control circuit coupled to the bit line is operative to oppose discharge of the bit line during at least a portion of a given memory read cycle. A tracking circuit connected to the control circuit is operative to control a delay in activation of the control circuit and/or a duration of time the control circuit is active as a function of a parameter affecting signal development time of a data signal on the bit line.

Abstract: A method for limiting writing of data to a specific memory cell without disconnecting a wiring of a memory cell array or placing a prober in contact with a memory cell, a row, or a column is provided. Row address data and column address data of a memory cell to which data cannot be written are stored in a register. Enable data which controls data writing is stored in the register. Next, in order to write data to a memory cell, row address data and column address data of a memory cell to which data is written, writing enable data, and the like are output from a logic circuit; thus, writing of data to a memory cell corresponding to the address data stored in the register is inhibited.

Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

Abstract: An apparatus for measuring data setup/hold time is capable of effectively measuring a setup/hold time of data, and includes a data generating unit for delaying an external clock signal according to counting signals and generating an internal clock signal and data signals from the delayed external clock signal in response to test signals, a data latch unit for latching buffered data signals in synchronization with the internal clock signal, wherein the buffered data signals are produced by buffering the data signals, a flag signal generating unit for generating flag signals from the latched data signals latched in the data latch unit in response to the test signals, and a counter for producing the counting signals in response to the flag signals.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.

Abstract: Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided.

Abstract: A solid state mass storage device having a first storage area portion and a second storage area portion. The mass storage device including accessing means adapted to cause data to be stored in the first storage area portion in one of: only in memory cells belonging to columns of a first collection or only to columns of a second collection such that memory cells of the first storage area portion belonging to the first or second collection are left unprogrammed; or only in memory cells of even rows or only memory cells of odd row such that the memory cells of the first storage area belonging to the even or to the odd rows are left unprogrammed; or only in memory cells such that memory cells that are immediately adjacent to said memory cells in said row and column are left unprogrammed.

Abstract: A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals.

Abstract: A memory includes a memory cell array including destructive read-out type memory cells; a decoder selecting a cell; a sense amplifier configured to detect the data; and a read and write controller controlling a read operation and a write operation, wherein the read and write controller outputs a logical value of a write enable signal at the start of the read operation in a first period and makes the write enable signal invalid after the read operation starts during the first period, on the basis of the write enable signal and a restore signal keeping an activated state during the first period, the write enable signal being a signal allowing the write operation, the first period being a period from when the read operation starts to when a restore operation for writing the data back to the memory cell is completed.

Abstract: Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided.

Abstract: A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully.

Abstract: A method for access control to at least one memory area of a passive and/or backscatter-based transponder is provided. In the method for access control, depending on an identification selection criterion, a first or at least one second identification within the transponder is activated, the activated identification upon an appropriate request by reader unit is transmitted to said unit, the at least one memory area of the transponder is divided into memory blocks with a settable size, access control information is assigned to a respective memory block, and read and/or write access to a specific memory block is released or blocked depending on the associated access control information and the identification selection criterion.

Abstract: Provided are methods of programming a nonvolatile data storage device including memory blocks sharing a block word line. The methods may include selecting the memory blocks, and the selected memory blocks may include a first memory block that is to be programmed and a second memory block that is to be program-inhibited. The methods may also include applying a program voltage to a selected word line of the first memory block. The methods may further include applying a bipolar prohibition voltage to word lines of the second memory block.

Abstract: A semiconductor memory device includes a bit line sense amplifier block array, upper and lower memory cell arrays and a sense amplifier controller. The bit line sense amplifier block array senses and amplifies data of a memory cell array. The upper and the lower memory cell arrays are respectively connected to upper and lower sides of the bit line sense amplifier block array and store the data in the memory cell array. The sense amplifier controller selectively connects one of the upper and lower memory cell arrays to the bit line sense amplifier block array in response to an active command, and releases the connection when a corresponding one of the upper and lower memory cell arrays are not selected but overdriven.

Abstract: A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.

Abstract: A semiconductor device includes a nonvolatile memory configured to store write data in a write-enabled state, a check circuit configured to enable the write data as data for comparison in response to an enabled-status indicating signal indicative of the write-enabled state and to output a result of comparison obtained by comparing data read from the nonvolatile memory with the enabled data for comparison, and a path configured to output the result of comparison output from the check circuit to outside the semiconductor device, wherein no path to output the data read from the nonvolatile memory to outside the semiconductor device is in existence.

Abstract: Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch.

Abstract: An integrated cell and method for extracting a binary value based on a value difference between two resistors values, including connection circuitry for a binary reading of the sign of the difference between the resistors, and connection circuitry for a modification of the value of one of the resistors to make the sign of the difference invariable.

Abstract: A memory including an array of memory cells and a control circuit. The control circuit is configured to control partial array self refreshes and to switch from one partial array self refresh to another partial array self refresh. Data in memory cells that are refreshed via the one partial array self refresh and refreshed via the other partial array self refresh is retained in the memory cells from before a first switch from the one partial array self refresh to the other partial array self refresh to after the first switch.

Abstract: A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully.

Abstract: A semiconductor device includes a nonvolatile memory configured to store write data in a write-enabled state, a check circuit configured to enable the write data as data for comparison in response to an enabled-status indicating signal indicative of the write-enabled state and to output a result of comparison obtained by comparing data read from the nonvolatile memory with the enabled data for comparison, and a path configured to output the result of comparison output from the check circuit to outside the semiconductor device, wherein no path to output the data read from the nonvolatile memory to outside the semiconductor device is in existence.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.

Abstract: A circuit for generating a read end signal includes a clock transferring unit which receives a clock signal, a write/read status signal and an all bank precharge signal and outputs a delayed clock signal, a read signal detecting unit which receives a read pulse signal and the delayed clock signal and generates a read detection signal having a pulse width corresponding to a certain clock, and a read end signal generating unit which receives a first signal, the delayed clock signal and the read detection signal and generates a read end signal.

Abstract: Provided is a method for programming a flash memory device. The method includes receiving writing data, detecting leakage bit lines of the flash memory device, and updating the received writing data in order for data corresponding to the leakage bit lines to be modified as program-inhibit data. A programming operation is performed on the flash memory device after updating the writing data.

Abstract: A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array.

Abstract: A storage system that comprises multiple solid-state storage devices includes a command set that enables a host system to initiate one or more types of purge operations. The supported purge operations may include an erase operation in which the storage devices are erased, a sanitization operation in which a pattern is written to the storage devices, and/or a destroy operation in which the storage devices are physically damaged via application of a high voltage. The command set preferably enables the host system to specify how many of the storage devices are to be purged at a time during a purge operation. The host system can thereby control the amount of time, and the current level, needed to complete the purge operation. In some embodiments, the number of storage devices that are purged at a time may additionally or alternatively be selectable by a controller of the storage system.

Abstract: An integrated circuit memory is described having multiple memory banks which are grouped into repair groups Group0, Group1. One of the memory banks is provided with redundant rows which can be used to substitute for a defective row found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells are also provided and these may be substituted for defective columns by multiplexing circuitry. This multiplexing circuitry shifts the bit lines which are selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry thereby reducing the number of redundant columns which need be provided.

Abstract: Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories.

Abstract: To provide a data fetch circuit, which reliably cuts off transmission of a high impedance state of a data strobe signal even if a manufacture condition or an operation condition is changed, and a control method thereof. The data fetch circuit includes an RL measuring part 10 measuring a latency measurement value RLB from an input of a read instruction signal RD to a valid edge of a data strobe signal DQS and an RL count comparing part 30 outputting a BL count start signal BST giving an instruction of a cancel of the cut-off of the data strobe signal DQS after standing by during the time based on the latency measurement value RLB in accordance with an input of a delay read instruction signal RDD.

Abstract: Methods and apparatus are provided for read/write control and bit selection with false read suppression in an SRAM. According to one aspect of the invention, a bit select circuit is provided for an SRAM. The disclosed bit select circuit comprises one or more transistors controlled by a write control gate signal to prevent data from being read from one or more data cells during a write operation. The transistors can comprise, for example, a pair of gated transistors controlled by the write control gate signal. The write control gate signal prevents data from being read from one or more data cells while the write control gate signal is in a predefined state.

Abstract: A memory system comprising one or more memory devices is purged to prevent unauthorized access to data stored therein. A host system passes control of purge operations to the memory system. The purge operations are configured to erase data, write a pattern to memory locations, physically damage the memory devices in the memory system, or combinations of the foregoing. The memory system can perform a purge operation on two or more memory devices in parallel. The memory system includes a destroy circuit to provide an over-current and/or over-voltage condition to the memory devices. The memory system also includes one or more isolation circuits to protect control circuitry in the memory system from the over-current and/or over-voltage condition. In some embodiments, the memory system includes a backup battery so it can complete a purge operation if it loses its power connection to the host system.

Abstract: A memory device is provided for performing writing operations on memory cells while maintaining a stability thereof. A memory array is provided including a plurality of memory cells. Additionally, segmented write bitlines are provided for performing writing operations on the memory cells while maintaining a stability thereof.

Abstract: A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line.

Abstract: A redundancy scheme for Non-Volatile Memories (NVM) is described. This redundancy scheme provides means for using defective cells in non-volatile memories to increase yield. The algorithm is based on inverting the program data for data being programmed to a cell grouping when a defective cell is detected in the cell grouping. Defective cells are biased to either “1” or “0” logic states, which are effectively preset to store its biased logic state. A data bit to be stored in a defective cell having a logic state that is complementary to the biased logic state of the cell results in the program data being inverted and programmed. An inversion status bit is programmed to indicate the inverted status of the programmed data. During read out, the inversion status bit causes the stored data to be re-inverted into its original program data states.

Abstract: A method and apparatus for write enable and write inhibit for high density spin torque three dimensional (3D) memory arrays.

Abstract: RFID tag circuits, tags, and methods are provided for using alternative memory lock bits. A pointer in tag memory is configured to point to one or the other of the alternative lock bits associated with a section of the memory for performing a function in response to a reader command. Upon receiving the reader command, the tag first checks the pointer and performs the function based on which lock bit(s) is selected.

Abstract: A memory interface subsystem including a write logic and a read logic. The write logic may be configured to communicate data from a memory controller to a memory. The read logic may be configured to communicate data from the memory to the memory controller. The read logic may comprise a plurality of physical read datapaths. Each of the physical read datapaths may be configured to receive (i) a respective portion of read data signals from the memory, (ii) a respective read data strobe signal associated with the respective portion of the received read data signals, (iii) a gating signal, (iv) a base delay signal and (v) an offset delay signal.

Abstract: A verify operation is performed on the one time programmable memory block to determine if it has been programmed. If any bits have been programmed, further programming or erasing is inhibited. In another embodiment, the memory block can be programmed and erased until a predetermined page or lock bit in the block is programmed. Once that page/bit is programmed, the one time programmable memory block is locked against further programming or erasing.

Abstract: One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.

Abstract: A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage.

Abstract: Methods for programming a memory array and memory devices are disclosed. In one such method, inhibited bit lines are charged to an inhibit voltage that is less than a supply voltage. The word lines of memory cells to be programmed are biased at a programming preparation voltage that is less than a nominal programming preparation voltage as used in the conventional art. Programming pulses can be applied to selected word lines of the memory cells to be programmed when the uninhibited bit lines are at 0V.

Abstract: A memory device having a plurality of memory cells employs a method to detect a light attack on the memory device. The method utilizes at least one memory cell to detect a light attack when the memory cell is in an inactive state, and outputs a signal indicating whether a light attack is detected. In one case, the method includes turning off all of the memory cells of memory blocks of the memory device that are not currently being accessed for a read/write operation; sensing a leakage current of at least one of the memory cells of the memory blocks that are not currently being accessed for a read/write operation; and detecting a light attack on the memory device when a leakage current of the one of the memory cells of the memory blocks that are not currently being accessed for a read/write operation is greater than a threshold.

Abstract: Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch.

Abstract: Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided.

Abstract: A program lock circuit for inhibiting programming of memory cells. A memory array can have both mask programmable and one-time programmable memory cells connected to the wordlines and the bitlines. Since the one-time programmable memory cells are convertible into mask programmable memory cells through mask programming, such as diffusion mask programming or contact/via mask programming, these mask programmed cells are still electrically programmable, thereby destroying the originally stored data. The programming lock circuit inhibits programming of the mask programmed cells by detecting an activated wordline during a programming operation, and then immediately disabling or decoupling the high voltage supply that is provided to the wordline drivers. Mask programmed transistor elements coupled to each wordline detect the wordline voltage and disable the high voltage supply. A mask programmable master lock device can be provided to inhibit all the rows in the memory array from being programmed.

Abstract: Semiconductor device having multiple I/O modes. The device includes a data buffer configured to receive data; a strobe input buffer configured to receive a data strobe signal, a phase controller configured to shift a phase of the data strobe signal by different numbers of degrees, including 0 degrees, according to input modes and a data detector configured to detect the data in response to the data strobe signal output from the phase controller.

Abstract: The present invention relates to a non-volatile memory comprising a memory array comprising functional memory cells and non-functional memory cells linked to at least one non-functional word line. A word line address decoder comprises a special decoding section linked to the non-functional word line, for selecting the non-functional word line when a functional word line is read-selected, such that non-functional memory cells are selected simultaneously with the functional memory cells, and distort the reading of the functional memory cells. Application particularly to integrated circuits for smart cards.