Abstract: A method of operating a non-volatile memory includes; during power-on, reading control information from an information block and lock information from an additional information block, then upon determining that a secure block should be locked, generating a lock enable signal that inhibits access to data stored in the secure block, and a read-only enable signal that prevents change in the data stored in the additional information block.

Abstract: A memory module has at least one secure and at least one insecure memory area, separate write/read electronic units for each of the memory areas and at least one shared analog circuit part such as a voltage supply circuit for supplying the write/read electronic units and/or the memory areas.

Abstract: A semiconductor memory device includes a memory block as a code storage memory area which has a large memory capacity and in which the number of bits to be written at once is large, and a memory block as a work memory area which has a small memory capacity and in which the number of bits to be written at once is small, in which in writing to the code storage memory area a first voltage is supplied to a source line of this memory block, and in writing to the work memory area a second voltage higher than the first voltage is supplied to a source line of this memory block.

Abstract: When writing into an antifuse memory element finishes, a value of resistance of the memory element rapidly decreases; accordingly, an output voltage of a boosting circuit which produces a writing voltage rapidly decreases. By detecting a change in the output voltage of the boosting circuit to control a writing command, the writing operation can be stopped immediately after the memory element is shorted. Thus, unnecessary current consumption caused by continuing a writing operation on the shorted memory element can be suppressed.

Abstract: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. The memory further may include chip enable circuits having control logic configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

Abstract: An operating method of a semiconductor memory device includes precharging a channel region of a program-inhibited cell of first memory cells coupled to a first word line, selected from a first one of word line groups between a drain select line and a source select line, to a first level based on first data; performing a first program operation for storing the first data in the first memory cells; precharging the channel region of a program-inhibited cell of second memory cells coupled to a second word line, selected from a second one of the word line groups, to a second level based on second data to be stored in the second memory cells; and performing a second program operation for storing the second data in the second memory cells.

Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

Abstract: Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided.

Abstract: Memory cells which have read noise are identified during a programming pass and an amount of programming is increased for noisy memory cells compared to non-noisy cells. The read noise is indicated by a decrease in the threshold voltage of a cell when the cell is repeatedly read. In one approach, during the programming pass, a cell enters a temporary lockout state when it passes a first verify test and is subject to one or more additional verify tests. Data is stored to identify the cell as a noisy cell or a non-noisy cell based on the one or more additional verify tests. Or, the cells are subject to the one or more additional verify tests at the end of the programming pass. In a subsequent programming pass, the noisy cell is programmed using a stricter verify condition. Or, the noisy cell is kept in an erased state.

Abstract: Methods for operating a non-volatile storage system utilizing a shared-bit-line NAND architecture are described. A shared-bit-line NAND architecture includes one or more pairs of NAND strings, wherein each pair of the one or more pairs of NAND strings shares a common bit line. In some embodiments, a pair of NAND strings includes an odd NAND string adjacent to an even NAND string. Prior to programming a memory cell associated with the even NAND string, an odd channel associated with the odd NAND string (i.e., the NAND string of the pair that is not selected for programming) is precharged to a bit line inhibit voltage, floated, and then boosted to a second voltage greater than the bit line inhibit voltage as an even channel associated with the even NAND string is precharged. Subsequently, the odd channel may be boosted (e.g., via self-boosting) prior to programming the memory cell.

Abstract: Memory cells which have read noise are identified during a programming pass and an amount of programming is increased for noisy memory cells compared to non-noisy cells. The read noise is indicated by a decrease in the threshold voltage of a cell when the cell is repeatedly read. During the programming pass, a cell enters a temporary lockout state when it passes a first verify test. In this state, the cell is subject to one or more additional verify tests. If the one or more additional verify tests indicate that the threshold voltage of a cell has decreased, the cell is noisy and is soft programmed before being permanently locked out. In contrast, programming of a non-noisy cell is concluded after the first verify test without further programming.

Abstract: A semiconductor device includes a sense amplifier, transistors selectively establishing electrical connection between the sense amplifier and a data bus, depending on address; a write amplifier connected to the data bus, an external terminal outputting data from a memory cell to outside via the sense amplifier, the transistors, and the data bus in a first operation mode and supplying data from outside to the sense amplifier via the write amplifier, the data bus, and the transistors in a second operation mode, and a control circuit supplying an electric potential to gate electrodes of first transistors that establish the electrical connection depending on the address.

Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

Abstract: An electric physical unclonable function (PUF) (100) is provided comprising a semiconductor memory element (110) connectable to a PUF control means for reading content from the memory element and for deriving at least in part from said content a digital identifier, such as a secret key. Upon powering the memory element it settles into one of at least two different stable states. The particular stable state into which the memory element settles is dependent at least in part upon random physical characteristics of the memory element introduced during manufacture of the memory element. Settling of the memory element is further dependent upon a control input (112) of the memory element.

Abstract: A content addressable memory (CAM) device has an array including a plurality of CAM rows that are partitioned into row segments, wherein a respective row includes a first row segment including a number of first CAM cells coupled to a first match line segment, a second row segment including a number of second CAM cells coupled to a second match line segment, and a circuit to selectively pre-charge the first match line segment in response to a value indicating whether data stored in the first row segment of the respective row is the same as data stored in the first row segment of another row. Power consumption can be reduced during compare operations in which the first row segment of another row that stores the same data as the first row segment of the respective row is not enabled.

Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

Abstract: A radiation hardened memory element includes at least two delay elements for maintaining radiation hardness. In an example, the memory element is an SRAM cell. Both delays are coupled together in series so that if either one of the delays fails, a delay will still be maintained within the SRAM cell. The critical areas of the delays may be positioned so that a common line of sight cannot be made between each delay and a circuit node.

Abstract: A memory has memory cells in a matrix; a first selection unit selecting any of first signal lines in the memory cells, in response to an access request; a second selection unit selecting any of second signal lines in the memory cells, after the first selection unit starts operating; a first voltage generation unit generating a first power supply voltage supplied to the first selection unit; a second voltage generation unit generating a second power supply voltage supplied to the second selection unit, when a start-up signal is active; a switch short-circuiting first and second power supply lines, when a short-circuit signal is active; and a power supply voltage control unit which activates the start-up signal in response to the access request, activates the short-circuit signal after a predetermined time elapses since activation of the start-up signal, deactivates the short-circuit signal and the start-up signal after completion of access operations.

Abstract: Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories.

Abstract: The apparatuses and methods described herein may comprise a memory array formed on a semiconductor substrate and including a plurality of cells associated with a plurality of word lines. The memory array may comprise a plurality of sub-blocks including a first sub-block and a second sub-block. Each sub-block may comprise a memory cell portion of the plurality of memory cells associated with a corresponding word line portion of the plurality of word lines. The memory cell portions in the first and second sub-blocks may be independently addressable with respect to each other such that a second operation can be performed on at least one memory cell of the memory cell portion of the second sub-block responsive to suspending a first operation directed to at least one memory cell of the memory cell portion of the first sub-block.

Abstract: Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.

Abstract: A programming technique which reduces program disturb in a non-volatile storage system is disclosed. A positive voltage may be applied to a substrate (e.g., p-well) during programming. Biasing the substrate may improve boosting of channels of unselected NAND strings, which may reduce program disturb. The substrate may be charged up during the programming operation, and discharged after programming. Therefore, for operations such as verify and read, the substrate may be grounded. In one embodiment, the substrate is charged just prior to applying a program pulse, then discharged prior to a program verify operation. In one embodiment, the substrate is charged while unselected word lines are ramped up to a pass voltage. The substrate bias may depend on program voltage, temperature, and/or hot count.

Abstract: A memory having a memory array having a plurality of word lines, a plurality of bit cells coupled to the word lines, and a plurality of control memory cells coupled to the word lines. Each word line of the plurality of word lines has a control memory cell coupled thereto and each control memory cell has an output. The memory also has a plurality of logic circuits coupled to the plurality of word lines. The output of each control memory cell is coupled to a corresponding one of the plurality of logic circuits. The plurality of logic circuits prevents access to the word line selected by a row address if the output of the control memory cell coupled to the selected word line is in a first logic state.

Abstract: Memory devices and methods are disclosed, such as devices configured to apply a first program inhibit bias to data lines during a first portion of a program operation and to apply a second program inhibit bias to data lines during a second portion of the program operation. The second program inhibit bias is greater than the first program inhibit bias.

Abstract: A semiconductor device includes: a memory cell array comprising a plurality of blocks each comprising a memory cell arranged at an intersection between a word line and a bit line; and a block state information storing unit configured to store state information of the respective blocks. The block state information storing unit stores lock state information to partially limit access to each of the blocks in response to a power-up signal.

Abstract: Disclosed is an operating method of a nonvolatile memory device, which includes programming the first selection transistors of the plurality of cell strings and programming the plurality of memory cells of the plurality of cell strings. The programming the first selection transistors comprises supplying a first voltage to a first bit line connected with a first selection transistor to be programmed and a different second voltage to a second bit line connected to a first selection transistor to be program inhibited; turning on the second selection transistors of the plurality of cell strings, and supplying a first program voltage to a selected first selection line among a plurality of first selection lines connected with the first selection transistors and a third voltage to an unselected first selection line among the plurality of first selection lines.

Abstract: Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided.

Abstract: Command signal management methods and circuits in memory devices are disclosed. Command signals are selectively passed and blocked to enforce safe operating characteristics within a memory device. In at least one embodiment, a command signal management circuit is configured to selectively block a command signal while a memory device operation is being performed. In at least one other embodiment, one or more command blocking circuits are configured to selectively pass and block one or more command signals generated by a memory access device coupled to the memory device while a memory device operation is being performed in the memory device.

Abstract: A mechanism is presented memory circuits, such a NAND-type flash memories, to autonomously protect themselves from temporary and short power drops. A detection mechanism looks for the supply voltage to drop below a function voltage for a period of time. When such an event occurs, a suspend mechanism is activated, and after completing the last micro-operation (such as a program pulse) the memory freezes. When power is again stable at an operational level, the suspended operation is resumed. The memory controller can then be notified upon occurrence of such voltage drop by polling a special status bit. Examples of how the pausing can be implemented include altering of clock signals and suspending sub-phases of larger operations.

Abstract: A semiconductor memory device that may perform a second operation during a first operation comprises a command decoder for generating a decoded command signal, a suspend pulse and a resume pulse, and a storage unit for storing the decoded address signal, the decoded command signal and a data signal in response to the suspend pulse and providing the decoded address signal, the decoded command signal and the decoded data signal as a stored address signal, a stored command signal and a stored data signal, respectively, in response to the resume pulse.

Abstract: A refresh control circuit is capable of activating a plurality of bank selection signals in response to a refresh command signal. Each of the plurality of bank selection signals is assigned to one of a plurality of bank groups. The refresh control circuit is configured to activate the plurality of bank selection signals when a refresh cycle selection signal is deactivated, and activate a part of the plurality of bank selection signals when the refresh cycle selection signal is activated.

Abstract: A semiconductor memory device includes a bit line sense amplifier block array, upper and lower memory cell arrays and a sense amplifier controller. The bit line sense amplifier block array senses and amplifies data of a memory cell array. The upper and the lower memory cell arrays are respectively connected to upper and lower sides of the bit line sense amplifier block array and store the data in the memory cell array. The sense amplifier controller selectively connects one of the upper and lower memory cell arrays to the bit line sense amplifier block array in response to an active command, and releases the connection when a corresponding one of the upper and lower memory cell arrays are not selected but overdriven.

Abstract: An apparatus for measuring data setup/hold time is capable of effectively measuring a setup/hold time of data, and includes a data generating unit for delaying an external clock signal according to counting signals and generating an internal clock signal and data signals from the delayed external clock signal in response to test signals, a flag signal generating unit for generating flag signals according to the internal clock signal and the data signals, and a counter for producing the counting signals in response to the flag signals.

Abstract: A dual port memory includes a mechanism for preventing collisions. The memory includes dual port bit cells arranged in rows and columns and each bit cell stores a data bit. The memory also includes a wordline unit that may provide a respective write wordline signal and a respective read wordline signal to each row of bit cells. The wordline unit may also selectively inhibit the read wordline signal for a given row based upon address information that is indicative of whether a write operation will be performed to the given row.

Abstract: A programming method of a semiconductor memory device includes charging a channel of an inhibit string to a precharge voltage provided to the common source line and boosting the charged channel by providing a wordline voltage to the cell strings. The inhibit string is connected to a program bitline among the bitlines.

Abstract: A dual port memory includes a mechanism for preventing collisions. The memory includes dual port bit cells arranged in rows and columns and each bit cell stores a data bit. The memory also includes a wordline unit that may provide a respective write wordline signal and a respective read wordline signal to each row of bit cells. The wordline unit may also selectively inhibit the read wordline signal for a given row based upon address information that is indicative of whether a write operation will be performed to the given row.

Abstract: A self-refresh control circuit includes: a code generator configured to generate a code by counting periods of a periodic wave based on a self-refresh signal and reset when a code value of the generated code reaches a first value; a bank active signal generator configured to generate a plurality of bank active signals activated in response to different code values of the generated code, respectively, by decoding the generated code; and an address generator configured to change a row address after the plurality of the bank active signals are each activated after the reset of the code generator.

Abstract: A mechanism is provided for enabling a proper write through during a write-through operation. Responsive to determining the memory access as a write-through operation, first circuitry determines whether a data input signal is in a first state or a second state. Responsive to the data input signal being in the second state, the first circuitry outputs a global write line signal in the first state. Responsive to the global write line signal being in the first state, second circuitry outputs a column select signal in the second state. Responsive to the column select signal being in the second state, third circuitry keeps a downstream read path of the cache access memory at the first state such that data output by the cache memory array is in the first state.

Abstract: A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.

Abstract: A nonvolatile semiconductor memory device according to one embodiment includes: a memory cell array; word lines; bit lines; and a control circuit configured to write multi-value data in the memory cells. The control circuit sets either even-ordinal-number bit lines or odd-ordinal-number bit lines as selected bit lines while setting the other as unselected bit lines; applies a write inhibiting voltage to the unselected bit lines; applies a write voltage to the selected bit lines corresponding to unwritten memory cells to be given one of threshold voltage distributions representing different written states; and applies the write inhibiting voltage to the selected bit lines corresponding to unwritten memory cells to be given any other of the threshold voltage distributions representing the different written states, memory cells already written, and memory cells to be maintained in a threshold voltage distribution representing an erased state, thereby executing a write operation.

Abstract: Disclosed herein is a memory device including: first and second wires; memory cells including a variable-resistance storage element having a data storage state making a transition by a change of a voltage applied and an access transistor connected in series between the first and second wires; driving control sections controlling a direct verify sub-operation by applying a write/erase pulse between the first and second wires in a data write/erase operation respectively for causing a cell current to flow between the first and second wires through the memory cell for a transition of the data storage state; sense amplifiers sensing an electric-potential change occurring on the first wire in accordance with control on the direct verify sub-operation; and inhibit control sections determining whether or not to inhibit a sense node of the sense amplifier from electrically changing at the next sensing time on the basis of an electric potential appearing at the sense node at the present sensing time.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, threshold voltages of memory cells being set lowest in an erase state and sequentially set higher according to data in a program state, a plurality of bit lines connected to the memory cells, a word line connected to the memory cells, and a control circuit. In a case where a first memory cell is programmed to a first threshold voltage that is lowest among threshold voltages in the program state, the control circuit is configured to charge a first bit line connected to the first memory cell to a third voltage between a first voltage applied to a bit line when a memory cell is programmed to a second threshold voltage higher than the first threshold voltage and a second voltage applied to a bit line when a memory cell is inhibited from being programmed.

Abstract: Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices, including peripheral circuits and I/O circuits. When the voltage supply to the peripheral circuits of one or more devices is disabled, the I/O circuits of that device may be disabled. In some examples, power may advantageously be saved in part by eliminating or reducing a DC current path through the I/O circuits.

Abstract: A microcomputer includes a CPU, a protection information storage configured to store memory protection information specifying an access permission or prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information and a reset apparatus configured to invalidate the memory protection information stored in the protection information storage according to a reset request signal output from the CPU.

Abstract: A semiconductor device includes a sense amplifier, transistors selectively establishing electrical connection between the sense amplifier and a data bus, depending on address; a write amplifier connected to the data bus, an external terminal outputting data from a memory cell to outside via the sense amplifier, the transistors, and the data bus in a first operation mode and supplying data from outside to the sense amplifier via the write amplifier, the data bus, and the transistors in a second operation mode, and a control circuit supplying an electric potential to gate electrodes of first transistors that establish the electrical connection depending on the address, wherein in a first operation mode, the control circuit supplies a first electric potential to the gate electrodes of the first transistors, so that the first transistors exhibit a first impedance value and in the second operation mode, the control circuit supplies a second electric potential to gate electrodes of the first transistors, so that th

Abstract: A memory system including a one time programmable (OTP) memory is provided. The memory system further includes a write enable verification circuit including an asymmetric inverter stage and a symmetric inverter stage coupled at a node. The write enable verification circuit is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node changes at a second rate higher than the first rate. The write enable verification circuit is further configured to generate a verified write enable signal for enabling programming of the OTP memory.

Abstract: In a document data management apparatus to manage document data read and digitized by an image reading apparatus, management of the document data is performed in view of the reliability of an image reading processing of the image reading apparatus, so that the reliability of various processings using the document data is improved. There are included a document data acquisition unit to acquire document data read and digitized by an image reading apparatus, a reliability determination unit to determine reliability of an image reading processing of the image reading apparatus for the document data based on the document data acquired by the document data acquisition unit, and a storage prohibition unit to prohibit, with respect to the document data for which the reliability determined by the reliability determination unit is lower than a specified threshold value, storage of the document data.

Abstract: In one embodiment, the semiconductor device, includes a non-volatile memory cell array, and a control unit configured to generate a mode signal indicating if a flash mode has been enabled. A write circuit is configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received.

Abstract: An image forming apparatus includes an image receiving unit configured to receive image data, a sender identifying unit configured to identify a sender of the received image data, a check unit configured to check whether the identified sender corresponds to a predetermined sender, a management information providing unit configured to provide management-purpose image data obtained by encoding management information for controlling at least one of a transmission operation for transmitting an image scanned from a printout and a copy operation for copying an image scanned from a printout, and a print unit configured to print the management-purpose image data together with the received image data in response to a check result by the check unit indicating that the identified sender corresponds to the predetermined sender.

Abstract: A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully.