Abstract: A first input unit, coupled to a repair checking node through a first fuse, is for inverting a logic level of the repair checking node in response to a first address. A second input unit, coupled to the repair checking node through a two or more second fuses, is for inverting a logic level of the repair checking node in response to a second address. The number of the second fuses corresponds to a delay time between a transfer path of the first address and a transfer path of the second address. A repair detecting signal generating unit is for generating a repair detecting signal in response to the logic level of the repair checking node. Other embodiments are also described.

Abstract: A method for reducing defect leakage current in a semiconductor memory device comprising a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier columns comprising a plurality of sense amplifiers, wherein there is a sense amplifier column positioned between and shared by memory arrays on opposites thereof. At least one bank-specific isolation control signal is independently generated for each of the plurality of memory banks depending on existence and location of an anomalous bitline leakage in a memory bank. The at least one bank-specific isolation control signal is supplied to at least one sense amplifier column in the corresponding memory bank to isolate at least one side to at least one memory array that is in an unselected state in a corresponding memory bank.

Abstract: A dynamic random access memory (DRAM) device, including a DRAM core having memory cells for storing data information, and a read protection unit, prevents data stored in the memory cells before power-off, from being read out at power-on.

Abstract: A semiconductor memory device has a refresh control circuit for switchingly controlling a first refresh mode in which access to the memory cell array from outside is prohibited while retaining data and a second refresh mode in which access to the memory cell array from outside is permitted while retaining data and for performing the refresh operation of the memory cells corresponding to a selected word line, and a designating circuit for individually designating a portion to be refreshed in the first refresh mode and a portion to be refreshed in the second refresh mode. In the semiconductor memory device, the refresh control circuit performs the refresh operation when the portion to which the selected word line belongs is designated to be refreshed, and does not perform the refresh operation when the portion to which the selected word line belongs is not designated to be refreshed.

Abstract: A device includes an anti-fuse including a first electrode that can be selectively coupled to a first voltage reference and a second electrode that can be selectively coupled to a second voltage reference. The device further includes a shunt transistor including a first current electrode coupled to the first electrode of the anti-fuse, a second current electrode coupled to the second electrode of the anti-fuse, and a control electrode. The device additionally includes control logic configured to disable the shunt transistor in response to a first program operation intended for the anti-fuse. The control logic also is configured to enable the shunt transistor in response to a second program operation not intended for the anti-fuse.

Abstract: A method for operating a memory device is disclosed. In one embodiment, the method includes receiving authorized operating parameters of the memory device and comparing sensed operational parameters to the authorized operating parameters. Access to data stored within the memory device may be prevented if the operational parameters are outside the authorized operating parameters. A memory device and method of manufacturing such a device are also provided.

Abstract: A method for programming a flash memory device which includes a plurality of memory cells arranged in rows and columns. The method includes programming selected memory cells from among the plurality of memory cells according to loaded data bits. Data bits are read from the programmed selected memory cells. It is determined whether each of the programmed memory cells has been successfully programmed based on the results of the reading step. The programming of memory cells that have been determined to have been successfully programmed are inhibited. The programming, reading, determining and inhibiting steps are repeated until each of the selected memory cells has been determined to have been successfully programmed. A memory cell that has been previously determined to have been successfully programmed and inhibited is uninhibited and subsequently re-programmed when it is determined that the previously inhibited memory cell is no longer successfully programmed.

Abstract: A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.

Abstract: A bus control apparatus includes a plurality of blocks configured to output a write command for writing data into memory via a bus, and a bus connection control unit provided in correspondence with each of the blocks. The bus connection control unit monitors signals between the bus and the block, and upon detecting a read command signal for reading data in a cause register of the block, blocks connection of a signal line between the block and the bus and outputs a dummy read command signal for the memory. The bus connection control unit releases blockage when a response signal for the dummy read command signal is received.

Abstract: A memory write timing system includes a modified memory bitcell including a storage device and a write/read circuit for writing/reading data to/from the storage device; and an output circuit for detecting the current state of the storage device.

Abstract: A semiconductor device can include a first ferroelectric random access memory to which a first voltage is applied and a second ferroelectric random access memory to which a second voltage is applied, where the second voltage is lower than the first voltage. A data protection circuit can determine whether test data is normally read from the second ferroelectric random access memory or whether a write-back operation is normally performed on the second ferroelectric random access memory on the basis of the second voltage. The data protection circuit can also generate a read prevention control signal to control whether a read operation is to be performed on the first ferroelectric random access memory based on the determined result.

Abstract: A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The read logic IP block may be configured to communicate data from the double data rate (DDR) synchronous dynamic random access memory (SDRAM) to the memory controller. The master delay IP block may be configured to generate one or more delays for the read logic IP block. The address and control logic IP block may be configured to control the write logic IP block and the read logic IP block. The core is generally configured to couple the double data rate (DDR) synchronous dynamic random access memory (SDRAM) and the memory controller.

Abstract: Methods and apparatus are provided for read/write control and bit selection with false read suppression in an SRAM. According to one aspect of the invention, a bit select circuit is provided for an SRAM. The disclosed bit select circuit comprises one or more transistors controlled by a write control gate signal to prevent data from being read from one or more data cells during a write operation. The transistors can comprise, for example, a pair of gated transistors controlled by the write control gate signal. The write control gate signal prevents data from being read from one or more data cells while the write control gate signal is in a predefined state.

Abstract: The operation code decoder 204 having received an access enable signal EN acquires and decodes the command, and sends the decoded command to the read/write controller 206. In the event that the received command is a write command, the read/write controller 206 acquires access control information from the fourth address following the head address of the memory array 201. In the event that the acquired access control information indicates that write operations are prohibited, the read/write controller 206 does not send the write command received from the operation code decoder 204 to the I/O controller 205.

Abstract: A semiconductor storage apparatus according to one embodiment of the present invention, comprising: memory cells which need refresh operation; and a refresh control circuit which suspends the refresh operation when external access for reading out from or writing into the memory cells is requested.

Abstract: A storage system that comprises multiple solid-state storage devices includes a command set that enables a host system to initiate one or more types of purge operations. The supported purge operations may include an erase operation in which the storage devices are erased, a sanitization operation in which a pattern is written to the storage devices, and/or a destroy operation in which the storage devices are physically damaged via application of a high voltage. The command set preferably enables the host system to specify how many of the storage devices are to be purged at a time during a purge operation. The host system can thereby control the amount of time, and the current level, needed to complete the purge operation. In some embodiments, the number of storage devices that are purged at a time may additionally or alternatively be selectable by a controller of the storage system.

Abstract: A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In particular, the identified memory cells are shut down after all sensing in the current pass have been completed. In this way the shutting down operation does not disturb the sensing operation. Sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells. In another aspect of sensing improvement, a reference sense amplifier is employed to control multiple sense amplifiers to reduce their dependence on power supply and environmental variations.

Abstract: Methods and apparatus are provided for read/write control and bit selection with false read suppression in an SRAM. According to one aspect of the invention, a bit select circuit is provided for an SRAM. The disclosed bit select circuit includes one or more transistors controlled by a write control gate signal to prevent data from being read from one or more data cells during a write operation. The transistors can include, for example, a pair of gated transistors controlled by the write control gate signal. The write control gate signal prevents data from being read from one or more data cells while the write control gate signal is in a predefined state.

Abstract: Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch.

Abstract: Method and apparatus for configuring a programmable logic device to operate at a plurality of clock frequencies comprising configurable programmable self-timed delay circuits and associated configuration software. The configurable IC clock frequencies increase device performance and manufacturing yield.

Abstract: A synchronous DRAM (SDRAM) terminates a write operation in response to detecting deactivation of a data strobe signal applied to it during the write operation. In one example, the SDRAM comprises a buffer circuit and an early write termination circuit. The buffer circuit is configured to sample input data responsive to a data strobe signal applied to the SDRAM during a write operation and direct the input data to one or more memory cells of the SDRAM for storing the input data. The early write termination circuit is configured to terminate the write operation at less than a programmed burst length by disabling access to one or more of the memory cells after storage of the sampled input data responsive to detecting deactivation of the data strobe signal.

Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

Abstract: A semiconductor device and method thereof. The semiconductor device may include a protection unit receiving an input signal and outputting a switching control signal based on the received input signal, the received input signal indicating an operating mode of a controller and a switching device receiving the switching control signal, the switching control signal setting an operating status of the switching device, the operating status of the switching device controlling a connection between the controller and an operating device (e.g., an e-fuse). In an example, the switching device may be controlled such that the operating device may be protected from voltage irregularies output by the controller.

Abstract: A write burst stop command function is provided for a semiconductor memory device, and in particular for a memory device having a write latency, such as is common in a low power double data rate (DDR) dynamic random access memory (DRAM) device. In the memory device, when a write stop command is received, pulses that are generated for a column address strobe signal are terminated so that no further data already in the memory device is transferred into a memory array. When the write stop command is received at the beginning of a write operation prior to generation of the pulses in the column address strobe signal, a first-in first-out (FIFO) circuit is reset. The FIFO circuit is used to introduce a predetermined write latency to the write operation. The column address strobe signal is supplied to a column decoder associated with the memory array and to a data path circuit that transfers data to the memory array based on pulses in the column address strobe signal.

Abstract: A semiconductor device has a memory cell, decoders, a redundancy circuit and a mode setting circuit. The memory cell array has word lines including a redundant word line, bit lines and memory cells. A row decoder selects the word lines in response to a row address. Further, the row address decoder selects the redundant word line when a replacement signal is received. A column decoder selects the bit lines in response to a column address. A row address redundancy circuit stores a redundant row address. The row address redundancy circuit provides the replacement signal when the redundant row address corresponds to the received address. The mode setting circuit receives a mode signal having a normal mode and a test mode. The mode setting circuit outputs the replacement signal to the row decoder when the mode signal is in the normal mode, and prohibits an output of the replacement signal.

Abstract: An apparatus for detecting a defect of a data transfer line in a semiconductor memory device, including a data transfer unit for transferring data between a local I/O line and a global I/O line; a data transfer controller for controlling the data transfer unit by generating a read signal, a write signal, and a local I/O line reset signal; a test mode controller for preventing an activation of the read signal, a column select signal and the local I/O line reset signal based on a test mode signal; a first temporary data storage for storing data of the global I/O line; and a second temporary data storage for storing data of the local I/O line.

Abstract: A write circuit of a semiconductor memory device includes a global data input/output (I/O) line; an amplifying block for receiving and amplifying write data and transmitting the amplified write data as global data onto the global data I/O line; and a control block for comparing the write data with the global data to thereby disable the amplifying block when the write data and the global data have substantially the same data value.

Abstract: A write circuit of a semiconductor memory device includes a global data input/output (I/O) line; an amplifying block for receiving and amplifying write data and transmitting the amplified write data as global data onto the global data I/O line; and a control block for comparing the write data with the global data to thereby disable the amplifying block when the write data and the global data have substantially the same data value.

Abstract: A memory includes at least one memory segment that includes an array of memory cells arranged in a plurality of columns, each of the plurality of columns having a corresponding bitline pair. An address decoder includes a row decoder and a column decoder that addresses a selected one of the array of memory cells in a selected one of the plurality of columns in response to a memory address. A sense amplifier generates a data output by sensing a differential voltage from the corresponding bitline pair of the selected one of the plurality of columns in response to a sense amp enable signal. A sense amp enable signal generator generates the sense amp enable signal with adjustable timing, based on sense amp feedback signals.

Abstract: Methods and apparatus to control voltage output of a write assist circuit are disclosed. An example method includes regulating pull down voltage from a write assist circuit having a write assist capacitor coupled to a discharge node coupled to a bit line. The write assist circuit further includes a transistor to receive an enable signal to couple the bit line to a low voltage rail. A voltage source is provided to charge the capacitor. The voltage produced by the voltage source is limited to limit the pull down voltage at the discharge node from the write assist capacitor.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.

Abstract: Systems and methods for reducing instability and writability problems arising from relative variations between a memory cell voltage (Vcell) and a logic voltage (Vdd) by inhibiting assertion of word line signals that enable accesses to the memory cells when the voltages are not within an acceptable operating range. One embodiment comprises a system having a critical condition detector configured to monitor the voltages and to determine whether the voltages are within an acceptable range. When the voltages are not within the acceptable range, the system inhibits assertion of the word lines to the memory cells. Memory accesses which fail because of the inhibited word line signals are retried by a memory controller when the critical conditions that caused the signals to be inhibited no longer exist.

Abstract: The present invention provides a power supply control circuit and a control method thereof, capable of securing an accurate operation of a GIO in a burst data transmission having a high compression rate. The power supply control circuit of a semiconductor memory device includes: a counter which is reset in response to a read command signal or a write command signal to count an input clock and then, to output a counting completion signal; and a power supply enable signal generator enabled in response to the read command signal or the write command signal and disabled in response to the counting completion signal, for generating a power supply enable signal.

Abstract: A current reduction circuit of a semiconductor device is disclosed which includes an enabling signal generator which outputs a predetermined enabling signal in association with a cell block in which a bridge has been formed between a word line and a bit line, and an isolation controller which is enabled in response to the enabling signal, and outputs a control signal to periodically isolate the bridge-formed cell block from a sense amplifier array for a predetermined period in a standby mode in response to a periodic signal enabled at intervals of a predetermined time.

Abstract: A storage device is capable of sequentially inputting a command, which includes address information and attached information, from an information processor through an input/output unit. The storage device includes a storage unit for storing data; an extractor for extracting the address information and the attached information from an input command inputted through the input/output unit; a generator for, in response to input of the input command, generating transition information that transitions according to rules using an initial value; a comparator for determining whether the attached information and the transition information agree with each other; and an output controller for, only when the attached information and the transition information agree with each other, outputting storage data out of the data, which corresponds to the address information extracted by the extractor, through the input/output unit.

Abstract: A method for programming a flash memory device which includes a plurality of memory cells arranged in rows and columns. The method includes programming selected memory cells from among the plurality of memory cells according to loaded data bits. Data bits are read from the programmed selected memory cells. It is determined whether each of the programmed memory cells has been successfully programmed based on the results of the reading step. The programming of memory cells that have been determined to have been successfully programmed are inhibited. The programming, reading, determining and inhibiting steps are repeated until each of the selected memory cells has been determined to have been successfully programmed. A memory cell that has been previously determined to have been successfully programmed and inhibited is uninhibited and subsequently re-programmed when it is determined that the previously inhibited memory cell is no longer successfully programmed.

Abstract: A non-volatile semiconductor memory device includes a memory cell array and an operation control circuit. The memory cell array includes a plurality of non-volatile memory cells that are electrically rewritable. The operation control circuit controls an operation of the memory cell array in accordance with an external instruction. The operation control circuit includes a flag circuit and an erase prohibition circuit. The flag circuit is set when erase incompletion is detected from any of the memory cells by an erase verify operation of the memory cell array. The erase prohibition circuit prohibits an erase operation to the memory cell array irrespective of the external instruction when the flag circuit is in a reset state.

Abstract: In a nonvolatile semiconductor memory device according to the present invention, a password protection function is enabled or disabled based on a first specified value M and a second state specified value P such that when both of the first specified value M and the second state specified value P are in a set state, the password protection function is enabled and when at least the second specified value P is in a reset state, the password protection function is disabled, and the first state specified value M maintains a previous state and the second state specified value P follows the state of the first state specified value M in response to a reset operation, and the cancel operation to shift the second state specified value P to the reset state can be performed only when the password is inputted correctly.

Abstract: A write circuit of a semiconductor memory device includes a global data input/output (I/O) line; an amplifying block for receiving and amplifying write data and transmitting the amplified write data as global data onto the global data I/O line; and a control block for comparing the write data with the global data to thereby disable the amplifying block when the write data and the global data have substantially the same data value.

Abstract: A nonvolatile semiconductor memory device includes a nonvolatile storage element to which data is inhibited from being rewritten, a read operation control circuit which captures a read operation instruction signal in synchronization with an external input clock, and a write operation control circuit to which a write operation instruction signal is input asynchronously with the external input clock. The read operation instruction signal gives an instruction to start a read operation to read data out of the nonvolatile storage element, and the write operation instruction signal gives an instruction to start a write operation to write data to the nonvolatile storage element. The device further includes a reset circuit which resets an operation of the read operation control circuit upon receiving the write operation instruction signal.

Abstract: Disclosed herein is a word line driving circuit in which sub-word lines are prevented from floating by using a sub-word line driver having two transistors. A plurality of sub-word line drivers is connected to one main word line. Each of the plurality of the sub-word lines includes a PMOS transistor and a NMOS transistor serially connected between a sub-word line driving voltage FX and a ground voltage. A floating prevention unit selects the main word line to a level of a threshold voltage using a driving signal having the level of the threshold voltage, thus preventing sub-word lines of a sub-word line driver, where the sub-word line driving voltage FX is off, from floating.

Abstract: An integrated cell for extracting a binary value based on a value difference between two resistors values, including connection circuitry for a binary reading of the sign of the difference between the resistors, and connection circuitry for a modification of the value of one of the resistors to make the sign of the difference invariable.

Abstract: An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location address enable signal, enabling one of a decoder and a redundant decoder in response to the match signal, wherein the decoder is operable to generate a location select signal for selecting a first location, the decoder being responsive to the pre-decoded location address signal, and wherein the redundant decoder is operable to generate a redundant location select signal for selecting a second location, the redundant decoder being responsive to the redundant location address enable signal, and terminating one of the generation of a location select signal and the generation of a redundant location select signal in response to a precharge signal.

Abstract: A memory includes at least two memory banks, each memory bank including an array of memory cells including rows and columns. The memory includes a directed auto-refresh memory bank selection circuit configured to simultaneously select a first of the at least two memory banks for a read or write operation and a second of the at least two memory banks for a directed auto-refresh.

Abstract: A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low and isolating the adjacent memory section, a timing circuit triggers a wordline decoder to activate a select wordline. The timing circuit prevents activation of the wordline decoder until the isolation signal is received.

Abstract: A computer system prevents an illegal program transmitted from an external communication device to a computer system such as IC cards and stored therein from being executed. The system comprises a CPU, a communication circuit, a first memory area storing a first and second computer program, a second memory area including storage areas for the first computer program, for data received by the communication circuit, for data used in program execution of the CPU. When a program to be executed by the CPU is the first computer program, if the program code is stored in the first memory area or a storage area for the first computer program in the second memory area, the program is allowed to be executed, and if the program code is stored in the second memory area other than the storage area for the first computer program, the program is not allowed to be executed.

Abstract: A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief information storing section). The shift register circuits are connected in series so as to successively transfer data. A test circuit tests the redundant memory, and serially outputs relief information for relieving a defective cell. The relief processing section stores the relief information into the shift register circuits using a data transfer operation thereof.

Abstract: Non-volatile storage elements are programmed using a series of voltage waveforms, where each waveform includes different portions with different amplitudes. For example, the amplitudes can vary as a decreasing staircase or ramp. Storage elements which are to be programmed to the highest level are programmed using the entire waveform, while storage elements which are to be programmed to intermediate and lower levels are programmed using different portions of the waveform. For example, the storage elements to be programmed to the intermediate level are programmed using the last two-thirds of each waveform, while the storage elements to be programmed to the lower level are programmed using the last one-third of each waveform. For these storage elements, programming is inhibited for a portion of the waveform by applying an inhibit voltage to an associated bit line. Higher programming speeds and narrower threshold voltage distributions can be achieved.

Abstract: The non-volatile semiconductor storage device 101 includes the specific command Enable/Disable signal lines 120 connected to the command decoder 108. The specific command Enable/Disable signals are externally inputted to the command decoder 108 through the signal lines 120. Thereby, when the device 101 is initialized, the command decoder 108 enables the specific command and the device 101 can shift to a mode corresponding to the specific command. On the other hand, the command decoder 108 can disable the specific command, for example, when a user uses the device 101, thereby preventing the specific command from being executed even when the specific command is erroneously issued.

Abstract: A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.