Abstract: A semiconductor memory device includes a first bit line to which a first memory cell is connected, and a second bit line to which a second memory cell is connected, the second bit line being complementary to the first bit line, a sense amplifier that includes a first transistor and a second transistor connected in series between the first bit line and the second bit line, the sense amplifier including a first node between the first transistor and the second transistor, a gate of the first transistor being connected to the second bit line, and a gate of the second transistor being connected to the first bit line, and a voltage providing unit that provides a first voltage to the first node during presensing, and provides a second voltage, different from the first voltage, to the first node during main sensing.

Abstract: A sensing circuit (100) for sensing the content of a memory cell (101), wherein the sensing circuit comprises a sense node (103) connectable to the memory cell (101) so that a signal indicative of the content of the memory cell (101) is providable to the sense node (103). The sensing circuit (100) further comprises a logic gate (102) having a first input, a second input and an output, wherein a reference signal (105) is providable to the first input and wherein the sense node (103) is coupled to the second input. The sensing circuit (100) further comprises a feedback loop (104) for coupling the output of the logic gate (102) to the second input of the logic gate (102) so that, during sensing the content of the memory cell (101), an electrical potential at the sense node (103) is used to make a decision but after a result is obtained, the memory and sense amplifier combination are configured so that the result is held indefinitely and so that no static current continues to flow.

Abstract: According to one embodiment, a semiconductor storage device includes first cells, first bit and first word, and first sense. The first cells are capable of holding 2-level or higher-level data. The first bit and first word are capable of selecting the first cells. The first sense detects a first current. The first sense includes a first supply unit, a first accumulation unit, a detector, and a counter. The first supply unit supplies a second current when the data is read. The first accumulation unit accumulates an amount of charge. The detector detects the potential the amount of charge. The counter counts output from the detector. The counter includes a second supply unit, a second accumulation unit, and a sensing unit. The second supply unit charges a first node. The second accumulation unit accumulates a charge. The sensing unit detects the amount of charge of the second accumulation unit.

Abstract: A semiconductor memory device comprises a plurality of memory cell mats, a plurality of sub-word driver regions and a plurality of sense amplifier regions, a plurality of intersection regions, a sub-amplifier, and a start signal (a control signal) supply circuit (a sub-amplifier control circuit). A plurality of sub-word driver regions and a plurality of sense amplifier regions are disposed adjacent to the plurality of memory cell mats. A plurality of intersection regions are intersection regions between the plurality of sub-word driver regions and the plurality of sense amplifier regions. The sub-amplifier is disposed in a first intersection region among the plurality of intersection regions. The start signal supply circuit is disposed in a second intersection region among the plurality of intersection regions, and supplies a start signal (a control signal) of the sub-amplifier to the sub-amplifier based on a sub-amplifier timing signal supplied from the extending direction of the sub-word driver region.

Abstract: A semiconductor device includes the following elements. A sense amplifier amplifies signal on a bit line. A column switch is between the bit line and a local input-output line. A sub-amplifier amplifies signal on the local input-output line. A write switch is between the local input-output line and a main input-output line. A write amplifier amplifies write data and supplies the amplified write data to the main input-output line when data write operation is performed. A test circuit activates the sense amplifier while the test circuit deactivating the sub-amplifier and the write amplifier when a data read operation is performed in test mode. The test circuit places the column switch and the write switch in conductive state.

Abstract: Memories, systems, and methods for repairing are provided. A memory with extra digit lines in end arrays with an open digit architecture, which can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are connected to an end array with an open digit architecture such that each sense amplifier corresponds to a group of four adjacent digit lines. Two digit lines of the group connect to two open digit sense amplifiers and the other two digit lines connect to the corresponding folded digit sense amplifier. To repair memories including folded digit end arrays, a row in a core array that includes a replaceable IO is activated and a row in an end array is activated. The repair cells in the end array can be sensed by the folded digit sense amplifiers to generate a replacement IO, which is selected rather than the replaceable IO.

Abstract: The invention relates to a device for testing an integrated circuit. The device comprises a plate for receiving and subjecting the integrated circuit to a test. The plate comprises a component for powering and operating the integrated circuit and another component for measuring the operation of the integrated circuit during the test. The device also comprises an irradiation device for subjecting the circuit to a proton bombardment and a mask with a variable thickness provided between a bombardment access region on the integrated circuit and an established zone of the integrated circuit.

Abstract: Herein, a voltage sensing circuit, which is capable of controlling a pumping voltage to be stably generated in a low voltage environment, is provided. The voltage sensing circuit includes a current mirror having first and second terminals, a first switching element configured to control current on the first terminal of the current mirror by a reference voltage, a second switching element configured to control current from the second terminal of the current mirror in response to a pumping voltage, and a third switching element configured to control current sources of the first and second switching elements to receive a negative voltage.

Abstract: A circuit comprises a control line and a two terminal semiconductor device having first and second terminals. The first terminal is coupled to a signal line, and the second terminal is coupled to the control line. The two terminal semiconductor device is adapted to have a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and to have a smaller capacitance when a voltage on the first terminal relative to the second terminal is below the threshold voltage. The control line is coupled to a control signal and the signal line is coupled to a signal and is output of the circuit. A signal is placed on the signal line and voltage on the control line is modified (e.g., raised in the case of n-type devices, or lowered for a p-type devices). When the signal falls below the threshold voltage, the two terminal semiconductor device acts as a very small capacitor and the output of the circuit will be a small value.

Abstract: A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias compensation unit. The sensing unit includes a sense amplifier, a latch circuit, a first precharged bit line, and a second precharged bit line. The equalizing unit is electrically connected to the first and the second precharged bit line for regulating a voltage of the first precharged bit line and a voltage of the second precharged bit line to the same electric potential. The bias compensation unit is electrically connected to the sense amplifier for compensating an input offset voltage of the current-sense amplifier.

Abstract: A semiconductor memory device can include a first driver configured to generate a pair of first sense amplifier driving signals having an activation period at a predetermined level during command execution; and a second driver that can be configured to generate a pair of second sense amplifier driving signals for increasing a driving strength of a pair of sense amplifiers when logic values of a pair of bit lines are constant during the command execution and decreasing the driving strength of the pair of sense amplifiers when the logic values of the pair of bit lines change.

Abstract: According to one embodiment, a differential circuit receives, as differential inputs, a readout signal read out from a semiconductor storage element and a reference voltage. An equalizing circuit controls, taking into account a state of a past input signal output from the differential circuit, the potential of the present differential signal output from the differential circuit. A sense amplifier detects a state of the differential signal output from the equalizing circuit. A state holding circuit holds a past state of the differential signal detected by the sense amplifier and supplies the state to the equalizing circuit.

Abstract: Disclosed is a non-volatile semiconductor memory circuit with an improved resistance spread characteristic distinguishing set data and reset data. The non-volatile semiconductor memory circuit includes a memory cell array, and a read/write circuit block configured to differentiate the current drivability based on the mode of operation, wherein the current drivability is provided in response to a bias signal based on set or reset state of data.

Abstract: A semiconductor device which has a sense amplifier and is supplied with an external power supply voltage includes a drive signal line connected to the sense amplifier, a step up circuit generating a first voltage from the external power supply voltage, the first voltage being higher than the external power supply voltage, and a step down circuit lowering the external power supply voltage into a second voltage. For enabling the sense amplifier to perform sensing operation in a normal mode involving external access, the first voltage is applied to the drive signal line in an initial stage of the sensing operation, and thereafter the second voltage is applied to the drive signal line. In a refresh mode not involving external access, the step up circuit is shut down, and the second voltage is applied to the drive signal line from the initial stage of the sensing operation.

Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.

Abstract: A semiconductor memory device includes a plurality of memory banks each having a plurality of memory cell arrays, a plurality of sense amplification units corresponding to the memory banks, configured to sense data corresponding to a selected memory cell to amplify the sensed data, and a common delay unit configured to delay a plurality of respective bank active signals activated in correspondence with the memory banks by a predetermined time to generate an operation control signal for controlling the sense amplification units.

Abstract: According to one embodiment, a semiconductor storage device includes cells, and a sense amplifier. Each of the cells is connected to a bit line. The sense amplifier reads out data. The sense amplifier includes a first transistor to third transistor, and a switch. The first transistor has one end of a current path, the other end, and a gate. The second transistor has one end, and the other end. The second transistor has one of a first and a second supply ability. The third transistor has one end, and the other end. The third transistor has one of a third and a fourth supply ability. The switch grounds the second and the third transistors. The sense amplifier turns off the first transistor after transferring the data to an outside, and supplies the second signal to the switch to set gates of the second transistor and third transistor to ground.

Abstract: Embodiments of the present disclosure use one or more gain stages to generate an output voltage representing whether a resistive memory element of a data cell stores a high data value or a low data value. In a particular embodiment, an apparatus includes a sensing circuit. The sensing circuit includes a first amplifier stage that is configured to convert a first current through a first resistive memory element of a memory cell into a first single-ended output voltage. A second amplifier stage is configured to amplify the first single-ended output voltage of the first amplifier stage to produce a second single-ended output voltage.

Abstract: A data sensing method for sensing storage data stored in a memory cell includes the steps of: biasing a sensing node and a reference node to a first voltage in response to a first control signal; discharging the sensing node and the reference node via the memory cell and a reference memory cell, respectively; enabling a latch circuit to amplify a voltage difference between the sensing node and the reference node.

Abstract: Some embodiments regard a circuit comprising a memory cell, a first data line, a second data line, a sensing circuit coupled to the first data line and the second data line, a node selectively coupled to at least three voltage sources via at least three respective switches, a fourth switch, and a fifth switch. A first voltage source is configured to supply a retention voltage to the node via a first switch. A second voltage source is configured to supply a ground reference voltage to the node via a second switch, and a third voltage source is configured to supply a reference voltage to the node via a third switch. The fourth switch and fifth switch are configured to receive a respective first control signal and second control signal and to pass a voltage at the node to the respective first data line and second data line.

Abstract: A memory cell array includes a memory cell comprising a ferroelectric capacitor and a transistor arranged therein. A plate line applies a drive voltage to one end of the ferroelectric capacitor. A bit line reads data stored in the memory cell from the other end of the ferroelectric capacitor. A sense amplifier circuit detects and amplifies a signal read to the bit line from the ferroelectric capacitor. A bit line voltage control circuit performs control of changing a voltage of the bit line to which the signal is read, thereby pulling up a potential difference between the plate line and the bit line, prior to operation of the sense amplifier circuit for data read. The bit line voltage control circuit varies a range of variation of the voltage of the bit line depending on ambient temperature.

Abstract: Method and device for controlling a memory access and correspondingly configured semiconductor memory A method and a device for controlling a memory access of a memory comprising memory cells are described. A completion of the memory access is determined by means of at least one dummy bit line. The at least one dummy bit line is connected to a plurality of memory cells of the memory cells of the memory such that a content of the at least one memory cell can be read out via the at least one dummy bit line. The at least one memory cell can be set to a predetermined potential. Each of said plurality of memory cells is connected to the at least one dummy bit line and to at least one dummy word line such that each of said plurality of memory cells can be set to the predetermined potential by means of the at least one dummy bit line and by means of the at least one dummy word line.

Abstract: In one embodiment, a semiconductor storage device includes a memory cell, a sense amplifier, a bit line, a pre-charge circuit, and a power-supply-voltage switching circuit. The memory cell is configured to store data. The sense amplifier is configured to amplify a signal from the memory cell. The bit line is configured to transmit the signal from the memory cell to the sense amplifier. The pre-charge circuit is configured to pre-charge the bit line. The power-supply-voltage switching circuit is configured to switch a voltage of a power supply and to actuate the sense amplifier after the bit line is pre-charged by the pre-charge circuit, wherein the power-supply-voltage switching circuit is configured to switch the voltage of the power supply to be larger than a voltage during the pre-charge by the pre-charge circuit.

Abstract: A semiconductor memory device includes a cell array including a plurality of unit cells, a first amplification circuit amplifying an input signal received from at least one unit cell among the unit cells, a signal transmission unit to transmit the signal to the first amplification circuit in response to a selection signal, first amplification control circuit to output a first amplification control signal controlling an amplification operation of the first amplification circuit, a second amplification circuit to amplify an output signal of the first amplification circuit, a second amplification control circuit to output a second amplification control signal controlling an amplification operation of the second amplification circuit, and a voltage adjustment circuit to adjust an internal voltage of the first amplification circuit in response to a voltage adjustment signal before the first and second amplification circuits perform the amplification operation.

Abstract: A sense amplifier comprises a sense node, a reference node, a memory input stage circuit, a reference input stage circuit, an output stage circuit, and a shielding circuit. The memory input stage circuit comprises first input node for maintaining a first sense voltage established by a cell current and establishes a second sense voltage on the sense node in response to the first sense voltage. The reference input stage circuit comprises an output node and a second input node, which is for maintaining a first reference voltage established by the reference current and establishes a second reference voltage on the reference node in response to the first reference voltage. The output stage circuit obtains a sense result in response to the second reference voltage and the second sense voltage. The first shielding circuit shields the output node from being interfered with the second reference voltage on the reference node.

Abstract: A voltage sensing circuit, which is capable of controlling a pumping voltage to be stably generated in a low voltage environment, is provided. The voltage sensing circuit includes a current mirror having first and second terminals, a first switching element configured to control current on the first terminal of the current mirror by a reference voltage, a second switching element configured to control current from the second terminal of the current mirror in response to a pumping voltage, and a third switching element configured to control current sources of the first and second switching elements to receive a negative voltage.

Abstract: A row decoder is disposed on a side of a memory cell array in a column direction and supplies one of word lines with a first drive signal for selecting one of memory cells. A dummy word line is formed extending in the column direction. A dummy bit line is formed extending in a row direction. At least one of the dummy word line and the dummy bit line is disposed outside of the memory cell array. The row decoder outputs a second drive signal toward a sense amplifier circuit via the dummy bit line and the dummy word line.

Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

Abstract: A semiconductor device includes a bit line connected to a plurality of memory cells in a memory block and a sense amplifier having a first node connected to the bit line and a second node, which is not connected to any bit line. The second node has a capacitive load less than that of the bit line. The sense amplifier amplifies a first data using a voltage difference between the first node and the second node caused by a charge sharing operation, and a second data using a capacitive mismatch between the first node and the second node.

Abstract: For example, four driver transistors are arranged in wells so as to adjoin both sides of each of two element isolation regions. Two pairs of cross-coupled sense transistors are arranged in the wells at positions farther from the element isolation regions than the driver transistors are. Such an arrangement provides more than a certain distance between the sense transistors and the respective corresponding element isolation regions. This reduces the effect of a phenomenon that threshold of a transistor varies according to a distance from an element isolation region. As a result, it is possible to exactly match the characteristics of each pair of cross-coupled transistors.

Abstract: A high speed linear differential amplifier (HSLDA) having automatic gain adjustment to maximize linearity regardless of manufacturing process, changes in temperature, or swing width change of the input signal. The HSLDA comprises a differential amplifier, and a control signal generator including a replica differential amplifier, a reference voltage generator, and a comparator. The comparator outputs a control signal that automatically adjusts the gain of the high speed linear differential amplifier and of the replica differential amplifier. The replica differential amplifier receives predetermined complementary voltages as input signals and outputs a replica output signal to the comparator. The reference voltage generator outputs a voltage to the comparator at which linearity of the output signal of the differential amplifier is maximized. The control signal equalizes the voltage level of the replica output signal and the reference voltage, and controls the gain of the differential amplifier.

Abstract: Embedded dynamic random access memory (eDRAM) sense amplifier circuitry in which a bit line connected to each of a first plurality of eDRAM cells is controlled by cell control lines tied to each of the cells. During a READ operation the eDRAM cell releases its charge indicating its digital state. The digital charge propagates through the eDRAM sense amplifier circuitry to a mid-rail amplifier inverter circuit which amplifies the charge and provides it to a latch circuit. The latch circuit, in turn, inverts the charge to correctly represent at its output the logical value stored in the eDRAM cell being read, and returns the charge through the eDRAM sense amplifier circuitry to replenish the eDRAM cell.

Abstract: A balanced differential amplifier sense amplifier senses the voltage level in a selected single bit line memory cell. The output of the selected single bit-line memory cell is connected to one input of the balanced differential sense amplifier while the other input receives a reference voltage provided by a corresponding single bit-line memory cell from a complementary memory bank. A supporting voltage is added-to/subtracted-from the reference voltage by providing a “bump” or “dip” mechanism or by utilizing a charge-sharing structure, in order to compensate for the variation in the sensed bit-line voltage over the duration of the sensing interval as well as for the disparity in voltage level from cell to cell.

Abstract: A semiconductor memory device, having a 6F2 open bit line structure, connects each bit line of a bit line pair to a respective bit line of a neighboring bit line pair for a precharge operation so that a layout size of the semiconductor memory device decreases. Plural first precharge units each precharge one bit line of a first bit line pair and one bit line of a second bit line pair in response to a bit line equalizing signal. Plural sense amplifiers each sense a data bit supplied to a respective one of the first and second bit line pairs and amplify sensed data.

Abstract: The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.

Abstract: A semiconductor integrated circuit includes a self-test circuit, wherein, when a operation mode of the self-test circuit has been switched from a low-speed operation mode to a high-speed operation mode, processing is performed in the high-speed operation mode during a given time period, and the processing result is invalidated based on a control signal.

Abstract: Memory storage requirements for digital signal processing operations, for example, motion-compensated video scan rate conversion, that produce intermediate output data, which is then used as an input to the operation, are reduced by reordering operations and organizing memory allocations in a special manner to allow intermediate output at a particular execution time, to substantially share the same memory space as the intermediate output of a previous execution time. Such a reduction in the amount of memory required for processing operations advantageously reduces cost and power consumption.

Abstract: A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line.

Abstract: A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.

Abstract: Characteristics of both a memory cell and a peripheral circuit are degraded due to random variations, and a defective characteristic occurs in a combination of components having a substantially worst characteristic at a macro level. To solve this problem, a selector is provided between the memory cell and the peripheral circuit so that a positive phase and a negative phase of bit lines are switched at a portion where the defective characteristic occurs. Alternatively, the combination of a bit line and a sense amplifier is switched between adjacent data input/output sections, for example. In other words, the defective characteristic is repaired or corrected by canceling the combination of worst components.

Abstract: A memory device, and method of operation of such a device, are provided. The memory device comprises an array of memory cells arranged in a plurality of rows and a plurality of columns, at least one bit line being associated with each column. Column multiplexer circuitry is coupled to the plurality of columns, for inputting write data into a selected column during a write operation and for outputting an indication of read data sensed from a selected column during a read operation. The column multiplexer circuitry comprises a single pass gate transistor per bit line, and latch circuitry is then used to detect the read data from the indication of read data output by the column multiplexer circuitry during the read operation, and to store that detected read data. Such an approach provides a particularly area efficient construction for the column multiplexer circuitry whilst enabling correct evaluation of the read data held in the addressed memory cell.

Abstract: A core voltage discharger is capable of adjusting an amount of a current discharged according to temperature. The discharger for decreasing a level of a predetermined voltage receives temperature information from an on die thermal sensor and discharges a different amount of current in response to the temperature information.

Abstract: A semiconductor memory device simultaneously selects an object cell and a counter cell which connect with a common bit line, simultaneously activates sub-word lines of the object cell and the counter cell after predetermined levels are written in the object cell and the counter cell, simultaneously read data of the object cell and the counter cell from the common bit line, and hence, determines whether the object cell is normal or defective, based on a voltage level of the common bit line. Thereby, the defective cell in the semiconductor memory device can be reliably detected.

Abstract: A semiconductor memory device includes a memory block having first and second word lines extending in a first direction and bit lines extending in a perpendicular second direction; a first driver region at a side of the memory block in the first direction driving the first word lines; a second driver region at another side of the memory block in the first direction driving the second word lines; a sensing region at a side of the memory block in the second direction controlling the bit lines responsive to signals from drive lines; a first conjunction region at an intersection of the first driver and sensing regions including a first driver driving the drive lines responsive to signals from control lines; and a second conjunction region at an intersection of the second driver and sensing regions, including a second driver driving the drive lines responsive to signals from the control lines.

Abstract: A differential sense amplifier can perform data sensing using a very low supply voltage.

Abstract: A semiconductor memory device comprises: a memory cell array including a plurality of word lines, a plurality of bit line pairs containing a first bit line and a second bit line, and a plurality of memory cells; a plurality of replica bit lines formed in the same manner as the first and second bit lines; a write buffer circuit operative to drive the first or second bit line to the ground voltage; a replica write buffer circuit operative to drive the replica bit lines to the ground voltage; and a boot strap circuit operative to drive the first or second bit line currently driven to the ground voltage further to a negative potential at a timing when the potential on the replica bit lines reaches a certain value.

Abstract: The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.

Abstract: A semiconductor memory device includes a sense amplifier that compares intensities of currents flowing through a first node and a second node with each other, a first MOSFET having a drain terminal connected with the first node, a second MOSFET having a drain terminal connected with the second node, a memory cell connected with a source terminal of the first MOSFET, and a reference cell. The semiconductor memory device further includes a connection control circuit that connects a source terminal of the second MOSFET with the reference cell at the time of a regular operation and connects the source terminal of the second MOSFET with a reference voltage terminal at the time of a test operation.

Abstract: A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

Abstract: A semiconductor memory device can include a first driver configured to generate a pair of first sense amplifier driving signals having an activation period at a predetermined level during command execution; and a second driver that can be configured to generate a pair of second sense amplifier driving signals for increasing a driving strength of a pair of sense amplifiers when logic values of a pair of bit lines are constant during the command execution and decreasing the driving strength of the pair of sense amplifiers when the logic values of the pair of bit lines change.