Abstract: Deterioration of holding characteristics due to fluctuations in power supply voltage VDD is prevented. During writing or reading in one of memory circuits, a pair of bit lines in the other memory circuit is controlled to a dummy-bit-line voltage ranging from a ground voltage to ½×VDD. In a subsequent precharge period, a pair of bit lines in one of the memory circuits and the pair of bit lines in the other memory circuit are coupled to a reference voltage generating circuit.

Abstract: A nonvolatile semiconductor device which can be driven at low voltage is provided. A nonvolatile semiconductor device with low power consumption is provided. A Schmitt trigger NAND circuit and a Schmitt trigger inverter are included. Data is held in a period when the supply of power supply voltage is continued, and a potential corresponding to the data is stored at a node electrically connected to a capacitor before a period when the supply of power supply voltage is stopped. By utilizing a change in channel resistance of a transistor whose gate is connected to the node, the data is restored in response to the restart of the supply of power supply voltage.

Abstract: Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of a cell with a floating-gate transistor in a non-conductive state is measured by periodically clocking a counter following initiation of a read cycle; a latch stores the counter contents upon the cell under test making a transition due to leakage of the floating-gate transistor. Logic for testing a group of cells in parallel is disclosed. In some embodiments, the read margin of a cell in which the floating-gate transistor is set to a conductive state is measured by repeatedly reading the cell, with the output developing a voltage corresponding to the duty cycle of the output of the read circuit.

Abstract: An electronic device comprising a semiconductor memory unit that includes a first vertical electrode; a first variable resistance layer surrounding the first vertical electrode; a second vertical electrode surrounding the first variable resistance; a second variable resistance layer surrounding the second vertical electrode; and a plurality of horizontal electrodes contacted with an outer side of the second variable resistance layer, wherein the plurality of horizontal electrodes are spaced apart from each other in a vertical direction.

Abstract: Disclosed herein is a semiconductor device comprising complementary pair of bit lines, memory cells connected to the bit lines, dummy cells having the same structure as the memory cells, a differential sense amplifier, an equalizing circuit equalizing potentials of the bit lines, and a control circuit. The memory cells are disconnected from the bit lines and the dummy cells are connected to the bit lines, and subsequently the bit lines are equalized by the equalizing circuit. When accessing a selected memory cell, the equalizing circuit is inactivated, a corresponding dummy cell is disconnected from the bit line, and subsequently the selected memory cell is connected to the bit line. Thereafter, the sense amplifier is activated so that potentials of the bit lines are amplified respectively.

Abstract: The present invention discloses a 3D-IC differential sensing and charge sharing scheme which includes a plurality of TSVs including a first TSV and a second TSV. A tracking circuit is coupled to the first TSV. A sensing circuit is coupled to the second TSV and the tracking circuit. A plurality of equaling circuits are provided and wherein each of equaling circuit is configured and electrically connected between adjacent two equaling circuits. A clamping circuit is coupled to the first TSV.

Abstract: Provided is a method for reading data from a variable resistance nonvolatile storage element, where the operation for reading data is less susceptible to a fluctuation phenomenon of resistance values in reading the data. The method includes: detecting a current value Iread that flows through the nonvolatile storage element that can be in a low resistance state RL and a high resistance state RH, with application of a fixed voltage; and determining that (i) the nonvolatile storage element is in a high resistance state when the current value Iread detected in the detecting is smaller than a current reference level Iref, and (ii) the nonvolatile storage element is in a low resistance state when the current value Iread detected in the detecting is larger than the reference level Iref, the current reference level Iref being defined by (IRL+IRH)/2<Iref<IRL.

Abstract: A memory includes a clock generator for providing a first clock signal responsive to a second clock signal and a feedback signal. A feedback loop provides the feedback signal and includes a tracking wordline, a tracking bitline, a tracking bit cell, and a tracking wordline driver for driving the tracking wordline responsive to the first clock signal. The memory includes a tracking wordline level tuner for reducing a voltage level of a tracking wordline signal on the tracking wordline responsive to a weak bit control signal.

Abstract: A sensing method of a current sensing amplifier is provided used for determining a storing state of a cell of a non-volatile memory device during a read cycle. After a sensing node and a reference node are adjusted to a constant voltage, the sensing node and the reference node are maintained in a floating state. Then, the sensing node is connected with a data line to receive a cell current from the cell, and the reference node is connected with a reference current source to receive a reference current from the reference current source. When a reference voltage of the reference node reaches a preset voltage, the storing state of the cell is determined according to a relationship between a sensing voltage of the sensing node and the preset voltage.

Abstract: A memory array includes a memory segment having at least one memory bank. The at least one memory bank includes an array of memory cells, and wherein at least two first read tracking cells are disposed in a read tracking column of the at least one memory bank. The memory array further includes a read tracking circuit coupled to the at least two first read tracking cells. Outputs of the at least two first read tracking cells are connected to a tracking bit connection line (TBCL). A tracking circuit connected to the TBCL is configured to output a tracking-cells output signal to generate a global tracking result signal to a memory control circuitry. The memory control circuitry is configured to reset a memory clock based on the global tracking result signal.

Abstract: A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises at least one dummy memory cell, a feedback-based controller having inputs coupled to respective internal nodes of the dummy memory cell, and write signal generation circuitry coupled to the feedback-based controller and configured to provide one or more write signals for controlling writing of data to portions of the memory array. The feedback-based controller generates a reset signal for application to a reset input of the write signal generation circuitry at least in part as a function of a logic level transition delay of a selected one of the first and second internal nodes of the dummy memory cell.

Abstract: Methods, memories and systems may include charging a sense node to a logic high voltage level, and supplying charge to a bit line and to a reference bit line for a precharge period that is based, at least in part, on a time for a voltage of the reference bit line to reach a reference voltage. A memory cell that is coupled to the bit line may be selected after the precharge period, and a clamp voltage may be set based, at least in part, on the voltage of the reference bit line. If a voltage level of the bit line is less than the clamp voltage level during a sense period, charge may be drained from the sense node, and a state of the memory cell may be determined based, at least in part, on a voltage level of the sense node near an end of the sense period.

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract: An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells.

Abstract: An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.

Abstract: An operating method of a variable resistance memory device including a pre-read step which may include the steps of: reading a first reference cell using a first reference voltage; reading a second reference cell using a second reference voltage; and setting a third reference voltage based on the first and second reference voltages; and a main read step of reading a selected memory cell using the third reference voltage.

Abstract: A high-voltage word-line driver circuit for a memory device uses cascode devices to prevent any single transistor of the driver circuit from having the full power supply voltage from which the word-line output signal is generated, from being applied across any single transistor of the word-line driver circuit. A pair of cascode devices are connected in series with the pull-down device of the input stage and a pull-up device of the input stage, and biased using reference voltages to control the maximum voltage drop across the pull-down device when the pull-down device is off and the pull-up device is active, and to control the maximum voltage drop across the pull-up device when the pull-down device is active. The output stage also includes cascode devices that protect the output pull-down and pull-up devices, and the reference voltages that bias the input and output cascode pairs may be the same reference voltages.

Abstract: A semiconductor memory apparatus may include a memory bank, row decoders, and an intersection region circuit. The row decoder may be configured to select a dummy block and a plurality of sub blocks based on row address signals, a bank select signal, and a dummy delayed bank select signal. The intersection region circuit may delay the bank select signal and may generate a delayed bank select signal and a dummy delayed bank select signal.

Abstract: A write tracking control circuit includes an input node, and a first transistor configured to pre-charge a word bit line connected to at least two memory cells. The write tracking control circuit further includes a second transistor configured to pre-charge a read bit line connected to the at least two memory cells. The write tracking control circuit further includes a first delay circuit between the input node and the first transistor, the first delay circuit configured to introduce a first delay time, wherein a gate of the first transistor is connected to the first delay circuit. The write tracking control circuit further includes a second delay circuit between the input node and the second transistor, the second delay circuit configured to introduce a second delay time different from the first delay time, wherein a gate of the second transistor is connected to the second delay circuit.

Abstract: In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed.

Abstract: Methods and apparatus for programming memory cells in a memory array are disclosed. A most recent programming time is determined, the most recent programming time being a time when a most recent programming operation was applied to a reference memory cell in the memory array. A programming signal is then applied to a target memory cell in the memory array, the programming signal having a programming parameter which depends at least in part on the most recent programming time.

Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

Abstract: A read time tracking mechanism (RTTM) for ensuring sufficient read time is provided. The read time tracking mechanism includes a read tracking circuit, which includes a tracking bit line (TBL) tracking circuit with one or more tracking cells, and a tracking word line (TWL). The RTTM also includes a sense amplifier enable (SAE) timing device configured to change the logic threshold of tracking WL (TWL) to delay the timing of signal change of TWL when necessary to ensure sufficient read time. The read time tracking mechanism is used to provide sufficient read time for memory arrays with various configurations, prepared under various process conditions, and operated under various voltages, and temperatures.

Abstract: A memory includes an array of active memory cells arranged in rows and columns, and at least one dummy memory cell column adjacent the array of active memory cells. A sensing circuit is coupled to the at least one dummy memory cell column to sense at least one variation associated with the at least one dummy memory cell column. An assist circuit is coupled to the array of active memory cells. An assist determination controller is coupled to the sensing circuit to store a look-up table of output assist values corresponding to different variations associated with the at least one dummy memory cell column, to determine an output assist value from the look-up table based upon the at least sensed variation, and to operate the assist circuit based upon the determined output assist value.

Abstract: A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell array and the tracking row, and a sense amplifier enable logic. The memory further includes a tracking bit line coupled to the tracking column and the sense amplifier enable logic, and a tracking word line coupled to the tracking row and the sense amplifier enable logic. The tracking circuit is configured to track a column time delay along the tracking column before a row time delay along the tracking row.

Abstract: A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier.

Abstract: A memory with extra digit lines in full size end arrays with an open digit architecture, which can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are connected to an end array with an open digit architecture such that each sense amplifier corresponds to a group of four digit lines. Two digit lines of the group connect to two open digit sense amplifiers and the other two digit lines connect to the corresponding folded digit sense amplifier. A repair method can be performed on memories including the end arrays with folded digit sense amplifiers. A row in a core array including a replaceable IO is activated and a row in an end array is activated. The repair cells in the end array can be sensed by the folded digit sense amplifiers to generate a replacement IO, which is selected rather than the replaceable IO.

Abstract: A semiconductor device includes a plurality of memory mats, each of which includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells that are arranged at intersections of the word lines and the bit lines, and a plurality of dummy word lines, each of which is sandwiched between two corresponding ones of the word lines; a main dummy word line to which the dummy word lines included in the memory mats are commonly electrically connected; and a dummy-word-line control circuit that detects an electric potential of the main dummy word line when a test signal is activated, and outputs an error signal when the electric potential exceeds a predetermined threshold value. According to the present invention, because an electric potential of each of the dummy word lines is directly detected, an address of the word line, which has a short circuit with the dummy word line, can be reliably detected in a short time.

Abstract: A sense amplifier comprises a sense amplifying unit configured to be connected to a bitline and a complimentary bitline of a memory device, to sense a voltage change of the bitline in response to first and second control signals, and to control voltages of a sensing bitline and a complimentary sensing bitline based on the sensed voltage change. It further comprises a first isolation switch configured to connect the bitline with the sensing bitline in response to an isolation signal, a second isolation switch configured to connect the complimentary bitline with the complimentary sensing bitline in response to the isolation signal, a first offset cancellation switch configured to connect the bitline with the sensing bitline in response to an offset cancellation signal, and a second offset cancellation switch configured to connect the complimentary bitline with the complimentary sensing bitline in response to the offset cancellation signal.

Abstract: Disclosed is a current sense amplifier suitable for a nonvolatile memory device such as a magnetic random access memory. In the current sense amplifier, a reference memory cell for sensing is implemented by a memory cell equal to a normal memory cell without fabricating different reference memory cells. The current sense amplifier is formed of first and second cross coupled differential amplifiers being covalent bonded. The current sense amplifier compares a current flowing to a sensing node of a memory cell directly with currents flowing to reference sensing nodes.

Abstract: A method of adjusting a threshold voltage of a ground selection transistor in a nonvolatile memory device includes providing a first voltage to a gate of a first ground selection transistor in a read operation and providing a second voltage to a gate of a second ground selection transistor in the read operation. The nonvolatile memory device includes at least one string, the string having string selection transistors, memory cells and the first and second ground selection transistors connected in series and stacked on a substrate.

Abstract: A memory macro includes a tracking circuit and a plurality of memory cells. The tracking circuit has tracking transistors configured to receive a tracking voltage value. Each memory cell of the plurality of memory cells has memory transistors configured to receive a cell voltage value different from the tracking voltage value. The tracking circuit is configured to generate a tracking signal based on which a reading signal of a memory cell of the plurality of memory cells is generated.

Abstract: A structure and method is described for an adaptive reference used in reading magnetic tunneling memory cells. A collection of magnetic tunneling memory cells are used to form a reference circuit and are coupled in parallel between circuit ground and a reference input to a sense amplifier. Each of the magnetic memory cells used to form the reference circuit are programmed to a magnetic parallel state or a magnetic anti-parallel state, wherein each different state produces a different resistance. By varying the number of parallel states in comparison to the anti-parallel states, where each of the two states produce a different resistance, the value of the reference circuit resistance can be adjusted to adapt to the resistance characteristics of a magnetic memory data cell to produce a more reliable read of the data programmed into the magnetic memory data cell.

Abstract: In-system repairing or configuring faulty memories after being used in a system. In one embodiment, a memory chip can include at least one OTP memory to store defective addresses that are to be repaired. The OTP memory can operate without requiring additional I/O pins or high voltage supplies for reading or programming. The memory chip can also include control logic to control reading or programming of the OTP memory as needed.

Abstract: Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is determined using differentiated timings of read outputs changing state, rather than differentiated values of read outputs. In some single-bit single-ended sensing embodiments, a reference, with resistance between the resistances corresponding to a pair of adjacent logical states, is stored in multiple reference cells; a “vote” unit emits a clock signal when a majority of the reference cell read outputs transition at the vote unit. Timing units produce different binary outputs depending on whether a data read output or the clock signal changes state first at the timing unit. Time-based decoding provides advantages including improved temperature and drift resilience, improved state discrimination, improved reliability of multibit PCM, and fast and reliable sensing.

Abstract: A method of writing to a magneto tunnel junction (MTJ) includes writing data to the MTJ, reading the written data using a first reference MTJ and reading the written data using a second reference MTJ. Based on the reading steps and the result of the comparing step, setting a select bit to select the proper reference for future reads.

Abstract: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.

Abstract: Systems, methods, and devices are disclosed, including an electronic device that includes a first data location, a quantizing circuit, and a reference current source, all coupled to an electrical conductor. The reference current source may include a current mirror with a side coupled to the electrical conductor and a second data location coupled to another side of the current mirror.

Abstract: The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T5, T6) for precharging the first and second bit lines during a precharge operation and for transferring the output provided by the sense circuit to a data line (LIO,/LIO) during a read operation.

Abstract: A memory includes memory cells each storing data according to a change in a resistance state, and reference cells referred to in order to detect data stored in the memory cells. Sense amplifiers compare reference data in the reference cells with data in the memory cells to detect the data in the memory cells. A counter counts a number NH of the memory cells having a resistance higher than a resistance of each reference cell or a number NL of the memory cells having a resistance lower than the resistance of each reference cell based on a result of detecting first logical data stored in the memory cells using each reference cell storing the first logical data. A determining part determines one of the reference cells as an optimum reference cell used in an actual data reading operation based on the number NH or NL for the reference cells.

Abstract: A semiconductor apparatus with an open bit line structure includes a memory bank including a plurality of memory cell blocks and dummy mats, in which a plurality of bit lines are formed, a bit line sense amplifier configured to be arranged between the plurality of memory cell blocks and the dummy mats, compare a voltage difference between a bit line and a complementary bit line, and amplify the difference, and a dummy word line driving unit configured to selectively activate a dummy word line of the dummy mat in response to a test mode.

Abstract: A semiconductor device includes a data memory cell for storing data; a reference data memory cell for storing reference data to be compared with the data; an inverted data memory cell for storing inverted data of the reference data; a sense amplifier unit; and a data output unit. In a first retrieving process, the sense amplifier unit differentially amplifies the data and the reference data, and adjusts an output thereof when a voltage difference between the data and the reference data becomes a predetermined retrievable voltage difference. In a second retrieving process, the sense amplifier unit differentially amplifies the data and the inverted data, and adjusts an output thereof when a voltage difference between the data and the inverted data becomes the predetermined retrievable voltage difference. The data output unit determines and outputs the data according to a result of the first retrieving process and the second retrieving process.

Abstract: The invention provides a flash memory apparatus including at least one flash memory array block and a sense amplifying module. The flash memory array block comprises N storage columns, N reference word-line cell units and a reference storage column, wherein N is a positive integer. Each of the reference word-line cell units disposed in each of the storage columns, wherein, the reference word-line cell units further coupled to a reference word line and a dummy word line. The reference storage column includes a plurality of reference bit-line cells, the reference word line and the dummy word line, one of the reference bit-line cells which coupled to the reference word line is coupled to a reference bit line. The sense amplifying module compares currents from one of the bit lines and the corresponding reference bit line to generate at least one sensing result.

Abstract: To produce a memory which resists ion or photon attack, a memory structure is chosen whose memory point behaves asymmetrically with regard to these attacks. It is shown that in this case, it is sufficient to have a reference cell for an identical and periodic storage structure in order to be able to correct all the memory cells assailed by an attack. An error correction efficiency of ½ is thus obtained, with a simple redundancy, whereas the conventional methods make provision, for the same result, to triple the storage, to obtain a less beneficial efficiency of ?.

Abstract: Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them.

Abstract: A memory includes an array of active memory cells arranged in rows and columns, and at least one dummy memory cell column adjacent the array of active memory cells. A sensing circuit is coupled to the at least one dummy memory cell column to sense at least one variation associated with the at least one dummy memory cell column. An assist circuit is coupled to the array of active memory cells. An assist determination controller is coupled to the sensing circuit to store a look-up table of output assist values corresponding to different variations associated with the at least one dummy memory cell column, to determine an output assist value from the look-up table based upon the at least sensed variation, and to operate the assist circuit based upon the determined output assist value.

Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.

Abstract: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a system for reading a memory cell includes a read path and a precharge path. The reference current is provided through the read path and is sampled via a sampling element in the read path. Subsequently, a current from the memory cell is provided through the same sampling element and read path. The output level is then determined by the cell current working against the sampled reference current.

Abstract: A memory device includes a memory array comprising a including of memory cells, and control circuitry coupled to the memory array. The control circuitry includes write signal generation circuitry configured to provide a write clock signal for controlling writing of data to portions of the memory array, with timing of the write clock signal being determined at least in part utilizing a parallel combination of two or more additional memory cells external to the memory array. The parallel combination of additional memory cells may comprise a mini-array that includes centrally-located active memory cells surrounded by dummy memory cells. In an arrangement in which the write signal generation circuitry includes a clock latch, the parallel combination of additional memory cells may be coupled between a clock output of the clock latch and a reset input of the clock latch.

Abstract: According to one embodiment, a semiconductor storage device includes cells, and a sense amplifier. Each of the cells is connected to a bit line. The sense amplifier reads out data. The sense amplifier includes a first transistor to third transistor, and a switch. The first transistor has one end of a current path, the other end, and a gate. The second transistor has one end, and the other end. The second transistor has one of a first and a second supply ability. The third transistor has one end, and the other end. The third transistor has one of a third and a fourth supply ability. The switch grounds the second and the third transistors. The sense amplifier turns off the first transistor after transferring the data to an outside, and supplies the second signal to the switch to set gates of the second transistor and third transistor to ground.