Abstract: High speed SRAM is realized such that a first dynamic circuit serves as a local sense amp for reading a memory cell through a lightly loaded local bit line, a second dynamic circuit serves as a segment sense amp for reading the local sense amp, and a tri-state inverter serves as an inverting amplifier of a global sense amp for reading the segment sense amp. When reading, a voltage difference in the local bit line is converted to a time difference for differentiating low data and high data by the sense amps for realizing fast access with dynamic operation. Furthermore, a buffered data path is used for achieving fast access and amplify transistor of the sense amps is composed of relatively long channel transistor for reducing turn-off current. Additionally, alternative circuits and memory cell structures for implementing the SRAM are described.

Abstract: A semiconductor memory apparatus includes: a bit line; a word line; a local bit line; a first switch unit provided between the local bit line and the bit; a memory cell connected to the bit line and the word line; a memory cell array including the memory cell; a first sense circuit connected to the bit line and configured to amplify a signal read out from the memory cell; and a second sense circuit connected to the local bit lines and configured to amplify a signal amplified by the first sense circuit, wherein the first switch unit disconnects the local bit line from the bit line when the first sense circuit amplifies the signal, and connects the local bit line to the bit line when the second sense circuit amplifies the signal amplified by the first sense circuit.

Abstract: A semiconductor memory device includes: a pre-amplifying unit configured to amplify a difference between an input signal and a reference signal to output a pre-output signal; a delaying unit configured to delay the input signal to output a delayed input signal; and a main amplifying unit configured to receive the pre-output signal and the delayed input signal as differential inputs to output an output signal.

Abstract: A resistance change memory includes two memory cell arrays each including a plurality of memory cells, the memory cells including variable resistive elements, two reference cell arrays provided to correspond to the two memory cell arrays, respectively, and each including a plurality of reference cells, the reference cells having a reference value, and a sense amplifier shared by the two memory cell arrays and detecting data in an accessed memory cell by use of a reference cell array corresponding to a second memory cell array different from a first memory cell array including the accessed memory cell. In reading the data, a particular reference cell in one reference cell array is always activated for an address space based on one memory cell array as a unit.

Abstract: A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line.

Abstract: A semiconductor memory device includes a one-transistor (1-T) field effect transistor (FET) type memory cell connected between a pair of bit lines, and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer. The device includes a plurality of word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a pair of clamp dummy lines arranged in the column direction, a pair of reference dummy lines arranged in the column direction, a cell array including the memory cell and formed in a region where the word line and the bit line are crossed, a dummy cell array including the memory cell and formed where the word line, the pair of claim dummy lines and the pair of reference dummy lines are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.

Abstract: Disclosed is a DRAM circuit that incorporates an improved reference cell, has half the capacitance of the memory cell, does not require a particular reference voltage, and can be formed using the same fabrication processes as the memory cell. This DRAM circuit comprises a memory cell with a single trench capacitor and a reference cell having two trench capacitors. The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor. Additionally, the reference cell trench capacitors have essentially the same structure as the memory cell trench capacitor so that they can be formed in conjunction with the memory cell trench capacitor. Also disclosed are a design structure for the above-described memory circuit and a method for forming the above-described memory circuit.

Abstract: A voltage detection circuit outputs a detection signal when an amount of charges read to one of a pair of bit lines reaches a predetermined amount. A mask circuit of a timing generator masks an output of a sense amplifier activation signal until the detection signal is output. A sense amplifier determines logics of data read to the bit lines from memory cells in synchronization with the sense amplifier activation signal. An operation of the sense amplifier is started after predetermined amounts of charges are read from the memory cells to the bit lines, that is, after the detection signal is output. Accordingly, even when a timing to output a timing signal becomes early due to a variance of manufacturing conditions of a semiconductor memory, data read from the memory cells can be latched correctly in the sense amplifier. As a result, malfunctions of the semiconductor memory can be prevented.

Abstract: A sense amplifier circuit for use in a semiconductor memory device has complemented logic states at opposite sides of the latch circuit in the sense amplifier circuit determinate all the time in operation. The sense amplifier circuit takes advantage of a current mirror circuit for ascending or descending a voltage level at the gate of a transistor by charge accumulation or charge dissipation, which turns on or off the transistor so as to control the logic states at opposite sides of the latch circuit in the sense amplifier circuit.

Abstract: Methods and circuit arrangements are provided for improving equalization of sense nodes of a sense amplifier in a semiconductor memory device. When a memory array segment on a side a sense amplifier has a bitline leakage anomaly for which the sense amplifier is to be isolated when that memory is in an unselected state, isolation of the sense amplifier from the memory array segment is delayed when transitioning from a selected state of the memory array segment to an unselected state of the memory array segment. The duration of the delay is sufficient to allow time for equalization of the sense nodes of the sense amplifier before isolating the sense amplifier from the memory array segment.

Abstract: There is provided a semiconductor memory device that includes: a plurality of memory mats each including a plurality of word lines, a plurality of bit lines, a plurality of memory cells each located at an intersection between the word line and the bit line, and at least one dummy word line not having connection to a dummy cell; a plurality of sense amplifier arrays located between adjacent memory mats, the sense amplifier arrays including a plurality of sense amplifiers including a pair of input/output nodes, one of which pair is connected to the bit lines of the adjacent memory mats on one side and the other of which pair is connected to the bit lines of the adjacent memory mats on the other side, respectively; and an activating unit which, in response to activation of the word line in a memory mat selected from the memory mats, activates the dummy word line in the memory mat adjacent to the selected memory mat.

Abstract: A semiconductor memory device includes a first cell array including a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells. Each unit cell is provided with a PMOS transistor and a capacitor. Therefore, the semiconductor memory device efficiently operates with low voltage without any degradation of operation speed.

Abstract: A semiconductor memory device includes: memory cells respectively arranged on intersecting points of a plurality of word lines and a plurality of data lines, and respectively having a capacitor for storing data; a sense amplifier provided in between the data lines forming a data line pair so as to amplify an electric potential difference between the data lines and to perform data reading; and a test memory cell arranged on each of the data lines and having a test capacitor with a capacitance value set smaller than the above capacitor, and when performing a test for a memory cell, inversed data of the data to be stored into a target memory cell of a test target is pre-written into the test memory cell.

Abstract: This invention provides a semiconductor memory device with enhanced speed performance or enabling timing adjustment reflected in characteristic variation of memory cells, adapted to suppress an increase in the number of circuit elements. A write dummy bit section comprises a first dummy line and a second dummy line corresponding to complementary bit lines and a plurality of first dummy cells formed to be similar in shape to static memory cells, wherein a write current path is coupled between the first dummy line and the second dummy line. In the write dummy bit section, one voltage level is input to the first dummy line through driver MOSFETs in relation to write signal inputs to the static memory cells and a signal change in the second dummy line precharged at the other voltage level is sensed and output. A timing control circuit deselects a word line selected by an output signal from the write dummy bit section.

Abstract: The sense amplifier detects and amplifies a signal read via bit lines from the ferroelectric capacitor of the memory cell. The dummy capacitor provides a reference voltage to bit lines. The dummy capacitor includes a first dummy capacitor and a second dummy capacitor. The first dummy capacitor is provided with a first dummy plate potential at one end to set the reference voltage to a certain potential. The other end is connected to the bit line. The second dummy capacitor is provided with a second dummy plate potential at one end to fine-tune the reference voltage from the certain potential. The other end thereof is connected to the bit line.

Abstract: A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of clamp bit lines and reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a clamp cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.

Abstract: A system and method, including software implemented techniques, can be used to adjust for sag in stored data values. Charge is applied to multiple memory cells, and each memory cell is charged to a target voltage corresponding to a data value. The memory cells include a reference cell that is charged to a predetermined voltage. A voltage level in the reference cell is detected, and voltage levels from a group of memory cells are also detected. An adjustment is performed based upon the difference between the detected voltage level in the reference cell and the predetermined voltage.

Abstract: The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.

Abstract: A sense amplifier includes a reference signal providing unit and an internal sense amplification unit. The reference signal providing unit provides a reference bit line signal in response to a reference control signal. The internal sense amplification unit receives the reference bit line signal and data signals that correspond to the data. The received signals are provided through bit lines connected to the memory cell array. The internal sense amplification unit senses the received reference bit line signal and the data signals and amplifies the sensed signals. The sense amplifier senses data stored in memory cells connected to dummy bit lines of the outmost memory cell array of a semiconductor memory device such that the memory cells that are not used can be used. Accordingly, the design area and cost of the semiconductor memory device can be reduced.

Abstract: A non-volatile semiconductor memory device includes a memory array having a cell string. The cell string includes a plurality of normal memory cells, a ground selection transistor gated so as to provide a source voltage to the normal memory cells, at least two dummy cells connected between a normal memory cell on one side end of the cell string and the ground selection transistor, wherein the normal memory cells are configured to store data and the dummy cells are configured to not store data. The memory device also includes a word line selection block which controls normal word lines to gate the normal memory cells and dummy word lines to gate the dummy cells, wherein the dummy word lines are controlled as sequential voltage levels during a program operation to select the normal memory cell on the one side end.

Abstract: This semiconductor memory device comprises a plurality of sub-arrays with a plurality of memory cells arranged in matrix form. Each local bit line is connected to a plurality of memory cells that are arranged in column direction in the sub-arrays. In addition, a global bit line is connected to the plural local bit lines. A column decoder is connected to the global bit line. The global bit line extends from the column decoder toward the plurality of sub-arrays, and it is cut before the furthest sub-array formed in the furthest region from that column decoder.

Abstract: Embodiments of the present invention provide channel estimation for multi-level memories using pilot signals. A memory apparatus includes a memory block comprising a plurality of memory cells and adapted to operate with at least two levels of signals for writing data into and reading data from the memory cells. At least two memory cells are employed as reference cells to output a plurality of pilot signals. The memory apparatus also includes a channel block operatively coupled to the memory block, and adapted to facilitate the writing and reading of data into and from the memory cells. The channel block is also adapted to receive the pilot signals and determine one or more disturbance parameters based at least in part on the pilot signals and to compensate the read back signals based at least in part on the determined one or more disturbance parameters during said reading of data from the memory cells. Other embodiments may be described and claimed.

Abstract: A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that trigger a read/write enable signal. A second programmable delay element coarsely adjusts the delay of a first signal associated with a dummy bitline. A third programmable delay element finely adjusts the delay of a second signal associated with the dummy bitline. A fourth programmable delay element controls the delay of a signal used to reset the read/write enable signal. During a read operation, the voltage level of the second signal is used as an indicator to activate the sense amplifiers. During a write operation, the voltage level of the second signal is used to control the write cycle.

Abstract: Dummy memory cells are disposed on an outside of real memory cells positioned on a peripheral part of a matrix. First contacts coupling between two wiring layers laminated on a semiconductor substrate are disposed around each of the real and dummy memory cells, and are shared by an adjacent real or dummy memory cell. Number of the first contacts disposed in each of the dummy memory cells is set to be smaller than number of the first contacts disposed in each of the real memory cells. Accordingly, even when a well region is not formed normally due to a variation in manufacturing conditions, it is possible to prevent an abnormal power supply current from being flown into the dummy memory cells, and an occurrence of latch up can be prevented.

Abstract: A dynamic type semiconductor memory device includes a sense amplifier connected with a bit line pair to amplify and sense a voltage difference on the bit line pair; a precharge circuit configured to precharge the bit line pair to a power supply voltage on a lower side in response to a first control signal; a memory cell capacitance having one end which is connected with the bit line pair through a first switch circuit which is controlled in response to a signal on a word line; and a reference cell capacitance having one end which is connected with the bit line pair through a second switch circuit which is controlled in response to a signal on a reference word line. The other end of the memory cell capacitance and the other end of the reference cell capacitance are electrically separated.

Abstract: A differential sense amplifier can perform data sensing using a very low supply voltage.

Abstract: A memory device includes a group of memory cells organized in rows and columns and a first addressing circuit for addressing said memory cells of said group on the basis of a cell address. The device further includes a plurality of sets of reference cells, associated to the group, each of said set having a plurality of reference cells, and a second addressing circuit for addressing one of the reference cells during operations of read and verify of addressed memory cells.

Abstract: A ferroelectric memory device includes: a memory cell having a transistor and a ferroelectric capacitor connected in series between a bit line and a plate line, and a connecting section below the ferroelectric capacitor; a dummy cell having a transistor, a ferroelectric capacitor and a connecting section, wherein the dummy cell has an electrically disconnected section among the bit line, the transistor, the ferroelectric capacitor, the connecting section and the plate line.

Abstract: A memory device that can provide good timing margins for read and write operations is described. In one design, the memory device includes a memory array, a timing control circuit, and an address decoder. The memory array includes memory cells for storing data and dummy cells to mimic the memory cells. The timing control circuit generates at least one control signal used for writing data to the memory cells and having timing determined based on the dummy cells. The timing control circuit may generate a pulse on an internal clock signal with a driver having configurable drive strength and a programmable delay unit. The pulse duration may be set to obtain the desired write timing margin. The address decoder activates word lines for rows of memory cells for a sufficiently long duration, based on the internal clock signal, to ensure reliable writing of data to the memory cells.

Abstract: A precharge circuit precharges a bit line paired with the bit line to which the selected one of the memory cells is connected, by applying to the former bit line an external reference voltage for comparison with a voltage in the bit line caused by selection of the memory cell. A precharge assist circuit, which is connected to the former bit line in parallel with the precharge circuit, charges the bit line to a predetermined potential by using a power supply voltage. A sense amplifier, which is connected to the pair of bit lines, senses and amplifies a potential of a bit line that is connected to a memory cell selected by word lines.

Abstract: The present invention relates to a circuit and a method for controlling a self-refresh cycle of a dynamic random access memory or DRAM. A cell voltage is directly detected so that a self-refresh cycle can be variably controlled. Detectors each detecting whether or not a voltage charged into a capacitor of a detection cell drops to or below a reference voltage and outputs a detection signal. A pulse generator generates a self-refresh pulse while being linked with an enabled detection signal of the plurality of detectors. A self-refresh cycle can be variably controlled and set to be suitable for the charging capacity of a cell. The detection cell is adapted to the change of the charging capacity of the cell in accordance with a change in temperature.

Abstract: Systems and methods of controlled value reference signals of resistance based memory circuits are disclosed. In a particular embodiment, a circuit device is disclosed that includes a first input configured to receive a reference control signal. The circuit device also includes an output responsive to the first input to selectively provide a controlled value reference voltage to a sense amplifier coupled to a resistance based memory cell.

Abstract: A resistance change memory includes first and second memory cell arrays which are adjacent to each other in a first direction, first and second reference cell arrays paired with the first and second memory cell arrays, a first sense amplifier shared by the first and second memory cell arrays and arranged between the first and second memory cell arrays, a first data bus which transfers data of a first readout cell in the first memory cell array to the first sense amplifier, and a second data bus which transfers data of a first reference cell in the first reference cell array to the first sense amplifier. The first and second data buses run on both sides of the first sense amplifier in a second direction and cross each other while sandwiching the first sense amplifier.

Abstract: A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line column, and a control circuit. The control circuit generates a control signal to perform read and write operations on the memory device. The address decoder selects a bit line and a word line. The selected word line is activated by the word line driver. While the reference word line column is used for vertical tracking of the word line, the reference bit line column is used for vertical tracking of the bit line. The sense amplifiers are activated to read the bit line.

Abstract: A sense amplifier control unit include: a control unit that detects a variation in the level of an external voltage and outputs a delay time selection signal on the basis of the result of the detection. A variable delay unit delays an active signal by a delay time corresponding to the delay time selection signal and outputs the delayed signal. A driving signal generating unit outputs a driving signal according to the output of the variable delay unit. A sense amplifier driver drives a sense amplifier on the basis of the driving signal.

Abstract: In a semiconductor memory device, a method for obtaining at least one reference cell adapted to be exploited as a generator of a reference signal, the reference signal depending on a value of an electrical characteristic of the at least one reference cell. The method includes providing a population of auxiliary cells, operating on said population of auxiliary cells for varying a value of the electrical characteristic thereof, in such a way that the varied values are statistically distributed in a range including a value of the electrical characteristic corresponding to the reference signal, and choosing the at least one reference cell, wherein choosing includes choosing at least one auxiliary cell in the population of auxiliary cells having the value of the electrical characteristic close to the value corresponding to the reference signal with a pre-defined tolerance.

Abstract: An apparatus including a memory cell, a reference cell, a control unit, coupled to the memory cell and the reference cell, and configured to initiate write processes of the memory cell and the reference cell, and a detection unit, coupled to the reference cell, and configured to detect a write completion of the reference cell. Related methods are also disclosed.

Abstract: A high voltage generator of a semiconductor device includes a first high voltage pump unit, a second high voltage pump unit, and a clock signal generating unit. The first high voltage pump unit compares a first high voltage and a first reference voltage to generate a first enable signal, and performs a pumping operation in response to the first enable signal and a first clock signal to generate the first high voltage. The second high voltage pimp unit compares a second high voltage and a second reference voltage to generate a second enable signal, and perform a pimping operation in response to the second enable signal and a second clock signal to generate the second high voltage. The clock signal generating unit generates the first clock signal or the second clock signal in response to the first enable signal and the second enable signal when at least one of the first enable signal and the second enable signal is enabled.

Abstract: A semiconductor memory has a memory unit including a regular cell array having a plurality of memory cells and a decoder for decoding an input address and selecting a memory cell corresponding to the input address in the regular cell array, in which an access operation is performed to the selected memory cell; a defective address storage section which stores a defective address corresponding to a defective bit in the regular cell array; and a replacement address storage section which stores a replacement address corresponding to a replacement bit in the regular cell array. When a supply address supplied to the memory unit matches the defective address, the replacement address, in place of the supply address, is supplied to the memory unit as the input address, according to which the access operation is performed.

Abstract: An embodiment of the invention relate to a memory device including a memory plane composed of memory cells located at the intersection of lines and columns, and a dummy path designed to output a signal to activate read amplifiers arranged at the bottom of the columns in the memory plane, said dummy path including dummy memory cells connected between two dummy bit lines means of selecting at least one dummy cell designed to discharge at least one of the dummy bit lines, and control means connected to the two dummy bit lines to generate said activation signal, characterized in that said device includes means of programming the number of selected cells to discharge at least said dummy bit line, to adjust the time at which said activation signal is output.

Abstract: According to one embodiment of the present invention, an integrated circuit having a cell arrangement is provided. The cell arrangement includes: at least one reference memory cell set to a reference memory cell state; and a bias supplier to supply a bias condition to the reference memory cell when accessing the memory cell, such that the bias condition increases the stability of the set reference memory cell state.

Abstract: A reference voltage supply apparatus and a driving method thereof in a ferroelectric memory device provide a reference voltage stabilized against the imprint effect thus maintaining reading reliability of the device. In the reference voltage supply apparatus (e.g., using a non-switching capacitance of a ferroelectric capacitor), a reference cell is constructed of a ferroelectric capacitor and an access switch, and provides a reference voltage to read data from a memory cell. In an active mode, the reference cell stores data of a first logic state (e.g., corresponding to the non-switching capacitance of the ferroelectric capacitor), in the reference cell, and then supplies, as a reference voltage, the voltage corresponding to the data of the first logic state to a bit line; and in a stand-by mode, a reference voltage controller stores (writes) data of a second logic state (opposite to the first logic state), into the reference cell.

Abstract: Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times of read and write operations. Changes in the resistance value of the dummy cells are detected by comparator circuits. If the resistance value have been changed beyond a predetermined reference value (that is, changed to a low resistance), a refresh request circuit requests an internal circuit, not shown, to effect refreshing. The memory cells and the dummy cells are transitorily refreshed and correction is made for variations in the programmed resistance value of the phase change devices to assure the margin as well as to improve retention characteristic.

Abstract: A dual mode accessing signal control apparatus for being used in a dummy cells set of a memory, and a dual mode timing signal generating apparatus comprising a dual mode accessing signal control apparatus are provided. The dual mode accessing signal control apparatus respectively generates a write delay signal and a read signal during the write and the read process. The memory is thereby capable of self-timing its write and the read process, and is able to generate a wordline signal with a shorter width in the write process to ensure an early start to precharging. As a result, the whole duty period of the memory can be shortened.

Abstract: A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that trigger a read/write enable signal. A second programmable delay element coarsely adjusts the delay of a first signal associated with a dummy bitline. A third programmable delay element finely adjusts the delay of a second signal associated with the dummy bitline. A fourth programmable delay element controls the delay of a signal used to reset the read/write enable signal. During a read operation, the voltage level of the second signal is used as an indicator to activate the sense amplifiers. During a write operation, the voltage level of the second signal is used to control the write cycle.

Abstract: Twin cell type semiconductor memory devices are provided that include a plurality of main bit lines and a plurality of reference bit lines. Each of the reference bit lines correspond to respective ones of the main bit lines to form a plurality of bit line pairs. A plurality of sense amplifiers are provided that are electrically connected to a respective one of the plurality of bit line pairs. At least one of the plurality of main bit lines or the plurality of reference bit lines is interposed between the main bit line and the corresponding reference bit line of each bit line pair. At least some of the main bit lines may cross respective ones of the reference bit lines in a sense amplifier region of the semiconductor memory device that contains the plurality of sense amplifiers.

Abstract: Voltage and current stress for magnetic random access memory (MRAM) cells can weed out potential early failure cells. Method and circuit implementation of such a stress test for a MRAM comprise coupling a stress test circuit to the read bus of the MRAM and stressing the Magnetic Tunnel Junctions (MTJS) by tying them to ground by activating isolation transistors associated with them. Read word lines control which MTJs are stressed Both the method and implementation can be used for any memory cells based on resistance differences, such as Phase RAM or Spin Valve MRAM.

Abstract: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.

Abstract: A semiconductor memory device includes a plurality of memory cell array blocks connected to word lines, source lines, and bit lines, each memory cell array including memory cells each having a transistor with a floating body, a reference voltage generator configured to have a reference memory cell and generate a reference voltage for bit line sensing corresponding to a current flowing into a reference memory cell during a data read operation, first and second prechargers configured to precharge a bit line connected to non-selected memory cells to the reference voltage in response to first and second precharge control signals during the data read operation, and a sense amplifier configured to sense and amplify a voltage difference between a bit line connected to the selected memory cells and a bit line connected to the non-selected memory cells during the data read operation.

Abstract: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of word lines (e.g., first and second word lines) and a plurality of word line segments (e.g., first and second word line segments) wherein each word line segment is coupled to an associated word line (e.g., a first segment is associated with the first word line and a second segment is associated with the second word line). The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, wherein the body region is electrically floating, and a gate coupled to an associated word line via an associated word line segment.