Abstract: An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.

Abstract: A memory circuit includes a voltage boosting circuit for generating a voltage that exceeds a voltage supply of the voltage boosting circuit. The voltage boosting circuit includes a first transistor having a first polarity type and a second transistor having a second polarity type opposite the first transistor. The first transistor is a planar transistor, a source of the first transistor being connected with the voltage supply, and a gate of the first transistor receiving a control signal. The second transistor includes a gate formed in at least two planes. A source of the second transistor is connected with the voltage supply, a gate of the second transistor receives the control signal, and a drain of the second transistor is connected with a drain of the first transistor and forms an output of the voltage boosting circuit for generating a boosted supply voltage as a function of the control signal.

Abstract: A solid state storage device receives a device sleep signal and a power signal from a host. The solid state storage device includes a control chip, a sleep control circuit, and a regulator. If the device sleep signal is activated, the control chip temporarily stores a system parameter into a flash memory module and then generates an acknowledge signal. The sleep control circuit receives the power signal, the device sleep signal and the acknowledge signal. If both of the device sleep signal and the acknowledge signal are activated, the sleep control circuit generates a disable state and a wake-up state. Moreover, if the power signal is received by the regulator and the sleep control circuit generates the disable state, the regulator stops providing a supply voltage to the control chip, so that the solid state storage device enters a sleep mode.

Abstract: A supply voltage distribution system for distributing a supply voltage through a semiconductor device, the supply voltage distribution system comprising: a first supply voltage distribution line arrangement and a second supply voltage distribution line arrangement, said first supply voltage distribution line arrangement and said second supply voltage distribution line arrangement being adapted to receive from outside the semiconductor device a semiconductor device supply voltage and to distribute a supply voltage to respective first and second portions of the semiconductor device; and a voltage-to-voltage conversion circuit connected to the first supply voltage distribution line arrangement, wherein the voltage-to-voltage conversion circuit is adapted to either transfer onto the first supply voltage distribution line arrangement the semiconductor device supply voltage received from outside the semiconductor device, or to put on the first supply voltage distribution line a converted supply voltage having a

Abstract: A semiconductor chip includes: a data output buffer that outputs a data signal; a first power-supply pad that supplies a first power-supply potential to the data output buffer; a power-supply wiring that is connected to the first power-supply pad; a strobe output buffer that outputs a strobe signal; and a second power-supply pad that supplies a second power-supply potential to the strobe output buffer. The power-supply wiring and the second power-supply pad are electrically independent of each other. Therefore, the power-supply noise associated with the switching of the data output buffer does not spread to the strobe output buffer. Thus, it is possible to improve the quality of the strobe signal.

Abstract: A semiconductor device includes: an input node supplied with an input signal; an output node provided correspondingly to the input node; first and second input circuits coupled in parallel to each other between the input and output nodes; and a control circuit configured to control the first and second input circuits such that one of the first and second input circuits is switched over from an active state to an inactive state and the other of the first and second input circuits is switched over from an inactive state to an active state during the one of the first and second input circuits being still in the active state.

Abstract: An apparatus including a memory module and power converter and method of operating the same. In one embodiment, the apparatus includes a memory module, located on a circuit board, configured to operate from a first voltage and a second voltage being a multiple of the first voltage. The apparatus also includes a power converter employing a switched-capacitor power train, located on the circuit board, configured to provide the second voltage for the memory module from the first voltage.

Abstract: Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines.

Abstract: Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (NVM), test cells associated with the NVM are read first. The test cells share a common power supply with the NVM and output read values from the test cells are configured to deviate from values pre-programmed in the test cells when a subnormal read voltage is applied on the common power supply. Thus, by comparing the output read values with the pre-programmed values, it can be determined whether voltage of the common power supply is subnormal, wherein configuration information will be read incorrectly at a subnormal read voltage. If the voltage is subnormal, power up is aborted. Otherwise, power up is allowed to proceed by reading the configuration information from the NVM.

Abstract: Methods and apparatus for providing single finFET and multiple finFET SRAM arrays on a single integrated circuit are provided. A first single port SRAM array of a plurality of first bit cells is described, each first bit cell having a y pitch Y1 and an X pitch X1, the ratio of X1 to Y1 being greater than or equal to 2, each bit cell further having single fin finFET transistors to form a 6T SRAM cell and a first voltage control circuit; and a second single port SRAM array of a plurality of second bit cells, each second bit cell having a y pitch Y2 and an X pitch X2, the ratio of X2 to Y2 being greater than or equal to 3, each of the plurality of second bit cells comprising a 6T SRAM cell wherein the ratio of X2 to X1 is greater than about 1.1.

Abstract: The present technology relates to an electronic device, and more particularly, to a semiconductor device. The semiconductor device includes a peripheral circuit, a power output line connected to the peripheral circuit and configured to transmit an operation voltage to the peripheral circuit, a current compensator including an OP-amplifier connected to the power output line, and a capacitor connected between an output terminal of the OP-amplifier and the power output line.

Abstract: An exemplary method includes performing flash memory operations; receiving a signal from a voltage monitor as being associated with the performed flash memory operations; and, based at least in part on the received signal, setting a limit for performing subsequent flash memory operations. In such a method, the limit can act to avoid resetting flash memory responsive to current demand associated with subsequent flash memory operations. Various other apparatuses, systems, methods, etc., are also disclosed.

Abstract: A system includes a first chip configured to supply a training command and a second chip configured to transfer to the first chip a measured time for performing an operation in response to the training command.

Abstract: A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.

Abstract: A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.

Abstract: Disclosed herein is a device that includes a capacitor, a pumping circuit supplying a pumping signal changed between first and second potential to a first electrode of the capacitor, and an output circuit precharging a second electrode of the capacitor to a third potential different from the first and second potentials. The second electrode of the capacitor is thereby changed from the third potential to a fourth potential higher than the third potential when the pumping signal is changed from the first potential to the second potential.

Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Abstract: The present invention relates to a voltage regulator and to a method of operating a voltage regulator that is operable in a reset mode and in a sampling mode. The voltage regulator comprises: a capacitive voltage divider having a first capacitor and a second capacitor in series with the first capacitor, wherein the capacitive voltage divider is connectable to an output of a voltage supply to activate the sampling mode, a comparator having an output connected to an input of the voltage supply, the comparator further having a first input connected to a sampling node arranged between the first capacitor and the second capacitor and the comparator having a second input connected to a reference voltage, wherein the sampling node is connectable to the reference voltage for activating the reset mode.

Abstract: A clock driver integrated circuit device and method is provided. The device can include a VTT regulator provided on a single integrated circuit (IC) chip. A first termination at an internal VDD/2 can be coupled to the VTT regulator. A VTT bus can be coupled to the first termination. A plurality of command control inputs can be coupled to the VTT bus. The plurality of command inputs can include A, BA, RAS, CAS, WE, CS, CKE, ODT, PARIN, and the like. A VDD termination can be coupled to a first end of the VTT bus and a ground can be coupled to a second end of the VTT bus. The method can include regulating or removing signal noise from a host controller via the clock driver IC device.

Abstract: A semiconductor storage device 100 includes a controller package 110 having a BGA terminal on a bottom surface thereof; and one or a plurality of memory packages 120 each including a plurality of semiconductor storage elements and mounted on the controller package. The controller package includes a bottom substrate having the BGA terminal on a bottom surface thereof; a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC. The controller provides an interface with an external system via the BGA terminal and controls a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements.

Abstract: A memory comprising a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is configured to boost the word line voltage to a predetermined voltage value greater than a target threshold voltage, change a clock frequency of a clock signal supplied to the charge pump from a non-zero frequency to a zero frequency if the word line voltage is above the predetermined voltage value, and change the clock frequency from the zero frequency to the non-zero frequency if the word line voltage is below the target threshold voltage.

Abstract: A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

Abstract: An input buffer includes a first buffer circuit to amplify a difference between a first input signal and a second input signal; a second buffer circuit formed of a replica circuit of the first buffer circuit to generate a common mode output signal in response to the first input signal; and a detector to compare the common mode output signal with a reference output signal and to control the first and second buffer circuits according to the comparison result such that a level of the common mode output signal coincides with a level of the reference output signal.

Abstract: An integrated circuit with SRAM cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and one passgate transistor may be variously configured to a separate read data line and write data line, or a combined data line, in different embodiments. The read buffer in addressed SRAM cells may be biased during read operations. The read buffer in half-addressed SRAM cells may be biased or floated, depending on the configuration of the read data line and the write data line. The read buffer in addressed and half-addressed SRAM cells may be biased or floated, depending on the configuration of the read data line and the write data line.

Abstract: Provided is an electronic device including a power supply circuit. The power supply circuit includes: a voltage driving unit configured to pull-up drive an output node and generate an output voltage; and a driving control unit configured to receive the output voltage, disable the voltage driving unit from the time at which a divided voltage obtained by dividing the output voltage at a set ratio becomes higher than a first level, and enable the voltage driving unit from the time at which the divided voltage becomes lower than a second level, which is higher than the first level.

Abstract: A startup circuit is disclosed operable to perform a startup operation for an electronic device comprising digital circuitry. The startup circuit comprises a first clock generator operable to generate a first clock comprising a first period, and a second clock generator operable to generate a second clock independent of the first clock. The second clock is operable to clock the digital circuitry and comprises a second period less than the first period. A first counter counts a first number of the second periods over the first period, and the second clock is enabled to clock the digital circuitry in response to the first counter.

Abstract: Disclosed is a semiconductor memory device, including a plurality of internal voltage generation units configured to be enabled in response to each of a plurality of decoding signals and to generate an internal voltage, a controller configured to generate a plurality of control signals in response to a power up signal and a test mode signal, and a decoder configured to generate the plurality of decoding signals corresponding to at least one decoding source signal and to simultaneously activate some or all of the plurality of decoding signals in response to the control signals.

Abstract: An embodiment of the present disclosure refers to retention of data in a storage array in a stand-by mode. A storage device comprises one or more storage array nodes, and a Rail to Rail voltage adjustor operatively coupled to the storage array nodes. The Rail to Rail voltage adjustor is configured to selectively alter the voltage provided at each said storage array node during stand-by mode. The storage device may further comprise a storage array operatively coupled to said Rail to Rail voltage adjustor and a Rail to Rail voltage monitor operatively coupled to said storage array nodes and configured to control said Rail to Rail voltage adjustor to provide sufficient voltage to retain data during stand-by mode.

Abstract: A power strategy selector queries a lookup table using a current flash status of a flash drive, and determines a burst operating voltage for operating the flash drive. Therefore, precise buffering of parameters or data can be ensured when the flash drive meets an unexpected power failure or malfunctions, or precise operations of the flash drive can be guaranteed.

Abstract: A voltage source controller for a memory array includes an input coupled to a voltage source, an output coupled to one or more memory cells of a memory array, where the output is configured to provide a cell source voltage to the memory cells. The controller also includes a switch circuit configured to: receive a retention enable signal, a write assist enable signal, and a standard mode enable signal; and based on the retention enable signal, write assist enable signal, and standard mode enable signal, selectively set the cell source voltage for one or more of the memory cells to one of: a retention voltage, a write assist voltage, or a standard mode voltage, where the retention voltage and the write assist voltage are less than the standard mode voltage.

Abstract: Embodiments of the invention are generally directed to interfacing between integrated circuits with asymmetric voltage swing. An embodiment of an apparatus includes a first integrated circuit including a first transmitter and a first receiver; a second integrated circuit including a second transmitter and a second receiver; and an interface including communication channel linking the first transmitter with the second receiver and the first receiver with the second transmitter, wherein the communication channel is one of a single channel or a dual channel. The first transmitter is operable to transmit a first signal and the second transmitter is operable to transmit a second signal, a first average voltage swing of the first signal being asymmetric with a second average voltage swing of the second signal.

Abstract: A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.

Abstract: Power management of an embedded dynamic random access memory (eDRAM) by receiving an eDRAM power state transition event and determining both the current power state of the eDRAM and the next power state of the eDRAM from the power states of: a power-on state, a power-off state, and a self-refresh state. Using the current power state and the next power state to determine whether a power state transition is required, and, in the case that a power state transition is required, transition the eDRAM to the next power state. Power management is achieved because transitioning to a power-off state or self-refresh state reduces the amount of power consumed by the eDRAM as compared to the power-on state.

Abstract: An internal voltage generation circuit includes a flag signal generator suitable for generating a first flag signal which is enabled after a first predetermined time from a moment that a deep power-down mode terminates and suitable for generating a second flag signal which is enabled after a second predetermined time from a moment that the first flag signal is enabled, a drive signal generator suitable for receiving the first and second flag signals to generate a first drive signal and a second drive signal and suitable for receiving a pre-oscillation signal in response to the first and second flag signals to generate a third drive signal and a fourth drive signal, and an internal voltage generator suitable for driving a first internal voltage signal in response to the first and second drive signals and suitable for pumping a second internal voltage signal in response to the third and fourth drive signals.

Abstract: A method for operating a memory module device. The method can include transferring a chip select, command, and address information from a host memory controller. The host memory controller can be coupled to a memory interface device, which can be coupled to a memory module. The memory module can comprise a plurality of memory devices. The chip select, command and address information can be received at the memory interface using a command-and-address-latency (CAL) mode. Control logic can be used to initiate a power state transition from a first power state to a second power state of an input termination circuit in the memory interface device.

Abstract: A flash memory device. In one embodiment, the flash memory device comprises a flash memory, a diode, a controller, and a capacitor. The flash memory has a voltage source pin. The diode is coupled between a voltage source and the voltage source pin of the flash memory. The controller is coupled to the flash memory via a data bus. The capacitor is coupled between the voltage source pin of the flash memory and a ground, and supplies power to the flash memory to enable the flash memory to complete writing of at least one data page when the level of the voltage source is lowered.

Abstract: A semiconductor integrated circuit according to an embodiment includes an oscillator that generates and outputs an oscillation signal in an active state and generates no oscillation signal in an inactive state. The semiconductor integrated circuit includes a negative charge pump that generates an output voltage that is a negative voltage in response to the oscillation signal and outputs the output voltage to an output pad. The semiconductor integrated circuit includes a negative voltage detecting circuit that detects the output voltage and controls the oscillator to be in the active state or inactive state so as to bring the output voltage close to a target voltage.

Abstract: A data split between a first data line and a second data line is caused to develop. At least one of the following sets of steps is performed: 1) a first power supply line of a sense amplifier is caused to rise towards a first power supply voltage value, and when the first power supply line reaches a first predetermined voltage value, the first power supply is caused to rise above the first power supply voltage value; and 2) a second power supply line of the sense amplifier is caused to fall towards a second power supply voltage value, and when the second power supply line reaches a second predetermined voltage value, the second power supply line is caused to fall below the second power supply voltage value.

Abstract: An operation method of a memory includes the following steps: determining the number of memory units required to update the content stored therein when the memory is performing a program operation based on the N-bit input data and accordingly generate a first determination result; and providing (N?M) number of loads to a source line decoder of the memory if the first determination result indicates that there are M number of memory units required to update the content stored therein, and thereby coupling the (N?M) number of the provided loads to a transmission path of a power supply voltage in parallel, wherein N and M are natural numbers. A memory is also provided.

Abstract: An integrated circuit includes a programmable storage unit suitable for operating with a plurality of powers and outputting stored data in response to a boot-up signal, a register unit suitable for storing the data outputted from the programmable storage unit, a internal circuit suitable for operating by using the data stored in the register unit, a voltage detection unit suitable for activating a power stabilization signal when levels of the plurality of powers are stabilized, and a boot-up control unit suitable for counting a number of activations of a periodic wave from a time of an activation of the power stabilization signal and activating the boot-up signal when the counted number reaches a predetermined number.

Abstract: Techniques are presented to improve the performance, accuracy and power consumption of on-chip voltage biasing and transmission for highly loaded RC networks (such as wordlines or bitlines in NAND or 3D memory arrays) that are otherwise limited by the physics of RC time constant. When transitioning the near-end voltage of the network, an under-drive or over-drive level is applied, combined with feedback control to estimate when the far-end voltage approaches the desired level.

Abstract: An apparatus including a memory module and power converter and method of operating the same. In one embodiment, the apparatus includes a memory module, located on a circuit board, configured to operate from a first voltage and a second voltage being a multiple of the first voltage. The apparatus also includes a power converter employing a switched-capacitor power train, located on the circuit board, configured to provide the second voltage for the memory module from the first voltage.

Abstract: A semiconductor device includes plural memory cells each having a first inverter and a second inverter, with an input of the first inverter being coupled to an output of the second inverter and an input of the second inverter being coupled to an output of the first inverter. The first and second inverters have drive transistors supplied with a source voltage where the source voltage is raised in response to a level shift of a control signal supplied to a switch of a control circuit. The control circuit further includes a resistance element in parallel with a MOS transistor connected as a diode.

Abstract: A hybrid charge pump and control circuit for use in a memory device is disclosed.

Abstract: A regulator includes a variable resistance unit coupled between an input node to which a pumping voltage is inputted and a control node and configured to adjust resistance of the variable resistance unit in response to a control signal varied depending on a target voltage, a voltage output unit configured to adjust the pumping voltage according to potential of the control node and output the adjusted pumping voltage, and a regulation unit configured to control the potential of the control node according to the adjusted pumping voltage, to output the target voltage. The regulator adjusts the resistance of an internal resistor according to the target voltage, thereby reducing current consumption.

Abstract: A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., synchronization bit(s)) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted.

Abstract: A charge/discharge circuit is configured to directly charge a storage system using a power source under a power-on stage and to charge the storage system using power pre-stored in a capacitor under a power-off stage. With the aid of the charge/discharge circuit, an access speed of the storage system is prevented from being slowed down by attaching the large capacitance of the capacitor, and data accuracy of the storage system is prevented from being affected by sudden loss of power supply of the power source.

Abstract: According to one embodiment, in a semiconductor storage system, the power supply wiring is connected to a first semiconductor storage device, and second semiconductor storage device as a common connection, and supplies power to the first and second semiconductor storage devices. A voltage detection circuit is provided in each of the first and second semiconductor storage devices. Each of the voltage detection circuits detects a power supply voltage of the power supply wiring. A control circuit is provided in each of the first and second semiconductor storage devices. When lowering of the power supply voltage is detected by a corresponding voltage detection circuit, each of the control circuits does not shift the operation of the first or second semiconductor storage device to the next operation until the power supply voltage is restored.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement.

Abstract: A semiconductor device comprises a first pair of signal lines and a first control circuit. The first control circuit precharges each of the first pair of signal lines to a first voltage in response to a precharge signal, and changes the voltage level of each of the first pair of signal lines to a second voltage different from the first voltage when a deep power down signal is input.