Abstract: A semiconductor memory apparatus performs a selection in a normal readout/write-in mode and an automatic refreshing mode and includes a sense amplifier reading out data from a memory device, a first switching device connecting a first power supply voltage acting as an overdrive voltage to a first power supply intermediate node during a first period and then connecting a second power supply voltage acting as an array voltage to the first power supply intermediate node, a second switching device connecting the fourth power supply voltage to a second power supply intermediate node of the sense amplifier when the sense amplifier is driven, a first capacitor connected to the overdrive voltage and charging it, a third switching device switched on in the automatic refreshing mode, and a voltage generator generating a third power supply voltage and applying it and the first power supply voltage in parallel through the third switching device.

Abstract: An implantable medical device have an associated memory device is disclosed. The implantable medical device utilizes techniques for optimizing one or more embedded operations of the memory device, such operations including programming, reading or erasing data. The techniques for optimizing the embedded operations include controlling the operations as a function of an energy source of the implantable medical device.

Abstract: A voltage supply circuit for a memory cell including a first circuit coupled between a first voltage supply and a first voltage supply terminal of the memory cell, and a second circuit coupled between the first voltage supply and a second voltage supply terminal of the memory cell. The first circuit is controlled by a first bit line of the memory cell, and the second circuit is controlled by a second bit line of the memory cell. The first and second circuits provide the first supply voltage to the first and second voltage supply terminals of the memory cell, respectively, during a pre-charge phase. During a write operation, only one of the first circuit and the second circuit provides the first supply voltage to the memory cell, and the other one of the first circuit and the second circuit provides an adjusted voltage (e.g., a collapsed voltage) to the memory cell.

Abstract: A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.

Abstract: A memory apparatus includes a write driver, a sense amplifier and a reference voltage setting circuit. The write driver programs a set data or a reset data into a memory cell. The sense amplifier generates an output signal by sensing data stored in the memory cell. The reference voltage setting circuit sets a set reference voltage having a lowest level to satisfy a set data distribution, and sets a set-up reset reference voltage from the set reference voltage.

Abstract: Efficiency of a charge pump circuit is increased. The charge pump circuit includes serially connected fundamental circuits each including a diode-connected transistor and a capacitor. At least one transistor is provided with a back gate, and the back gate is connected to any node in the charge pump circuit. For example, the charge pump circuit is of a step-up type; in which case, if the transistor is an n-channel transistor, a back gate of the transistor in the last stage is connected to an output node of the charge pump circuit. Back gates of the transistors in the other stages are connected to an input node of the charge pump circuit. In this way, the voltage holding capability of the fundamental circuit in the last stage is increased, and the conversion efficiency can be increased because an increase in the threshold of the transistors in the other stages is prevented.

Abstract: The dNap architecture is able to accurately transition cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

Abstract: A semiconductor memory device includes a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to a power supply voltage and an output driver configured to generate a data signal having a VOH proportional to the power supply voltage based on the pull-up VOH code, wherein VOH means “output high level voltage.

Abstract: A memory system has a non-volatile memory including a plurality of circuit blocks using different voltages, a power-off switch circuitry that switches whether or not voltage supply to each of the plurality of circuit blocks in the non-volatile memory is cut off, and a power-off controller that controls the switching of the power-off switch circuitry based on at least one of circuit volumes of the plurality of circuit blocks, standby power of the plurality of circuit blocks, and a circuit volume of the power-off switch circuitry.

Abstract: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.

Abstract: A memory control circuit capable of holding a memory device in a self-refresh mode even when a memory controller is powered off and then restarted. The controller performs data memory reset processing including deleting data in a buffer of a volatile memory device which operates when supplied with power from a first power supply, by changing an effective memory reset signal after the voltage of a second power supply becomes equal to or higher than a predetermined value. The memory reset signal is masked when an effective mask signal is generated. Whether to keep the data is determined when an event occurs which makes the voltage of the second power supply lower than the reset reference value and the first power supply is on. The memory reset signal is masked by making the mask signal effective when the data is determined to be kept.

Abstract: A method of manufacture of the memory management system includes: fabricating a dual in-line memory module carrier; mounting a volatile memory device on the dual in-line memory module carrier; mounting a non-volatile memory on the dual in-line memory module carrier on a side opposite the volatile memory device; mounting an uninterruptible power supply on the dual in-line memory module carrier for maintaining a memory module power when a system power input decays; and mounting a controller logic integrated circuit on the dual in-line memory module carrier coupled to the volatile memory device, the non-volatile memory, and the uninterruptible power supply for copying data content of the volatile memory device to the non-volatile memory when the uninterruptible power supply detects the decay of the system power input to a first cross-over level.

Abstract: A power supply control device for a system having two or more power supply devices, configured to control a first power supply device that includes a compensation device configured to perform power compensation at a time of power failure, the power supply control device includes a controller configured to limit the power compensation of the compensation device in a normal state, and release the limitation on the power compensation of the compensation device if detecting power failure of the first power supply device and detecting power failure of a second power supply device provided redundantly in addition to the first power supply device.

Abstract: The disclosure is directed to a system that includes a memory device. The memory device includes a memory system and an energy storage device including a capacitor. The memory storage device includes power delivery circuitry that delivers to the memory system a first power from the energy storage device and a second power from an external power supply coupled to the memory device.

Abstract: An electronic device may receive a supply voltage from another external device, and detect when a level of the supply voltage drops below a threshold. In response, a controller of the electronic device may deactivate an interface configured for communication with the other electronic device. The controller may manage time periods and time period counters to determine when the check whether to reactivate the interface or conclude that the other external device is non-compliant.

Abstract: A circuit to a extend signal comparison voltage range includes a latching circuit and a comparator responsive to common-mode input signals. The comparator is coupled to the latching circuit and to a dynamic node. The circuit also includes a clocked boost circuit coupled to the dynamic node. The clocked boost circuit is configured to extend a supply voltage range of the comparator via biasing the dynamic node. A method to extend a signal comparison voltage range includes selectively shifting a voltage level of one of a ground reference of a dynamic circuit or a supply reference of the dynamic circuit in response to a clock signal.

Abstract: A memory device and a method for rescheduling memory operations for dynamically controlling power consumption of the memory device is disclosed. The method includes receiving a plurality of memory operations for a plurality of memory arrays of a memory device via a memory channel; storing the plurality of memory operations in a plurality of queues associated with the memory array; receiving a power budget associated with the plurality of memory arrays; determining one or more candidate memory operations in the plurality of queues to meet the power budget for a time window; dynamically rearranging the plurality of memory operations in the plurality of queues and generating rescheduled memory operations that meet the power budget for the time window; and fetching the rescheduled memory operations to the plurality of memory arrays.

Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Abstract: An apparatus includes an integrated circuit, which includes a processor and a driver. The integrated circuit is fabricated by a process that establishes a nominal maximum voltage for components of the integrated circuit. The driver is adapted to selectively electrically couple a voltage that is higher than the nominal maximum voltage to an external terminal of the integrated circuit.

Abstract: Systems, circuits and methods for controlling word line (WL) power levels at a WL of a Magnetoresistive Random Access Memory (MRAM). The disclosed power control scheme uses existing read/write commands and an existing power generation module associated with the MRAM to supply and control WL power levels, thereby eliminating the cost and increased die-size of schemes that control WL power through relatively large and expensive power control switches and control circuitry on the MRAM macro.

Abstract: A three-dimensional (3D) integrated circuit (IC) device can include a first die having a first supply line and a second die having a second supply line, a power header, and a voltage selection logic. The power header can be connected to the first die and the second die and configured to generate a first voltage on a first voltage line and a second voltage on a second voltage line. The voltage selection logic can be connected to the first supply line and the second supply line and configured to select between the first voltage line and the second voltage line for each of the first supply line and the second supply line.

Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.

Abstract: Some embodiments include apparatuses and method using a first node to receive an input voltage, a second node to provide an output voltage, circuit lanes coupled to the first and second nodes, each of the circuit lanes including switches coupled between the first and second nodes, and a controller to selectively place at least one circuit lane among the circuit lanes in an activated state to cause the at least one circuit lane to control the switches in order to adjust an amount of charge provided from a capacitor network to the output node based on a toggling frequency of a comparator output signal generated based on a comparison between a value of a reference voltage and a value of a feedback voltage generated from a value of the output voltage.

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract: Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.

Abstract: Circuits and methods for limiting cell current or throttling write operation, or both, in resistive random access memory (RRAM or ReRAM) cells are provided. An RRAM cell can include a select transistor and a programmable resistor that can change between a relatively high resistance and a relatively low resistance. The present circuits and methods can reduce or inhibit excess current from being applied to the programmable resistor, which potentially can regulate the resistance of the programmable resistor so as to reduce or inhibit decreases in the resistance of that resistor below the relatively low resistance. Such regulation potentially can improve reliability of the RRAM cell. Additionally, or alternatively, the present circuits and methods can throttle a write operation in an RRAM cell, e.g., can disable current flow through the RRAM cell based on the programmable resistor reaching a pre-defined target resistance, such as the relatively low resistance.

Abstract: A semiconductor apparatus including a multichip package is disclosed. The semiconductor apparatus includes a slave chip having a slave region and a master region. The slave region is configured to have a first threshold voltage smaller than an operation voltage and the master region is configured to have a second threshold voltage greater than the operation voltage.

Abstract: A three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) (3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also disclosed. In embodiments disclosed herein, memory read access ports of a memory block are separated from a memory cell in different tiers of a 3DIC. 3DICs achieve higher device packing density, lower interconnect delays, and lower costs. In this manner, different supply voltages can be provided for the read access ports and the memory cell to be able to lower supply voltage for the read access ports. Static noise margins and read/write noise margins in the memory cell may be provided as a result. Providing multiple power supply rails inside a non-separated memory block that increases area can also be avoided.

Abstract: A memory module with power management system, and a method of operation of a memory module with power management system thereof, including: a base power plane; a power management circuit electrically connected to the base power plane; a managed power plane electrically connected to the base power plane only through the power management circuit; and a memory array electrically connected to the managed power plane.

Abstract: Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host processor to communicate with a plurality of memory devices in a memory stack as a single device, regardless of an actual number of memory devices within the memory stack. Power is provided to a single one of the plurality of the memory devices in the memory stack at a time to reduce power consumption. Other methods, apparatuses, and devices are also disclosed.

Abstract: Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory.

Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.

Abstract: A PV system composed of sub-arrays, each having a group of PV cells that are electrically connected to each other. A power management circuit for each sub-array has a communications interface and serves to connect or disconnect the sub-array to a programmable power grid. The power grid has bus rows and bus columns. A bus management circuit is positioned at a respective junction of a bus column and a bus row and is programmable through its communication interface to connect or disconnect a power path in the grid. As a result, selected sub-arrays are connected by selected power paths to be in parallel so as to produce a low system voltage, and, alternately in series so as to produce a high system voltage that is greater than the low voltage by at least a factor of ten.

Abstract: This application discusses, among other things apparatus and methods for a voltage boost circuit. In an example, a voltage boost circuit can include first and second inverters, sharing a first supply node, and sharing a second supply node, a first charge transfer capacitor, configured to couple a first clock signal to the first inverter output, a second charge transfer capacitor, configured to couple a second clock signal to the second inverter output, the second clock signal being out-of-phase with the first clock signal, a first gate drive capacitor, configured to couple the first clock signal to the second inverter input, and a second gate drive capacitor, configured to couple the second clock signal to the first inverter input.

Abstract: A voltage generation circuit may include: a comparison unit configured to compare a reference voltage and a feedback voltage and output a comparison signal to a node; an output unit configured to generate an internal voltage and the feedback voltage according to a voltage level applied to the node; and a control unit configured to discharge the node when a level of the internal voltage drops to less than a preset level.

Abstract: A chain of switches is connected between a first power supply line coupled to a first voltage and a second power supply line coupled to the sector. These switches are controllable by a control signal. The control signal is propagated from a first end of the first chain towards a second end of the first chain without control of the switches during this first propagation. The control signal is then propagated in the reverse direction from the second end towards the first end with a control of the switches during this second propagation starting from a group of at least one switch situated at the second end. There is a detection of the arrival of the control signal at the first end of the chain at the end of its propagation in the reverse direction.

Abstract: A system and method are provided for sharing capacitance. The system may include a first electronic entity with a capacitor having capacitance. The system may further include a switched path in the first electronic entity. The switched path may have a first switched position in which the switched path provides the capacitance to a voltage using device in first electronic entity. The switched path may also have a second switched position in which the switched path provides the capacitance to a second electronic entity. The switched path may also have a third switched position in which the switched path provides the capacitance to both the voltage-using device in the first electronic entity and the second electronic entity.

Abstract: A semiconductor device that includes first to fourth banks spaced apart from each other in first and second directions, column control regions extending in the second direction between the first bank and the second bank and between the third bank and the fourth bank, and suitable for controlling column operations of the first to fourth banks, at least one power supply/ground voltage line extending in the second direction at one side edge of the first to fourth banks adjacent to the column control regions, and at least one power supply/ground voltage pad adjacent to and coupled with the at least one power supply/ground voltage line between the first bank and the third bank and between the second bank and the fourth bank, and suitable for receiving an external power supply voltage and a ground voltage.

Abstract: Methods and apparatus relating to detecting access to powered down devices are described. In one embodiment, the power status of a device is determined based on a memory address corresponding to a data access request initiated by a processor or processor core. Access to a storage device, corresponding to the device, is controlled based on the power status of the device, e.g., to avoid random system hanging or crashes that may be hard to reproduce or debug. Other embodiments are also disclosed and claimed.

Abstract: A method of protecting data of a flash memory is provided. The method includes detecting primary power applied to the flash memory, and applying secondary power converted from the primary power to the flash memory. The primary power is compared to first and second values, and a writing-protection pin of the flash memory is enabled when the detected primary power reaches a predetermined value.

Abstract: According to one embodiment, a memory system includes a non-volatile first storage unit, a second storage unit, a third storage unit, and a controller. The controller is configured to selectively execute, following transition to a first mode, either a procedure of writing data of the second storage unit in the third storage unit, or a procedure of writing data of the third storage unit in the first storage unit while reducing power feed to the first and third storage units.

Abstract: A non-volatile storage system includes a plurality of non-volatile storage elements, a plurality of bit lines connected to the non-volatile storage elements, a plurality of word lines connected to the non-volatile storage elements, and one or more control circuits connected to the bit lines and word lines. The one or more control circuits perform programming, verifying, reading and erasing for the non-volatile storage elements. When verifying, a first subset of bit lines connected to non-volatile storage elements are charged to allow for sensing, while a second subset of bit lines are not charged. When reading, a two strobe sensing process is selectively used to more accurately read data from the non-volatile storage elements.

Abstract: To provide a semiconductor device having a novel structure. To provide a semiconductor device excellent in reducing power consumption. A memory cell including an SRAM capable of backing up data to the nonvolatile memory and a peripheral circuit of the memory cell are configured to offer different power gating states. In a first period, which is extremely short, the bit line is brought into an electrically floating state by turning off the switch. In a second period, which is longer than the first period, power gating is performed on the memory cell. In a third period, which is longer than the second period, power gating is performed on the memory cell and the peripheral circuits.

Abstract: A memory apparatus includes a data receiver, a data delay unit, a strobe output unit, and a data latch unit. The data receiver may receive a plurality of symbols and generate a plurality of data and a data strobe signal. In response to a command and address signals, the data delay unit may variably delay the plurality of data and generate a plurality of delayed data. The strobe output unit may generate an internal strobe signal by delaying the data strobe signal by a predetermined delay time. The data latch unit may generate internal data from the plurality of delayed data in synchronization with the internal strobe signal.

Abstract: An energy recycling system and an energy recycling method are disclosed. The energy recycling system includes several working circuits and a first energy recycling circuit. The working circuits include at least one first working circuit and at least one second working circuit. The first energy recycling circuit is coupled between the first working circuits and the second working circuits. The first alternating-current-type (AC-type) voltage source is supplied to the first working circuits and the second working circuits. The energy loss of the first AC-type voltage source is replenished by a direct-current-type (DC-type) voltage source. The first energy recycling circuit includes an inductor and pairs of switches, and the pairs of switches are configured for conducting in different time sequences and transferring the energy of the first AC-type voltage source between the first working circuits, the inductor and the second working circuits.

Abstract: Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with the capacitor. The capacitors may be metal-insulator-metal (MIM) capacitors. The resistor in each cell may limit the current through an individual capacitor in the event of a short in the capacitor due to a dielectric defect.

Abstract: A memory includes BLs and WLs. Resistance-change memory elements are connected between the BLs and the WLs via selection gates, respectively. A BL driver applies a voltage to a selected BL among the BLs. A WL driver applies a voltage to a selected WL among the WLs. In a write operation, the BL driver and the WL driver apply a first voltage between a reference voltage and a write voltage to selection candidate memory elements connected to the selected BL or the selected WL among the memory elements to bring the selection candidate memory elements to a half-selected state. The BL driver and the WL driver apply a second voltage to the selection candidate memory elements in the half-selected state at different timings, respectively, in order to bring the selection candidate memory elements to a write state and then return the selection candidate memory elements to the half-selected state.

Abstract: An electronic control apparatus as one of nodes connected to a communication line includes a microcomputer, a power integrated circuit for controlling power supply to the microcomputer, and a timer adjuster. The power integrated circuit has a timer for measuring a time period during which no data flows through a communication line. The timer is reset, when no data flows through the communication line and then data flows through the communication line. The power integrated circuit starts power supply to the microcomputer, when data flows through the communication line. The power integrated circuit stops the power supply when the timer reaches a threshold value. The timer adjuster prevents the timer from reaching the threshold value until the microcomputer completes a shutdown process.

Abstract: A charge pump device is disclosed. The charge pump device includes a driving stage, for generating a driving signal corresponding to a driving capability; a charge pump circuit, for generating an output voltage according to the driving signal; a comparing circuit, comprising a first comparator for comparing the output voltage and a first reference voltage to generate a first comparing result; an overload detection circuit, for generating a detection result according to at least one of the first comparing result and the output voltage; and a driving capability control circuit, coupled between the overload detection circuit and the driving stage for controlling the driving capability corresponding to the driving signal according to the detection result.

Abstract: The disclosure provides a power supply circuit including a pulse width modulator (PWM), a first voltage conversion unit, a second voltage conversion unit, a conversion chip, and a delay unit. The first voltage conversion unit converts a voltage of a power supply to a first voltage according to pulse signals output by the PWM. The second voltage conversion unit converts the voltage of the power supply to a second voltage according to the pulse signals. The conversion chip converts the first voltage to a third voltage, converts the second voltage to a fourth voltage, and outputs a power-good signal to a south bridge chipset through the delay unit. The disclosure also provides a notebook computer including the power supply circuit.