Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract: A magnetic random access memory (MRAM) cell including an MRAM cell stack located over a substrate and first and second write lines spanning opposing termini of the MRAM cell stack. At least one of the first and second write lines includes at least one first portion spanning the MRAM cell stack and at least one second portion proximate the MRAM cell stack. The first and second portions have first and second cross-sectional areas, respectively, wherein the first cross-sectional area is substantially less than the second cross-sectional area.

Abstract: An apparatus includes a low magnetic-coercivity layer of material (LMC layer) having a majority electron-spin-polarization (M-ESP), an energy-gap coupled with the LMC layer, wherein a flow of spin-polarized electrons having an electron-spin-polarization anti-parallel to the LMC layer are injected via the energy-gap, to change the M-ESP of the LMC layer. A non-magnetic material is in electrical communication with the LMC layer and provides a spin-balanced source of current to the LMC layer, responsive to the injection of spin-polarized electrons into the LMC layer.

Abstract: In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, and a data read current is supplied thereto. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, whereby the data read speed can be increased.

Abstract: A magnetic random-access memory (MRAM) cell according to an embodiment of the invention is disclosed that comprises a magnetic storage element having an easy axis and a hard axis, a write conductor positioned along one of the easy axis and the hard axis, and a write conductor positioned at a non-parallel and non-perpendicular angle to both of the easy axis and the hard axis.

Abstract: A magnetoresistive multi-level generator including a first series circuit with a first magnetoresistive element having a resistance equal to Rmax connected in series with n first magnetoresistive elements each having a resistance equal to Rmin. Where n is equal to a whole integer greater than one, n additional series circuits, each including an additional magnetoresistive element with a resistance equal to Rmax connected in series with n magnetoresistive elements each with a resistance equal to Rmin. The first and n additional series circuits being connected in series between the input and output terminals and in parallel with each other. Whereby a total resistance between the input and output terminals is a level Rmin+&Dgr;R/n, where &Dgr;R is equal to Rmax−Rmin.

Abstract: MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SC1 and SC2. The sub-cell SC1 includes magneto resistive elements MTJ1 and MTJ2 and a selection transistor Tr1, and the sub-cell SC2 includes magneto resistive elements MTJ3 and MTJ4 and a selection transistor Tr2. The magneto resistive elements MTJ1 and MTJ2 are connected in parallel, and the magneto resistive elements MTJ3 and MTJ4 are also connected in parallel. Further, the sub-cells SC1 and SC2 are connected in series between the write/read bit line BLW/R and the ground.

Abstract: MTJ elements are accumulated in a plurality of portions on a semiconductor substrate. Upper lines and lower lines extending in the X direction are connected to the MTJ elements. The number of MTJ elements arranged in each portion is gradually increased from a lower portion towards an upper portion. With respect to the upper lines, the upper lines arranged in the lower portion are connected to transistors present near an array of the MTJ elements, and the upper lines arranged in the upper portion are connected to transistors distant from the array of the MTJ elements. Also with respect to the lower lines, the lower lines in the lower portion are connected to transistors nearer to the array of the TRM elements than the lower lines in the upper portion.

Abstract: A magnetic random access memory circuit comprises a plurality of magnetic memory cells, each of the memory cells including a magnetic storage element having an easy axis and a hard axis associated therewith, and a plurality of column lines and row lines for selectively accessing one or more of the memory cells, each of the memory cells being proximate to an intersection of one of the column lines and one of the row lines. Each of the magnetic memory cells is arranged such that the easy axis is substantially parallel to a direction of flow of a sense current and the hard axis is substantially parallel to a direction of flow of a write current.

Abstract: A magnetic random access memory array includes a data storage layer having an easy axis. A non-linear first conductor is positioned on a first side of the data storage layer, wherein a portion of the first conductor has an angle of orientation that is perpendicular to the easy axis. A non-linear second conductor is positioned on a second side of the data storage layer, wherein a portion of the second conductor also has an angle of orientation that is perpendicular to the easy axis.

Abstract: In a method for operating an MRAM semiconductor memory configuration, for the purpose of reading an item of stored information, reversible magnetic changes are made to the TMR cell and a current that is momentarily altered as a result is compared with the original read signal. As a result, the TMR memory cell itself can serve as a reference, even though the information in the TMR memory cell is not destroyed, i.e. writing-back does not have to be effected. The method can preferably be applied to an MRAM memory configuration in which a plurality of TMR cells are connected, in parallel, to a selection transistor and in which there is a write line which is not electrically connected to the memory cell.

Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.

Abstract: A memory cell of a data storage device includes serially-connected first and second magnetoresistive devices. The first magnetoresistive device has first and second resistance states. The second magnetoresistive device has third and fourth resistance states. The four resistance states are detectably different.

Abstract: The present invention discloses a magnetic random access memory for reading two or more data, by sensing the current flowing into source and drain regions. The current is regulated by the amount of a current flowing through an MRJ in an MRAM cell according to a word line voltage. In order to accomplish this object of the present invention, the MRAM comprises a data detecting circuit for converting a current flowing through an MTJ in the MRAM cell into a voltage and detecting data resulting in magnetization orientation ge.

Abstract: A thin film magnetic memory device includes an antenna section transmitting and receiving a radio wave to an from an outside of the thin film magnetic memory device. An inductance wiring constituting the antenna section has a metal wiring, and a magnetic film formed to correspond to a lower surface portion of the metal wiring or lower surface and side surface portions of the metal wiring. The magnetic film is formed in an original manufacturing step of the thin film magnetic memory device without providing a dedicated manufacturing step.

Abstract: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.

Abstract: MTJ elements are accumulated in a plurality of portions on a semiconductor substrate. Upper lines and lower lines extending in the X direction are connected to the MTJ elements. The number of MTJ elements arranged in each portion is gradually increased from a lower portion towards an upper portion. With respect to the upper lines, the upper lines arranged in the lower portion are connected to transistors present near an array of the MTJ elements, and the upper lines arranged in the upper portion are connected to transistors distant from the array of the MTJ elements. Also with respect to the lower lines, the lower lines in the lower portion are connected to transistors nearer to the array of the TRM elements than the lower lines in the upper portion.

Abstract: In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, and a data read current is supplied thereto. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, whereby the data read speed can be increased.

Abstract: An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the fixed magnetic layer and the soft magnetic layer. The MRAM cells are all formed simultaneously and at least some of the MRAM cells are designed to function as antifuse devices whereby the application of a selected electrical potential can short the antifuse device to thereby affect the functionality of the MRAM device.

Abstract: A problem associated with the programming of MRAM (magnetic random access memory) has been that the required current is orders of magnitude larger than that needed for many other memory devices such as SRAMs or DRAMs. This problem has been overcome by adding heating lines to the standard array configuration. These lines provide local heating sources located in close proximity to the memory elements so that when a given element is being programmed it is also being heated. The effect of the heating is to lower the threshold for magnetization so that a lower field (and hence reduced program current) can be used. It is also possible to make the base layer of the memory element itself serve as the heating element.

Abstract: An apparatus includes a low magnetic-coercivity layer of material (LMC layer) having a majority electron-spin-polarization (M-ESP), an energy-gap coupled with the LMC layer, wherein a flow of spin-polarized electrons having an electron-spin-polarization anti-parallel to the LMC layer are injected via the energy-gap, to change the M-ESP of the LMC layer. A non-magnetic material is in electrical communication with the LMC layer and provides a spin-balanced source of current to the LMC layer, responsive to the injection of spin-polarized electrons into the LMC layer.

Abstract: An improved magnetic memory element is provided in which a magnetic sense layer is formed of two ferromagnetic material layers separated by a spacer layer. The two ferromagnetic layers are formed as a synthetic ferrimagnet with stray field coupling and antiferromagnetic exchange coupling across the spacer layer.

Abstract: A method and apparatus are provided for storing and retrieving data in a non-volatile manner. The data is stored in a magnetic cell having a magnetic moment with a direction. A conductor is positioned near the cell and carries a current formed by a current driver. A data detector detects a value for data stored in the cell based on a level of current driven through the conductor.

Abstract: A resistive memory device (40) and method of manufacturing thereof including magnetic memory cells (14) having a second magnetic layer (20) including at least a first and second material (24/26). The Curie temperature of the second material (26) is lower than the Curie temperature of the first material (24). A plurality of non-continuous second conductive lines (22) are disposed over the magnetic memory cells (14). A current (28) may be run through the second conductive lines (22) to increase the temperature of the second material (26) to a temperature greater than the second material (26) Curie temperature, causing the second material (26) to lose its ferromagnetic properties, providing increased write selectivity to the memory array (40).

Abstract: A magnetic random access memory (MRAM) having an MTJ cell located between a word line and a gate oxide film, a reference voltage line in a source junction region, and a connection line in a drain junction region. The constitution and fabrication process of the MRAM are simplified to improve productivity and properties of the device.

Abstract: The invention includes an apparatus and a method that provides a shared global word line MRAM structure. The MRAM structure includes a first bit line conductor oriented in a first direction. A first sense line conductor is oriented in a second direction. A first memory cell is physically connected between the first bit line conductor and the first sense line conductor. A global word line is oriented in substantially the second direction, and magnetically coupled to the first memory cell. A second bit line conductor is oriented in substantially the first direction. A second sense line conductor is oriented in substantially the second direction. A second memory cell is physically connected between the second bit line conductor and the second sense line conductor. The global word line is also magnetically coupled to the second memory cell. The first memory cell and the second memory cell can be MRAM devices.

Abstract: The present disclosure relates to a solid-state storage device. In one arrangement, the storage device comprises a memory device comprising one of an atomic resolution storage (ARS) device and a magnetic random access memory (MRAM) device, a controller, and an integral connector that is used to directly connect the storage device to another device.

Abstract: A configuration and method for low-loss writing of an MRAM includes setting voltages at bit lines and word lines such that the voltage across the memory cells between a selected word/bit line and the individual bit line/word lines is minimal. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the memory cell and voltages at the bit/word lines are set to minimize a cell voltage across the memory cells between a selected word/bit line and individual bit/word lines. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the particular cell, and, when a voltage V1 and a voltage V2<V1 are present at a respective end of the selected word line/bit lines, the cell field is configured to have all of the bit/word lines set to voltages (V1+V2)/2 and to have a maximum cell voltage of ±(V1−V2)/2.

Abstract: A method is provided for electrically coupling a magnetoresistive memory MRAM circuit component to a host component. The method includes keeping the temperature of the MRAM circuit component below about 200° C. while aligning at least one interface feature of the MRAM circuit component with at least one interface feature of the host component and electrically coupling the interface features using a z-axis conductive material. In certain exemplary implementations, the temperature of the magnetoresistive memory circuit component is keep below about 180° C. It has been found that lower temperatures such as these eliminate the need to conduct additional MRAM annealing processes to re-set/re-pin a selected magnetic direction in certain materials within the MRAM.

Abstract: The invention includes an apparatus and a method that provides a shared global word line MRAM structure. The MRAM structure includes a first bit line conductor oriented in a first direction. A first sense line conductor is oriented in a second direction. A first memory cell is physically connected between the first bit line conductor and the first sense line conductor. A global word line is oriented in substantially the second direction, and magnetically coupled to the first memory cell. A second bit line conductor is oriented in substantially the first direction. A second sense line conductor is oriented in substantially the second direction. A second memory cell is physically connected between the second bit line conductor and the second sense line conductor. The global word line is also magnetically coupled to the second memory cell. The first memory cell and the second memory cell can be MRAM devices.

Abstract: A method is provided for electrically coupling a magnetoresistive memory MRAM circuit component to a host component. The method includes keeping the temperature of the MRAM circuit component below about 200° C. while aligning at least one interface feature of the MRAM circuit component with at least one interface feature of the host component and electrically coupling the interface features using a z-axis conductive material. In certain exemplary implementations, the temperature of the magnetoresistive memory circuit component is kept below about 180° C. It has been found that lower temperatures such as these eliminate the need to conduct additional MRAM annealing processes to re-set/re-pin a selected magnetic direction in certain materials within the MRAM.

Abstract: A memory device comprising a plurality of bit lines and a plurality of word lines forming a cross-point array. A memory cell is located at each of the cross-points in the array. A bit decoder and word decoder are coupled to the bit lines and word lines, respectively. A first series of switch circuits are coupled to and located along the adjacent bit lines resulting in the array being divided into segments along the adjacent bit lines such that a shortened programming current path is provided which results in decreased resistance across the device.

Abstract: An MRAM device (200) and method of manufacturing thereof having second conductive lines (228) with a narrow width. The second conductive lines (228) partially contact the resistive memory elements (214), reducing leakage currents in neighboring cells (214).

Abstract: A self-aligned magnetic clad bit line structure (274) for a magnetic memory element (240a) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure (274) extends within a trench (258) and includes a conductive material (250), magnetic cladding sidewalls (262) and a magnetic cladding cap (252). The magnetic cladding sidewalls (262) at least partially surround the conductive material (264) and the magnetic cladding cap (252) is substantially recessed within the trench with respect to the top of the trench.

Abstract: The present invention provides a memory cell array structure comprising: a plurality of cell array blocks aligned in matrix in both the row and column directions, and each of the cell array blocks including a plurality of magnetic memory cells; a plurality of main word lines being connected through sub-word switching devices to the same number of sub-word lines as a first number of the cell array blocks aligned in the row direction, and each of the sub-word lines being connected to at least one of the magnetic memory cells; and a plurality of main bit lines being connected through sub-bit switching devices to the same number of sub-bit lines as a second number of the cell array blocks aligned in the column direction, and each of the sub-bit lines being connected to at least one of the magnetic memory cells.

Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.

Abstract: An architecture for a magnetoresistive random access memory (MRAM) storage cell 300 with reduced parasitic effects is presented. An additional runs of metal laid in parallel to both the wordline 310 and the bitlines 320 of the MRAM device provide a write wordline 345 and a write bitline 355 are separated from the wordline and the bitline by a dielectric layer 340 and 350 provides electrical isolation of the write currents from the magnetic stacks. The electrical isolation of the write wordline 345 and bitlines 355 reduces the parasitic capacitance, inductance, and resistance seen by the wordline and bitlines during the write operation. The wordline 310 and bitlines 320 remain as in a standard MRAM cross-point array architecture and is dedicated for reading the contents of the MRAM storage cell.

Abstract: A magnetic memory device for selectively writing one or more memory cells in the memory device includes a plurality of global write lines for selectively conveying a destabilizing current, the global write lines being disposed from the memory cells such that the destabilizing current passing through the global write lines does not destabilize unselected memory cells in the memory device, each global write line including a plurality of segmented write lines operatively connected thereto. The memory device further includes a plurality of segmented groups, each segmented group including a plurality of memory cells operatively coupled to a corresponding segmented write line, each segmented write line being disposed in relation to the plurality of corresponding memory cells such that the destabilizing current passing through the segmented write line destabilizes the corresponding memory cells for writing.

Abstract: The fabrication process of a conventional MRAM using a magnetoresistive effect element as a memory device is difficult, and the device structure makes it difficult to decrease the cell area and increase the degree of integration. It is an object of this invention to realize an MRAM which can achieve a high integration degree. A memory device is characterized by including a magnetoresistive element, a bit line formed above this magnetoresistive element, and a write line. The magnetoresistive element is formed immediately above the drain region of a field-effect transistor.

Abstract: A structure and method for forming a magnetic memory having a number N of levels of magnetic memory cells by forming a plurality of levels of magnetic memory cells, each level including at least one magnetic memory core structure having first and second surfaces, forming a first access conductor connecting to the first surface, forming a second access conductor connecting to the second surface, wherein N+1 access conductors are formed per number N of levels of magnetic memory cells. The structure comprises a plurality of levels of magnetic memory cells, each level including at least one magnetic memory having a number N of levels of magnetic memory cells, including a magnetic memory core structure having first and second surfaces, the first and second surfaces each connecting to an individual access conductor, wherein N+1 access conductors are employed per number N of levels of magnetic memory cells.

Abstract: An MRAM memory array has nonlinear word lines and linear bit lines. The word lines cross the bit lines at memory cell locations, and are substantially coextensive with the bit lines at the crossing points. When a current is passed through the word and bit lines, the magnetic fields generated by the word line and the bit line at a coextensive portion are substantially aligned. The magnitude of the resultant field is therefore greater than in conventional, orthogonally oriented fields. Because the addition of the fields generated by the word and bit lines is enhanced, smaller word and bit line currents can be utilized, which reduces the size required for the memory array. The memory array can also utilize memory cells having a magnetic layer for producing a transverse magnetic field. The transverse field is orthogonally oriented to the magnetic field generated by the word and bit lines, and increases the reproducibility of switching of the memory cell.

Abstract: MRAM memory having a memory cell array (2) comprising magnetoresistive memory components (6a, 6b) arranged in at least one memory cell layer above a semiconductor substrate (4), word lines (7) and bit lines (8, 9) for making contact with the magnetoresistive memory components (6a, 6b) in the memory cell array (2); and having a drive logic arrangement (5a, 5b, 5c) for driving the magnetoresistive memory components (6a, 6b) in the memory cell array (2) via the word and bit lines (7, 8, 9), the drive logic arrangement (5a, 5b, 5c) being integrated below the memory cell array (2) in and on the semiconductor substrate (4).

Abstract: The invention described herein defines a system and a method for selectively controlling the sensitivity of a region of a magnetoresistive element to an incident magnetic field, by applying an external magnetic field to the magnetoresistive element. A number of applications to non-volatile data storage are described, as is a magnetic sweep element based on a FET structure. Finally, the storage media and recording modes (in-plane vs. perpendicular) best suited to the proposed applications are analyzed, and the desired or optimal characteristics of the proposed devices are discussed.

Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.

Abstract: A write circuit for a large array of memory cells of a Magnetic Random Access Memory (“MRAM”) device. The write circuit can provide a controllable, bi-directional write current to selected word and bit lines without exceeding breakdown limits of the memory cells. Additionally, the write circuit can spread out the write currents over time to reduce peak currents.

Abstract: A ferromagnetic tunnel junction random access memory includes a ferromagnetic tunnel junction structure including a first ferromagnetic layer, a second ferromagnetic layer disposed adjacent to the first ferromagnetic layer and having a fixed magnetization, and a tunnel insulator layer interposed between the first and second ferromagnetic layers; a conductor plug penetrating the first ferromagnetic layer, the tunnel insulator layer and the second ferromagnetic layer along a center axis; a first selection line coupled to a first end of the conductor plug; and a second selection line coupled to a second end of the conductor plug opposite to the first end. The first ferromagnetic layer has a generally ring shape surrounding the conductor plug and is insulated from the conductor plug. One of the first and second ferromagnetic layers has an antiferromagnetic layer pattern on a portion thereof.

Abstract: A Hall effect ferromagnetic non-volatile random access memory cell comprising a Hall effect sensor adjacent to a ferromagnetic bit which is surrounded by a drive coil. The coil is electrically connected to a drive circuit, and when provided with an appropriate current creates a residual magnetic field in the ferromagnetic bit, the polarity of which determines the memory status of the cell. The Hall effect sensor is electrically connected via four conductors to a voltage source, ground, and two read sense comparator lines for comparing the voltage output to determine the memory status of the cell. The read and write circuits are arranged in a matrix of bit columns and byte rows. A method for manufacturing said Hall effect ferromagnetic non-volatile random access memory cell.

Abstract: An architecture for selectively writing one or more magnetic memory cells in a magnetic random access memory (MRAM) device comprises at least one write line including a global write line conductor and a plurality of segmented write line conductors connected thereto, the global write line conductor being substantially isolated from the memory cells.

Abstract: A write circuit for a large array of memory cells of a Magnetic Random Access Memory (“MRAM”) device. The write circuit can provide a controllable, bi-directional write current to selected word and bit lines without exceeding breakdown limits of the memory cells. Additionally, the write circuit can spread out the write currents over time to reduce peak currents.

Abstract: A magnetic storage cell includes an active layer and a reference layer which is structured to minimize disruptions to magnetization in its active layer. The reference layer is structured so that a pair of its opposing edges overlap a pair of corresponding edges of the active layer. This may be used minimize the effects of demagnetization fields on the active layer. In addition, the reference layer may be thinned at its opposing edges to control the effects of coupling fields on the active layer and balance the demagnetization field.