Abstract: A magnetic random access memory (MRAM) device disclosed herein includes an array of magnetic memory cells having magnetoresistive (MR) stacks. The MRAM array also includes a series of bit lines and word lines coupled to the MR stacks. The array layout provides for reduced crosstalk between neighboring memory cells by increasing a distance between neighboring MR stacks along a common conductor without increasing the overall layout area of the MRAM array. Several embodiments are disclosed where neighboring MR stacks are offset such that the MR stacks are staggered. For example, groups of MR stacks coupled to a common word line or to a common bit line can be staggered. The staggered layout provides for increased distance between neighboring MR stacks for a given MRAM array area, thereby resulting in a reduction of crosstalk, for example during write operations.

Abstract: An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

Abstract: A horizontally disposed elliptical or rectangular magnetic memory cell includes at least two conductive lines to carry current and a magnetic element disposed between the conductive lines. The current through the conductive lines induces a magnetic field, such that the magntic element is directly accessible. The magnetic memory cell can be sensed with a GMR head.

Abstract: The present invention generally relates to the field of magnetic devices for memory cells that can serve as non-volatile memory. More specifically, the present invention describes a high speed and low power method by which a spin polarized electrical current can be used to control and switch the magnetization direction of a magnetic region in such a device. The magnetic device comprises a pinned magnetic layer with a fixed magnetization direction, a free magnetic layer with a free magnetization direction, and a read-out magnetic layer with a fixed magnetization direction. The pinned magnetic layer and the free magnetic layer are separated by a non-magnetic layer, and the free magnetic layer and the read-out magnetic layer are separated by another non-magnetic layer. The magnetization directions of the pinned and free layers generally do not point along the same axis. The non-magnetic layers minimize the magnetic interaction between the magnetic layers.

Abstract: Memory cell arrays include a data cell array, a reference cell array and a dummy cell array. First read word lines are connected respectively to the gates of the read selection switches of the data cells. Second read word lines are connected respectively to the gates of the read selection switches of the reference cells. The gates of the read selection switches of the dummy cells are also connected respectively to the first and second read word lines but the dummy cells do not function as memory cells because the read selection switch and the MTJ element are cut apart in each of the dummy cells.

Abstract: Line drivers that fit within a specified line pitch. One method of placing line drivers completely underneath a cross point array requires splitting the line driver up so that a portion of the line drivers is on a first side of the cross point array and the other portion is on the opposite side. However, using this technique requires that the width of the drivers is no larger than the width of the memory cells that are being driven. This can be accomplished by stacking transistors such that line drivers fit within a specified line pitch, but are as long as is necessary to include all the necessary circuitry.

Abstract: An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.

Abstract: A semiconductor memory device includes memory cell arrays, word lines, sub-sense lines, main sense line, row decoders, column decoders, first switch elements, read circuit, and write circuit. Each memory cell array has a matrix of memory cells including magnetoresistive elements. Each magnetoresistive element has first and second magnetic layers and a first insulating layer formed between the first and second magnetic layers. The word line is connected to the first magnetic layers on each row. The sub-sense line is connected to the second magnetic layers on each column. The main sense line is connected to each sub-sense line. The row decoder and column decoder select a word line and sub-sense line. The first switch element connects the sub-sense line selected by the column decoder to the main sense line. The read circuit reads out data from a memory cell. The write circuit writes data in a memory cell.

Abstract: MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SC1 and SC2. The sub-cell SC1 includes magneto resistive elements MTJ1 and MTJ2 and a selection transistor Tr1, and the sub-cell SC2 includes magneto resistive elements MTJ3 and MTJ4 and a selection transistor Tr2. The magneto resistive elements MTJ1 and MTJ2 are connected in parallel, and the magneto resistive elements MTJ3 and MTJ4 are also connected in parallel. Further, the sub-cells SC1 and SC2 are connected in series between the write/read bit line BLW/R and the ground.

Abstract: An apparatus includes a low magnetic-coercivity layer of material (LMC layer) having a majority electron-spin-polarization (M-ESP), an energy-gap coupled with the LMC layer, wherein a flow of spin-polarized electrons having an electron-spin-polarization anti-parallel to the LMC layer are injected via the energy-gap, to change the M-ESP of the LMC layer. A non-magnetic material is in electrical communication with the LMC layer and provides a spin-balanced source of current to the LMC layer, responsive to the injection of spin-polarized electrons into the LMC layer.

Abstract: Normal memory cells are arranged in rows and columns, and dummy memory cells are arranged to form dummy memory cell rows by sharing memory cell columns with the normal memory cells. When there is at least one defect in the normal memory cells and/or the dummy memory cells, replacement/repair is carried out using a redundant column in a unit of memory cell column. The redundant column includes not only spare memory cells for repair of the normal memory cells but also spare dummy memory cells for repair of the dummy memory cells.

Abstract: A defect management enabled PIRM including a data storage medium providing a plurality of cross point data storage arrays. Each array provides a plurality of memory cells. The arrays are allocated into separate super arrays, the separate super arrays virtually aligned as sets. A controller is also provided, capable of establishing the selection of a virtually aligned set of arrays and a virtually aligned set of memory cells. The controller is operable during a write operation to receive a word of data bits and detect a defective array in the selected virtually aligned set of memory arrays. The controller is further capable of directing the allocation of at least one data bit from the defective memory array to a spare memory array.

Abstract: A magnetic random-access memory (MRAM) cell according to an embodiment of the invention is disclosed that comprises a magnetic storage element having an easy axis and a hard axis, a write conductor positioned along one of the easy axis and the hard axis, and a write conductor positioned at a non-parallel and non-perpendicular angle to both of the easy axis and the hard axis.

Abstract: An MRAM memory array includes a set of memory cell strings wherein each memory cell string has a voltage divider input, a bit-sense output, a voltage divider ground, and a bit-sense output control, a shared switched voltage line that is capable of applying a voltage to the voltage divider inputs of the memory cell strings in the set, a common bit-sense line operatively coupled to the bit-sense outputs of the memory cell strings, a bit-sense output control line that is capable of selectively connecting the bit-sense output of a memory cell string to the common bit-sense line, and a ground operatively coupled to the voltage divider grounds of the voltage divider grounds.

Abstract: An MRAM cell including an MRAM cell stack located over a substrate and first and second write lines spanning at least one side of the MRAM cell stack and defining a projected region of intersection of the MRAM cell stack and the first and second write lines. The MRAM cell stack includes a pinned layer, a tunneling barrier layer, and a free layer, the tunneling barrier layer interposing the pinned layer and the free layer. The first write line extends in a first direction within the projected region of intersection. The second write line extends in a second direction within the projected region of intersection. The first and second directions are angularly offset by an angle ranging between 45 and 90 degrees, exclusively. At least one write line may be perpendicular to the easy axis of free layer, while the other line may be rotated off the easy axis of the free layer by an angle which is larger than zero, such as to compensate for a shifting astroid curve.

Abstract: A closed flux magnetic memory cell has a ferromagnetic pinned structure and a ferromagnetic free structure. Data is stored by controlling the relative magnetization between the pinned and free structures. The free structure is formed as a horizontally extending toroid, or tube, that is insulated from the pinned structure. A first conductive line passes through the center of the free structure while a second conductive line is connected to the pinned structure. A third conductive line can be formed through the free structure. This line is insulated from the toroid and the first conductor. The third conductive line can also be located outside the free structure. In operation of one embodiment, the first and third conductive lines are used to control the magnetized direction of the free structure. A resistance between the first and second conductive lines defines the data stored in the memory cell.

Abstract: A multiple-memory-layer magnetic random access memory (MRAM) has multiple memory layers arranged as pairs and stacked on a substrate. The first memory layer in the pair comprises a plurality of rows of memory cells located between electrically conductive access lines, and the second memory layer in the pair is substantially identical to the first memory layer, but is rotated about an axis perpendicular to the substrate so that the access lines and memory cell rows in one memory layer of the pair are orthogonal to their counterpart lines and rows in the other memory layer. The memory cells in each layer are aligned vertically (perpendicular to the substrate) with the memory cells in the other layer, with the vertically aligned memory cells forming memory cell columns that extend perpendicularly from the substrate. Each memory cell column has an electrical switch between the lowermost memory cell and the substrate.

Abstract: For writing K-bit write data in parallel (K is integer at least 2), bit lines each arranged for each memory cell columns and at least K current return lines are provided. K selected bit lines to write the K-bit write data are connected in series in a single current path. When data having different levels are written through adjacent selected bit lines, the selected bit lines are connected to each other at their one ends or the other ends, so that a bit line write current flowing through the former selected bit line is directly transmitted to the latter selected bit line. On the other hand, when data having the same level are written through adjacent selected bit lines, a bit line write current flowing through the former selected bit line is turned back by the corresponding current return line, and then transmitted to the latter selected bit line.

Abstract: A read block is formed from a plurality of TMR elements stacked in the vertical direction. One terminal of each TMR element in the read block is connected to a source line through a read select switch. The source line extends in the Y-direction and is connected to a ground point through a column select switch. The other terminal of each TMR element is independently connected to a corresponding one of read/write bit lines. Each read/write bit line extends in the Y-direction and is connected to a read circuit through the column select switch.

Abstract: A memory cell is constituted by a TMR element and a MOS transistor. The source diffusion layer of the MOS transistor is connected to a source line and the drain diffusion layer of the transistor is connected to a TMR element via a local interconnection wire. The TMR element is held between the local interconnection wire and a bit line. The TMR element is constituted by stacked TMR layers. Each TMR layer is able to have two states, that is, a state in which spin directions are parallel and anti-parallel. Therefore, the TMR element stores four-value data. A current-driving line is set immediately below the TMR element.

Abstract: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline).

Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.

Abstract: Methods and apparatuses are disclosed for retrieving data stored in a magnetic integrated memory. In one embodiment, the method includes applying a perturbing hard-axis magnetic field to a magnetic element in a magnetic integrated memory and detecting a change in an electrical parameter caused by said perturbing hard-axis magnetic field.

Abstract: This invention relates to an array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of cells each column being provided in a respective stacked memory layer.

Abstract: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated magnetic memory structures. In one aspect, the present teachings relate to magnetic memory structure fabrication techniques in a high density configuration that includes an efficient means for programming high density magnetic memory structures.

Abstract: An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.

Abstract: The present invention relates to a magnetic ring unit and a magnetic memory device; an object of the invention is to control the direction of rotation of the magnetic flux freely and with high reproducibility in a simple structure without using a thermal process such as pinning; and a magnetic ring unit is formed of a magnetic ring in eccentric ring form where the center of the inner diameter is located at a decentered position relative to the center of the outer diameter.

Abstract: A single transistor type magnetic random access memory device and a method of operating and manufacturing the same, wherein the single transistor type magnetic random access memory device includes a substrate, first and second doped regions spaced apart from each other, a gate dielectric layer on a portion of the semiconductor substrate between the first and second doped regions, a magnetic tunnel junction on the gate dielectric layer, word lines on the magnetic tunnel junction extending in a first direction which is the same direction as the second doped region, bit lines connected to the first doped region in a second direction perpendicular to the first direction, and an insulating layer covering the gate dielectric layer, the magnetic tunnel junction, and the word lines. The single transistor type magnetic random access memory device has a simple circuit structure, has a prolonged lifetime and is easy to manufacture.

Abstract: A read block is formed from a plurality of TMR elements stacked in the vertical direction. One terminal of each TMR element in the read block is connected to a source line through a read select switch. The source line extends in the Y-direction and is connected to a ground point through a column select switch. The other terminal of each TMR element is independently connected to a corresponding one of read/write bit lines. Each read/write bit line extends in the Y-direction and is connected to a read circuit through the column select switch.

Abstract: A structure and method for forming a magnetic memory having a number N of levels of magnetic memory cells by forming a plurality of levels of magnetic memory cells, each level including at least one magnetic memory core structure having first and second surfaces, forming a first access conductor connecting to the first surface, forming a second access conductor connecting to the second surface, wherein N+1 access conductors are formed per number N of levels of magnetic memory cells. The structure comprises a plurality of levels of magnetic memory cells, each level including at least one magnetic memory having a number N of levels of magnetic memory cells, including a magnetic memory core structure having first and second surfaces, the first and second surfaces each connecting to an individual access conductor, wherein N+1 access conductors are employed per number N of levels of magnetic memory cells.

Abstract: The present invention generally relates to the field of magnetic devices for memory cells that can serve as non-volatile memory. More specifically, the present invention describes a high speed and low power method by which a spin polarized electrical current can be used to control and switch the magnetization direction of a magnetic region in such a device. The magnetic device comprises a pinned magnetic layer with a fixed magnetization direction, a free magnetic layer with a free magnetization direction, and a read-out magnetic layer with a fixed magnetization direction. The pinned magnetic layer and the free magnetic layer are separated by a non-magnetic layer, and the free magnetic layer and the read-out magnetic layer are separated by another non-magnetic layer. The magnetization directions of the pinned and free layers generally do not point along the same axis. The non-magnetic layers minimize the magnetic interaction between the magnetic layers.

Abstract: This invention provides a probe based magnetic memory storage device. In a particular embodiment, magnetic memory cells are provided in an array. Each cell provides a magnetic data layer and a conductor. At least one movable probe having a tip characterized by a conductor and a soft reference layer is also provided. In addition, an intermediate layer joined to either the movable probe or each memory cell is provided. The movable probe may be placed in contact with a given memory cell, the probe and cell thereby forming a tunnel junction memory cell with the intermediate layer serving as the tunnel junction. The magnetic field provided by the probe conductor may be combined with a field provided by the cell conductor to produce a switching field to alter the orientation of the data layer. The memory cells may include a material wherein the coercivity is decreased upon an increase in temperature. The probe may also include a heat generator.

Abstract: A magnetic random access memory circuit comprises a plurality of magnetic memory cells, each of the memory cells including a magnetic storage element having an easy axis and a hard axis associated therewith, and a plurality of column lines and row lines for selectively accessing one or more of the memory cells, each of the memory cells being proximate to an intersection of one of the column lines and one of the row lines. Each of the magnetic memory cells is arranged such that the easy axis is substantially parallel to a direction of flow of a sense current and the hard axis is substantially parallel to a direction of flow of a write current.

Abstract: Read word lines and write word lines are provided corresponding to the respective MTJ (Magnetic Tunnel Junction) memory cell rows, and bit lines and reference voltage lines are provided corresponding to the respective MTJ memory cell columns. Adjacent MTJ memory cells share at least one of these signal lines. As a result, the pitches of signal lines provided in the entire memory array can be widened. Thus, the MTJ memory cells can be efficiently arranged, achieving improved integration of the memory array.

Abstract: A memory device includes an array of magnetic storage cells. Each magnetic storage cell in the array includes a set of conductors used to write data to a storage cell and a second set of conductors used to heat the magnetic storage cell and read data from the magnetic storage cell. The magnetic storage cells can be used in electronic systems such as a computer system or consumer electronic system.

Abstract: A magnetic storage element and a recording method using the same capable of ensuring correct information recording without causing erroneous writing are proposed. A magnetic storage device having the magnetic storage elements incorporated therein, and being capable of recording information in a stable and correct manner even if the magnetic characteristics vary from the element to element is also proposed. The magnetic storage element comprises a storage layer, magnetic field applying means for applying magnetic field to the storage layer, and a magnetic field shield, disposed between the magnetic field application means and the storage layer, comprising a soft magnetic material, for shielding at least a part of the magnetic field. Recording to the magnetic storage element is made effective by applying a magnetic field to the storage layer while heating the magnetic field shield to thereby allow it to reduce or lose its magnetization.

Abstract: There are provided a first reference layer, in which a direction of magnetization is fixed, and a storage layer including a main body, in which a length in an easy magnetization axis direction is longer than a length in a hard magnetization axis direction, and a projecting portion provided to a central portion of the main body in the hard magnetization axis direction, a direction of magnetization of the storage layer being changeable in accordance with an external magnetic field.

Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.

Abstract: A magnetic tunneling junction (MTJ) memory cell for a magnetic random access memory (MRAM) array is formed as a chain of magnetostatically coupled segments. The segments can be circular, elliptical, lozenge shaped or shaped in other geometrical forms. Unlike the isolated cells of typical MTJ designs which exhibit curling of the magnetization at the cell ends and uncompensated pole structures, the present multi-segmented design, with the segments being magnetostatically coupled, undergoes magnetization switching at controlled nucleation sites by the fanning mode. As a result, the multi-segmented cells of the present invention are not subject to variations in switching fields due to shape irregularities and structural defects.

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract: A magnetic memory includes a magnetic substance composed of a disc-shaped first magnetic layer and a ring-shaped second magnetic layer which is formed on the first magnetic layer.

Abstract: A method and system for providing magnetic memory are disclosed. The method and system include providing a plurality of magnetic memory elements and providing at least one wrapped write line. Each wrapped write line includes a bottom write line and a top write line electrically connected to the bottom write line. The bottom write line resides below a portion of the plurality of magnetic elements, while the top write resides above the portion of the plurality of magnetic elements. The bottom write line carries a first current in a first direction, while the top write line carries a second current in a second direction opposite to the first direction.

Abstract: Each memory cell is constituted by a pair of magnetic memory elements. The magnetic memory elements are connected at one ends to sense bit lines, and at the other ends to a sense word line through a pair of reverse current preventing diodes, respectively. A constant current circuit is disposed on the grounded side of the sense word line. The constant current circuit has a function of fixing a current flowing through the sense word line, and is constituted by a constant voltage generating diode, a transistor and a current limiting resistor.

Abstract: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.

Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.

Abstract: A method and system for providing and using a magnetic memory are disclosed. The method and system include providing a plurality of magnetic memory cells and providing at least one magnetic write line coupled with the plurality of magnetic memory cells. Each of the magnetic memory cells includes a magnetic element having a data storage layer. The data storage layer stores data magnetically. The magnetic write line(s) are magnetostatically coupled with at least the data storage layer of the magnetic element of the corresponding magnetic memory cells. Consequently, flux closure is substantially achieved for the data storage layer of each of the plurality of magnetic memory cells.

Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.

Abstract: The invention includes a stacked magnetic memory structure. The magnetic memory structure includes a stacked magnetic memory structure. The first layer includes a first plurality of magnetic tunnel junctions. A second layer is formed adjacent to the first layer. The second layer includes a second plurality of magnetic tunnel junctions. The stacked magnetic memory structure further includes a common first group conductor connected to each of the first plurality of magnetic tunnel junctions and the second plurality of magnetic tunnel junctions.

Abstract: A magneto-resistive memory comprising magneto-resistive memory cells is disclosed, comprising a pinned magnetic layer and a free magnetic layer. The two magnetic layers are formed having widened regions at the ends of the layers. As such, the shape made out by the magneto-resisitve memory, from a top-view perspective, is wide at the ends and narrower at the mid-, forming an I shape in one preferred embodiment. The end portions of the free magnetic layer are allowed to magnetically couple to the end portions of the pinned magnetic layer such that magnetic coupling is shifted to these widened regions and coupling in the mid-portion between the widened regions is minimized. Thus, the influence of the pinned magnetic layer on the magnetization orientation of the mid-portion of the free magnetic layer is substantially eliminated, allowing for increased predictability in switching behavior and increased write selectivity of memory cells.

Abstract: A closed flux magnetic memory cell has a ferromagnetic pinned structure and a ferromagnetic free structure. Data is stored by controlling the relative magnetization between the pinned and free structures. The free structure is formed as a horizontally extending toroid, or tube, that is insulated from the pinned structure. A first conductive line passes through the center of the free structure while a second conductive line is connected to the pinned structure. A third conductive line can be formed through the free structure. This line is insulated from the toroid and the first conductor. The third conductive line can also be located outside the free structure. In operation of one embodiment, the first and third conductive lines are used to control the magnetized direction of the free structure. A resistance between the first and second conductive lines defines the data stored in the memory cell.