Abstract: The probability of frame destruction is lowered while suppressing the redundancy of the transmission data. On the transmitting side, a predetermined unique word is contained in a frame n for storing the n-th data, and header information n, frame length information and header information n−1 of the frame n−1 one frame before the frame n are subjected to error-correcting coding, contained in the frame n, and transmitted. On the receiving side, the header of the frame n is received. When the frame length information is transmitted with error, the timing is specified by detecting the unique word and header information in the next frame n+1. When the header of the frame n is not successfully decoded, the information data of the frame n is decoded by using the header information n inserted into a predetermined position of the frame n+1.

Abstract: A distributed method and apparatus for assigning a unique identifier number to devices connected in a sequential fashion and determining a total device count is presented. Additionally, a method and apparatus for enabling the support of a variable number and type of time slots within a time division multiplexed serial protocol is presented.

Abstract: It is proposed that currently unused portions of transport overhead in frames sent on a high-speed outgoing channel be used to carry error count information from each of four low-speed input channels. At a 4:1 combiner, error monitoring bytes are extracted from transport overhead of frames received on each of the four input channels. Error counts are determined and accumulated for each input channel before being passed to a transport overhead generator for the outgoing channel, where they are inserted as bit patterns in unused portions of the transport overhead. At a receiving demultiplexer, the error counts are extracted from the transport overhead of incoming frames. The extracted error counts are then used to alter the error monitoring bytes included in the transport overhead of frames sent on each of four outgoing channels such that, at the far end of those outgoing channels, a correct number of errors for the three part path may be determined.

Abstract: A cellular network is controlled such that time slots of transmissions from base stations with the same operating frequency are synchronized. Moreover, adjacent base stations using the same frequency are controlled such that, at any given time, they are transmitting different sync words.

Abstract: A broadband network, such as a cable television system, includes a synchronous code generator that converts an analog signal into a digital signal and inserts a synchronous code in the digital signal. The synchronous code generator is in communication with an optical link, which transmits the digital signal. An optical performance monitor receives the digital signal from the optical link and determines performance of the optical link based on errors in the synchronous code. The optical link performance monitor includes an error detector, which detects errors in the synchronous code, and, in response thereto, signals a counter of the error. The counter accumulates the errors detected by the error detector for a period of time. A processor, which is in communication with the counter, determines the optical performance of the optical link based upon the number of errors accumulated by the counter. A user interface displays the results of the processor.

Abstract: A reception synchronization circuit for receiving a unique word transmitted in a predetermined digital pattern. A detection circuit detects the reception electric field intensity as received power. A UW correlation judgment circuit detects the unique word (hereinafter referred to as “UW”) and takes a correlation between the unique word thus detected and a predetermined digital pattern. A memory stores two or more threshold values for the movement average. After the two or more threshold values and the movement average are compared with each other, the correlation is taken by the UW correlation judgment circuit when the movement average is larger than the minimum values of the two or more threshold values.

Abstract: A base station transmits, in addition to a pilot channel, signals which are multiplexed with pilot symbols inserted in the respective signals in communication channels. As the transmission of the pilot channel as a reference signal for coherent detection is unnecessary with high power so as to attain high reliability, the pilot channel can be transmitted with low power by means of weight in comparison with the communication channel, so that interference with the communication channel of any other station is reduced. Moreover, accurate coherent detection can be made from the pilot symbol inserted in the communication channel on the mobile station side.

Abstract: Link quality control information is generated by receiving a received signal from a front end receiver. Time dispersion information is then estimated during a synchronization of the received signal. Then, link quality control information is generated using the time dispersion information. The link quality control information includes information pertaining to an optimal transmission parameter. The link quality control information can be transmitted back to a unit that transmitted the received signal so that the appropriate transmission parameters may be adjusted.

Abstract: A method and apparatus for an overhead processing system is described. More particularly, frame latency is used to process less time-critical overhead with the overhead processing system. Such a system uses less semiconductor wafer area and consumes less power than processing all overhead in a time-critical manner using flip-flops and the like.

Abstract: A base station transmits, in addition to a pilot channel, signals which are multiplexed with pilot symbols inserted in the respective signals in communication channels. As the transmission of the pilot channel as a reference signal for coherent detection is unnecessary with high power so as to attain high reliability, the pilot channel can be transmitted with low power by means of weight in comparison with the communication channel, so that interference with the communication channel of any other station is reduced. Moreover, accurate coherent detection can be made from the pilot symbol inserted in the communication channel on the mobile station side.

Abstract: A TDMA system in which the mobile receiver performs unique word detection (and hence frame synchronization) by using real correlation coefficients which are not equal to the binary unique word (nor to any shift or scaling of it), but which are dependent on the unique word. In some embodiments, the correlation coefficients are dependent both on the unique word and also on the bit_sync pattern.

Abstract: In coded representation of audio, video and system bitstreams, it is common to insert start codes to facilitate synchronization points. The start codes are usually unique patterns that cannot be duplicated within the bitstream. In the decoding process it is necessary to detect these start codes in order to begin the decoding of the bitstream in a synchronized way. In typical cases, it is normal for the start code to be byte aligned and have the first few bytes comprising of the same pattern. The present invention is a method and apparatus that exploit this feature to reduce the number of comparisons required. A specific order is used in comparing the input bitstream to the start code pattern. Using this order the decoder only need to compare a subset of the bytes during the start code detection process.

Abstract: A data recovery device for precisely recovering a transmission signal even if the signal having phase variations is provided. The device comprises a demodulator for demodulating a transmission signal, a plurality of symbol recovery units, each generating a corresponding synchronous signal and a lock signal, wherein the lock signals are selectively enabled to select one of the synchronous signals, based on pattern variations of the transmission signal detected by the symbol recovery units, and a data decision unit for performing a data recovery operation using the selected synchronous signal to recover original data of the transmission signal.

Abstract: A method for phase encoding DPSK and N-PSK which maintains phase continuity and which does not require any reference symbols when using N-PSK. A sequence of known DPSK phases are encoded with respect to an initial phase. The N-PSK phases are then all offset by this same initial phase. The known DPSK phases can be used at a receiver to determine a sum consisting of the initial phase and any further phase shift introduced by the channel, and this sum is used to decode the unknown N-PSK phases. The method is more generally applicable to any case where a switch between a phase encoding method which requires an absolute phase reference and a phase encoding method which does not have an absolute phase reference is to be implemented on a single carrier or channel.

Abstract: A status phase processor for a data pattern recognizer or correlator provides an optimized synchronization signal. The synchronization signal can be utilized to adjust the data sampling clock. The data pattern correlator utilizes two or more samples per symbol of the signal which is expected to be received. The system provides high accuracy correlation without significant hardware and software overhead. The status phase processor relies on a counter circuit and a logic circuit for generating the synchronization signal.

Abstract: In transmitting ten-bit word string data including synchronous word data converted, at a transmitting side, from eight-bit word string data, representing signal information data synchronization required for reproducing the signal information is reliably established at a receiving side. An additional word data group containing eight-bit synchronous word data is inserted between words of the eight-bit word string data. Then, 8B-10B conversion is performed on the eight-bit word string data, thereby obtaining ten-bit word string data. In this case, the additional word data group is selected so that a running disparity of the ten-bit synchronous word data contained in the additional word data group of the composite ten-bit synchronous word data is consistently positive or negative.

Abstract: A waveform to be transmitted as a burst within a channel that is used for the synchronization of unsynchronized wireless communications terminals in a wireless communications system, and a method of synchronization involving the waveform, that consists of a composite waveform. The composite waveform comprises two or more component waveforms, wherein each of the two or more component waveforms has a known frequency variation throughout the burst. The composite waveform has a composite bandwidth on an order of an available channel bandwidth and each of said two or more component waveforms have a component bandwidth on the order of the available channel bandwidth. Furthermore, a range of values for the differences between the instantaneous frequencies of two of said two or more component waveforms is on an order of twice of said available channel bandwidth.

Abstract: An apparatus, method and system are provided for an intermediate reliability protocol for network message transmission and reception, and are particularly suited for real time applications, such as internet telephony. The preferred system embodiment includes a plurality of servers, connected to each other over a plurality of networks, such as over two ethernets. A first server, when operative, includes program instructions to transmit a message. A second server, which is coupled to the first server over the networks, when operative, includes program instructions to receive the message. Under typical circumstances, the received message will be delivered locally on the second server, to a designated local process. Under other circumstances, the second server will resynchronize to the received message, dropping stored messages and avoiding further delay in message delivery.

Abstract: Methods and systems are provided which utilize pilots in an information sequence to periodically retrain a channel estimator. Thus, a channel tracker may be synchronized using a synchronization sequence and then periodically retrained using known pilot symbols. Furthermore, the utilization of pilots may allow for the detection of errors in previous channel estimates. When errors are detected, a new channel estimate may be used based on the retraining using the pilot symbols and, optionally, previous errors in symbol estimation may be corrected. Thus, by retraining based on pilot symbols, the propagation of errors may be reduced.

Abstract: The present invention provides a synchronizing data protocol comprising one or more serial input-output (SIO) control word(s) and data passed across a high voltage interface, to allow the elimination of a frame synchronization signal (and corresponding AC coupling capacitors). The present invention has particular applicability to, e.g., time division multiplexed (TDM) data, serial data communication devices, or synchronous serial communication interfaces in general, and to the communication between a controller and a codec in an audio codec device in accordance with the AC '97 Specification, i.e., the AC Link. The synchronizing data protocol is implemented over a transmit data signal line to provide occasional synchronization (i.e., not frame-by-frame synchronization) between the two communicating devices. The master device includes a preamble insertion module to insert a predetermined preamble code word into the transmitted data stream.

Abstract: A method is provided for identifying a training baud in a digital audio broadcasting signal. The method includes the steps of receiving a plurality of carrier signals modulated by a plurality of data baud, wherein the data baud include normal baud and training baud. The data baud received on the carriers are compared with predetermined data signals to produce a plurality of difference signals. The difference signals are then used to produce a plurality of distance signals, which are combined to produce group distance signals. One of the group distance signals is selected and used to determine if the data baud corresponding to the selected group distance signal is a training baud or a normal baud. This determination is performed by storing successive selected group distance signals until at least one training baud has been received, and using the stored group distance signals to determine normal/training synchronization.

Abstract: A system includes a unique word correlator module which correlates a unique word field in a burst of a time division multiple access (TDMA) signal against a predefined marker sequence. Automatic timing control circuitry is coupled to the unique word correlator module. The automatic timing control circuitry derives a number of errors that are allowable during correlation of the unique word field.

Abstract: A base station transmits, in addition to a pilot channel, signals which are multiplexed with pilot symbols inserted in the respective signals in communication channels. As the transmission of the pilot channel as a reference signal for coherent detection is unnecessary with high power so as to attain high reliability, the pilot channel can be transmitted with low power by means of weight in comparison with the communication channel, so that interference with the communication channel of any other station is reduced. Moreover, accurate coherent detection can be made from the pilot symbol inserted in the communication channel on the mobile station side.

Abstract: A digital data transmission system for transmitting digital data, a frame pulse signal, and a clock using a required minimum number of signal lines and with a simple circuit structure is provided. A signal separation circuit (46) that receives a multiple clock (CKFP) which is a frame pulse signal (FP) multiplexed with a clock (CK) includes a clock recovery circuit (47) for reproducing a recovered clock (RCK) by synchronization with the multiple clock (CKFP) using a synchronization loop, and a frame pulse signal separation circuit (48) for separating a recovered frame pulse signal (RFP) from the multiple clock (CKFP) on the basis of the recovered clock (RCK).

Abstract: A signal synchronism detecting circuit comprises a receiving circuit receiving a serial data including data bit groups each composed of a predetermined number of continuing bits and delimiter bit groups each composed of a predetermined number of continuing bits for delimiting the data bit groups from one another, a detecting circuit for obtaining an exclusive OR between continuing bits of the received serial data, so as to detect the delimiter bit group, and a serial-to-parallel converting circuit for serial-to-parallel converting the received serial data on the basis of the result of the detection of the delimiter bit group by the detecting circuit.

Abstract: In processing a frame synchronous pattern, a data switch section arranges in such a manner that an object frame synchronous pattern comes as a start of the parallel data, and a provisional-region detection section for samples, among the parallel data, a part in which the object frame synchronous pattern is presumably located, as a provisional region, and converts the parallel data of the provisional region in serial. And a frame synchronous pattern detecting section detects the object frame synchronous pattern from the partial serial data of the sampling and converted and responsive to the frame synchronous pattern detection section and the provisional-region detection section. A data switch control section, controls the data switch section based on the output of the provisional-region detection section and the output of the frame synchronous pattern detection section.

Abstract: An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock.

Abstract: The invention relates to a synchronism judgment apparatus for judging establishment of synchronization with a frame received as a sequence of consecutive slots to which sync patterns are dispersively distributed in a form commensurate with the receiving mode according to a standard suitable for one of a plurality of receiving modes, as well as to a communication system where such a synchronism judgment apparatus is employed. The synchronism judgment apparatus of the invention enables judgement of establishment of synchronization with accuracy compared to a conventional example as long as the above standard is reliably given or identified. Therefore, in a communication system to which the invention is applied, it is possible to maintain the transmission quality and the service quality high and flexibly adapt to a variety of communication services and transmission rates, and the transmission information quantity that may vary to a large extent.

Abstract: Burst transmissions in a burst-type communication system include a preamble synchronization sequence which allows detection and synchronization a burst transmission while at the same time providing information to a receiver, for example, on the subsequent burst payload data. Each burst transmission includes a preamble synchronization sequence which is one of a plurality of predetermined allowed preamble sequences in the system, according to the information desired to be transmitted. The system may also use differential encoding and decoding to eliminate the effects of frequency uncertainty. In that case, the allowed preamble sequences may be such that, after differential decoding, they differ from one another only by a polarity inversion such that a single matched filter may be used to detect two preamble sequences.

Abstract: The present invention concerns a method of transmitting a synchronization signal during a synchronization time slot of a system for telecommunication by mobile stations of the time division duplex (TDD) type where the data are transmitted in frames consisting of time slots, the said synchronization signal including a synchronization sequence.

Abstract: Device for recovering synchronization on a signal transmitted to a mobile-telephone receiver, including phase-estimator means (47, 49) for the absolute value (ABS) and the sign (SIGN) of the transmitted signal, estimation processor (64) for processing the output signals of the estimators (47, 49), a sequencer (67), one input of which is connected to the output of the processor (64) and one output of which applies a mode signal to the processor, another output of the sequencer (67) being connected via a sampling-time generator (68) to the sampling-time control inputs of the estimators (47, 49).

Abstract: A frame synchronous circuit enables a frame synchronization in relation to high speed SDH (Synchronous Digital Hierarchy) signal to be realized with simple constitution. A shift register which performs serial-parallel conversion of an STM-N (Synchronous Transport Module-N (=1, 2, 3, . . . )) signal by 1-byte unit, is in use by way of shift registers 4, and 7 with parallel configuration inputting data alternately in every 1-bit, thus enabling sufficient time for processing operation of the data to be secured. Appearance of A1-byte on two shift registers can be generated by way of two kinds of patterns of output positions which are shifted by one bit with each other caused by input order toward the shift register. Thereby, when the A1-byte detecting circuit 6 detects the A1-byte at an inappropriate output position, slowing the STM-N signal by 1 bit at the 1-bit delay circuit in order to reverse the input order such that the A1-byte is detected at the normal output position.

Abstract: A discrete multitone modulation transmission system is described in which frame synchronization is monitored at the receiver by correlating frequency domain complex amplitudes of a synchronizing frame with a stored synchronizing pattern. If the correlation result falls below threshold, indicating a loss of frame synchronization, a plurality of correlations are performed, in each case using the stored complex amplitudes of the synchronizing frame multiplied by a respective complex value representing a respective complex derotation corresponding to a respective possible time shift of the synchronizing frame. The best correlation result, if it exceeds another threshold, indicates a time shift for restoring frame synchronization, this being possible before the next synchronizing frame is received.

Abstract: The invention pertains to a communication system (300) including one or more communication channels (10), each channel comprising a transmitter unit (20) and a receiver unit (40). Each transmitter unit (20) is connected through an optical fiber link (30) to its associated receiver unit (40). In operation, each receiver unit (20) receives payload data from its associated sending client and adds overhead data to the payload data to generate corresponding aggregate data (600). The aggregate data of each transmitter unit (20) is conveyed through the fiber link (30) to its associated receiver unit (40) which receives the aggregate data, decodes it to separate the payload data from the overhead data and then outputs the payload data to its associated receiving client. The receiver unit (40) interprets the overhead data and uses it for controlling and managing the payload data in the system (300).

Abstract: A method for analyzing the channel using the preceding slot synchronization sequence is provided. The method of the invention is for operating a receiver receiving a signal frame in a dynamic channel wherein the signal frame includes a plurality of slots, each including a plurality of data bits. Each of the slots further includes a synchronization sequence wherein at least a predetermined one of the slots is assigned for the receiver. The preceding slot following the receiver assigned slot includes a varying synchronization sequence which is selected from a group of predetermined synchronization sequences postulates. The method includes the steps of calculating from the preceding slot synchronization sequence an estimated taps value for each of the synchronization sequence postulates, calculating from the preceding step synchronization sequence a log likelihood metric value C(y,h) for each of the synchronization sequence postulates and selecting the synchronization word postulate having the best metric value.

Abstract: A transmitter produces radio signal bursts in periodic time slots allocated to a time-division multiplexed channel. The radio signal of each burst is made up of digital symbols comprising two training sequences enabling the receiver to estimate demodulation parameters and information symbols which the receiver can estimate by a demodulation applied using the estimated parameters. The two training sequences are placed at the start and the end of the burst so that the receiver uses them to demodulate the received signal in the order of the symbols and demodulate the received signal again in the reverse order of the symbols.

Abstract: A data transmission device and a data transmission method are adapted to add an RTP time stamp accurately synchronized with the PCR when sequentially transmitting data stored in a recording medium in advance with the MPEG2-TS format or data sequentially formatted to the MPEG2-TS format by means of hardware according to the RTP.

Abstract: A circuit comprising a first counter, a second counter, a third counter and a decoder, where the decoder may be configured to present a locked output signal. The first counter may present a first output signal in response to a start of frame signal and one or more control signals. The second counter may be configured to present a second output signal in response to the start of frame signal and the first output signal. The third counter may present a tracking control signal to the first counter in response to one or more of the control signals.

Abstract: The invention relates to a method for synchronizing a radio terminal in a radio-communication network with a received signal flow comprising a predefined synchronization sequence repeated at predefined time intervals. According to the invention, the method consists in generating correlation profiles at the radio terminal by correlating a part of said signal flow with the synchronization sequence to reveal correlation peaks and accumulating as many correlation profiles as necessary, until a threshold level is reached by at least the largest correlation peak. The threshold level is updated, during the accumulation, depending on a background noise level estimated in the signal flow to dynamically determine if the synchronization sequence has been detected at the radio terminal.

Abstract: A slot receiving synchronous circuit includes a temporary storage register for temporarily storing receiving slot data having an m-bit fixed length, where m is an integer, a detector for detecting whether the m-bit receiving slot data stored in the temporary storage register has a predetermined pattern, a slot counter circuit, initialized by the detection signal outputted by the detector, for synchronizing the receiving slot data, and a bit counter circuit for counting bit clocks inputted thereto in synchronization with each bit input of the receiving slot data, to provide a count value, and for supplying signals, when the count value reaches a predetermined value, to the slot counter circuit such that the slot counter circuit counts the signals. The slot counter circuit and the bit counter circuit are set to their initial values, respectively, by the detection signal.

Abstract: A router interface that increases the data transmission rate between optical data routers is provided. In particular, a parallel router interface according to this invention includes: (1) a plurality of parallel channels, (2) a parallel-to-serial converter, and (3) a plurality of framers. Each of the channels can transmit a block of bits at a time, and each block forms at least a portion of a packet. The parallel-to-serial converter converts each of the blocks to a serial stream of data and provides the stream to a serial interface. The plurality of framers are coupled to the serial interface and are each associated with one of the parallel channels.

Abstract: In a PN code generating apparatus, a code of the predetermined number of stages is generated using primitive polynomial G(x), then the code content of each stage is shifted to the next stage. And a state setting section obtains a code state of the PN code generating section after shifted the specific times from a code state of the PN code generating apparatus at a certain time, based on ximodG(x) as the number of shift times is i.

Abstract: A synchronization equipment performs correlation processing between a first known pattern included in a received signal and a second known pattern, and detects reception timing of the received signal. A correlation value computing portion computes a correlation value between the first known pattern and the second known pattern at every reception time. A reception timing detection portion compares the computed related value with a predetermined threshold value, determines the reception time when the correlation value becomes larger than the threshold value to be the reception timing of a received signal, and, after this determination, suspends the comparison between the correlation value and the threshold value, and holds the reception time determined to be the reception timing.

Abstract: When a sync pattern in a frame of a bit stream is detected to synchronize a data processing apparatus with the bit stream, data patterns containing a pattern identical to the sync pattern are often erroneously detected as the sync pattern. In order to overcome such problem, an apparatus for detecting data in a bit stream is provided. The bit stream contains a sequence of frames, and each frame has a predetermined number of bits and comprises a sync pattern and a data portion. The apparatus contains a detecting circuit, a counting circuit, and a synchronization signal generating circuit. The detecting circuit detects a first data pattern in the bit stream that equals the sync pattern and detects a second data pattern in the bit stream that equals the sync pattern. The counting circuit begins counting bits in the bit stream to generate a count value when the first data pattern is detected by the detection circuit.

Abstract: A frame synchronization detecting circuit is provided which is capable of efficiently reducing power consumption in a hunting state.

Abstract: Transmission timing of the control signal is controlled such that each transmission timing differs between at least adjacent base stations. Thus, the mobile station can reproduce the control signal using only a predetermined spreading signal for the base station which transmits the control single. Therefore the time for reproducing process of the control signal can be reduced.

Abstract: In a terminal apparatus to which an SDH transmission mode is applied, there is a method including a pseudo-synchronization detecting step of detecting, by one transmitter-receiver, that a pseudo-synchronization state is established by finding in data the same pattern as a synchronization pattern in byte information, a pseudo-synchronization posting step of inserting, by the one transmitter-receiver, information to the effect that the pseudo-synchronization state is established in an overhead of an STM frame, and posting the information to the other transmitter-receiver, and a changed synchronization pattern transmitting step of changing a synchronization pattern into an additional synchronization pattern different from the synchronization pattern in the byte information, and transmitting the synchronization pattern obtained by the change from the other transmitter-receiver to the one transmitter-receiver.

Abstract: A data transmission apparatus using a digital modulation system wherein a transmitting side inserts a group of predetermined synchronization symbols into a transmission signal at predetermined intervals to be transmitted. A receiving side calculates an electric power value of a received transmission signal. When a no-signal period (null section) in the synchronization symbol group is to be detected and decided from a magnitude of the received signal electric power value, a threshold for reference of decision for detecting the null section is calculated on the basis of an average electric power value for a predetermined period in the received signal electric power value and the threshold calculated in accordance with the received signal level of the transmission signal is used to detect synchronization stably.

Abstract: A method and apparatus for detecting framing alignment sequence within a received bit stream. A stream state memory is assigned for each possible location of the framing alignment sequence. Bits of a particular stream are loaded into the respective stream state memory. If the bits do not match an acceptable subsequence of the framing alignment sequence then the stream is eliminated from consideration by writing an exile state to the respective stream state memory. Then subsequently received bits are used to transition either to the next state if the next bit is a correct bit in the framing alignment sequence, or to the exile state if the bit is not the correct bit. After all of the streams have been exiled but one, the remaining stream may contain the framing alignment sequence. However, it may be that a certain number of correctly received bits are required to declare in-frame with sufficient certainty in which case incoming bits will continue to be processed until this is satisfied.

Abstract: For a method for searching synchronization patterns in serial, packet-oriented and multiplexed data streams, the m bits of a synchronization pattern are continuously inserted into each nth packet of a data stream. One bit of bits of the serial data stream that is acquired and comprises n packets is respectively stored in a memory cell of allocated memories that are m memory cells wide, said memory cell representing a bit position within n packets. The number of memories is determined by n×number of bits per packet. Upon recognition of a bit pattern in one of the memories, the bit position of the bit pattern in the serial data stream is defined.