Abstract: A wireless transmit receive unit (WTRU) and methods are used in a wireless communication system to process sampled received signals to establish and/or maintain wireless communications. A selectively controllable coherent accumulation unit produces power delay profiles (PDPs). A selectively controllable post processing unit passes threshold qualified magnitude approximation values and PDP positions to a device such as a rake receiver to determine receive signal paths.

Abstract: A received synchronization pattern (300″) is compared against first and second known synchronization patterns. If the received pattern is substantially similar to the first known pattern, the payload is processed as voice; and if the received pattern is substantially similar to the second known pattern, the payload is processed as non-voice. Alternatively, a target synchronization pattern dependent on an operating mode is selected. The received pattern is compared against the target pattern. If the received pattern is substantially similar to the target pattern, the payload is processed; otherwise, the burst is discarded. In yet another alternative, the received pattern is compared against first and second known synchronization patterns having a common length. If the received pattern is substantially similar to the first known pattern, a first operating mode is selected, and if the received pattern is substantially similar to the second known pattern, a second operating mode is selected.

Abstract: A data sync signal detecting device for detecting a sync signal having sync signal detection errors. The detecting device applies the output data of a most-likelihood decoder to shift register bit cells. The data is sequentially shifted and held in the bit cells of the shift register. The bit cell outputs are separated into odd-numbered and even-numbered bit string and applied to first and second pattern matching circuits. The odd-numbered bit string is matched with “01001” by a first pattern matching circuit. The even-numbered bit string is matched with “01011” by a second pattern matching circuit. First and second matching results are applied to a coincidence number adder/majority decision circuit. When coincidence occurs, the matching result is “1”, and when non-coincidence occurs, the matching result is “0”.

Abstract: A method and system for synchronizing clocks in a packet network that includes a master node and at least one slave node that communicate with one another is disclosed. A timer value from a master clock is retrieved upon transmission of a first packet to the slave node. The timer value and an associated code are subsequently sent to the slave node in a subsequent packet. After receiving the first packet, the slave node, retrieves a timer value from a slave clock and associates it with an identifying code of the first packet. After receiving the subsequent packet, the slave node relates the timer values and adjusts a clock value of the slave clock accordingly. An interrupt scheme may be used to implement the retrieval of the timer values.

Abstract: An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock.

Abstract: On the transmitting side a spread modulated signal that has undergone spread spectrum processing and an information modulated signal that has not undergone spread spectrum processing are multiplexed in a same frequency band. On the receiving side the specific modulated signal is first demodulated by a spread spectrum demodulation section 1803, then a replica signal of the specific modulated signal is generated by a spread spectrum modulated signal regeneration section 1805, and the information signal that has not undergone spread spectrum processing is extracted by eliminating the replica signal from the multiplex signal. By this means, even when a large number of information signals are transmitted in a same frequency band, these signals can be separated and demodulated satisfactorily on the receiving side.

Abstract: A method, apparatus and software program is provided for scheduling and admission controlling of real-time data packet traffic. Data packets are admitted or rejected for real-time processing according to throughput capabilities of a packet scheduler. A delivery deadline is determined for each payload data packet at the packet scheduler and packets are sorted into a time-stamp-based queue. Deadline violations are monitored and an adaptation of payload data packets can be triggered on demand in order to enter a stable state.

Abstract: A system and method are provided for encoding and decoding a bitstream according to the High level Data Link Control protocol (HDLC) without having to analyze the bitstream bit by bit. An optimized encoder and an optimized decoder are provided. Both encoder and decoder analyze their respective input streams by using a number of bits in parallel as an index into a table, the contents of which control an action by the encoder or decoder that emits in parallel a number of output bits.

Abstract: A method for detecting synchronization loss of the trellis minimum path metric in V.34 modem communications. The invention detects synchronization loss due to bit inversions in trellis decoding in transmitted digital frames due to a periodic inversion pattern that is used for superframe synchronization. The method provides synchronization loss detection by finding the ratio of moving averages for a series of data blocks to the average of a series of inverted 4D symbols located periodically in the beginning and center of received data frames.

Abstract: Transmission timing of the control signal is controlled such that each transmission timing differs between at least adjacent base stations. Thus, the mobile station can reproduce the control signal using only a predetermined spreading signal for the base station which transmits the control single. Therefore the time for reproducing process of the control signal can be reduced.

Abstract: A method and apparatus for generating a code in an asynchronous code division multiple access mobile communication system is provided. Specifically, the method and apparatus are for use in a transmitter in a mobile communication system which has multiple code groups having inherent code indices in response to each of slots, which selects one code group from among the multiple code groups, and which generates a second synchronization code corresponding to any one slot from among multiple slots, which are included in the selected code group.

Abstract: Method and system for recognizing the presence of a reference signal having M components. A signal s(t) is received that may contain a reference signal s(t;ref). An M×M covariance matrix of the M components of the received signal is formed, and M eigenvector solutions V=Vj and associated eigenvalue solutions &lgr;=&lgr;j (j=1, 2, . . . , M) of the matrix relation R·V=&lgr; V are determined. A subspace S′ of the space spanned, spanned by a selected subset of the vectors Vj′ (j′=1, . . . , N(s)) is formed, with N(s) a selected number that is ≦M. Product signals s(t)·Vj′(t) are formed and integrated over a selected time interval, t0≦t′≦t, to form estimation signals xj′(t) (j′=1, . . . , N(s)). The estimation signal xj′(t) and the reference signal s(t;ref) are used to determine a weighting coefficient wj′(t) (j′=1, . . .

Abstract: A frame synchronizing apparatus using a memory in which a frame synchronizing algorithm is embodied in an ASIC(application specific integrated circuit) so as to be used in a circuit for synchronizing a frame in framing/deframing method for improving a performance of ATM(asynchronous transfer mode) cell extraction in high-error wireless environment of WATM(wireless asynchronous transfer mode), and such an algorithm can be employed in a circuit for synchronizing the frame in a received data stream.

Abstract: A system for data communication receives more than one input data streams that have independent clocks and an input order. The system synchronizes the input data streams to a common clock, and multiplexes the synchronized data streams onto an input of a data communication link. The system demultiplexes one or more output data streams from an output of the data communication link. The system identifies each of the output data streams and reorders the output data streams into the same order as the input data streams.

Abstract: When signals for two mobile stations PS-A and PS-B are multiplexed using path division, a clock generating unit 52 generates a clock signal so as to delay the timing for transmitting symbols to the mobile station PS-B by 0.5 symbol periods relative to the transmission of symbols to the mobile station PS-A. If the transmission timing is adjusted in this way, a mobile station that picks up symbols which are spatially multiplexed with the signal for the present mobile station but are intended for another mobile station will not be synchronized with the symbols for the other mobile station.

Abstract: The present invention relates to a CDMA wireless base station apparatus. An object of the present invention is to provide a CDMA wireless base station apparatus which is able to shorten the period from a fault to recovery. Each of a 0-system spread processing section 3a and a 1-system spread processing section 3b which constitute a duplex configuration generates a perch channel signal, an active synthesized spread signal and a standby synthesized spread signal. In normal operation, the perch channel signal and the active synthesized spread signal from the 0-system spread processing section 3a and the standby spread signal from the 1-system spread processing section 3b are synthesized in a radio transmission processing circuit 4 and radiated from an antenna 5.

Abstract: A serial data signal having a predetermined sequence to indicate a start of a frame of data is received. The serial data signal is compared to a plurality of values. The plurality of values include the predetermined sequence and one or more values representing logical rotations of the predetermined sequence. A match signal is generated in response to the serial data signal matching one of the plurality of values.

Abstract: This proposal describes an optimized synchronization (SYNCH) symbol sequence to be used in transmission systems, which are currently under standardization. The synchronization symbol is constructed using specially designed OFDM (orthogonal frequency division multiplexing) symbols with an optimized sequence, which is mapped onto the modulated subcarriers. The resulting synchronization symbol consists of several repetitions in the time domain. Using the proposed sequence the resulting synchronization symbol achieves a high timing detection and frequency offset estimation accuracy. Furthermore the burst is optimized to achieve a very low envelope fluctuation (low Peak-to-Average Power Ratio) and a very low dynamic range to reduce complexity on the receiver and to save time and frequency acquisition time in the receiver. The proposed sequence is furthermore optimized with respect to all other synchronization symbols that are used to construct the synchronization and training preambles for the BCCH-DLCHs.

Abstract: In a method for the unidirectional and interference-safe transmission of digital data via radio waves, wherein the data which are composed of data packets each comprising a defined number of bytes and of at least one synchronization packet are transmitted from a transmitter to a receiver, it is proceeded such that each byte is transmitted in a manner comprised of flag bits as start bits, information-representing information bits and identification bits encoding the number of the respective byte and carrying the parity information and that the flag bits and the information bits are inverted in every second byte.

Abstract: A method for high-speed signal framing of an incoming bit stream includes receiving the incoming bit stream in a datapath and locating a predetermined framing pattern in the datapath by finding a predetermined number of repetitions of a first portion of the framing pattern, bit aligning the bits in the datapath based on the predetermined number of repetitions of the first portion, priority encoding bits in a next cycle of the datapath, identifying a location of a second portion of the framing pattern, word aligning the priority encoded bits. The method includes declaring the bit stream as in frame. The incoming bit stream is over a datapath of at least 64 bits and the predetermined number of repetitions is at least three repetitions. Further, the incoming bitstream is a parallelized bitstream, the parallelization being performed in a shift register.

Abstract: A method, apparatus and software program is provided for scheduling and admission controlling of real-time data packet traffic. Data packets are admitted or rejected for real-time processing according to throughput capabilities of a packet scheduler. A delivery deadline is determined for each payload data packet at the packet scheduler and packets are sorted into a time-stamp-based queue. Deadline violations are monitored and an adaptation of payload data packets can be triggered on demand in order to enter a stable state.

Abstract: A method and apparatus reduces the complexity of initial synchronization in mobile terminals operating in TDMA communications systems. A TDMA transmission comprises multiple repeating time slots marked by synchronization words. Initial synchronization requires locating at least one time slot in the received signal. Information in a slot is received as a sequence of symbols at a defined symbol rate. The mobile terminal receives the TDMA transmission for a period longer than one time slot and samples a baseband version of the received signal at M times the symbol rate. This oversampling produces M symbol-rate sample sets, with each sample set corresponding to one of M sampling phases. The mobile terminal performs a FFT on each one of the plurality of the M sample sets after raising it to the nth power, where n is based on the number of modulation phases used to transmit the symbols.

Abstract: The present invention will allow the use of the asynchronous Ethernet MAN as if it was a regular fiber optic line, while eliminating the uncertainties of it's cloud environment. The invention provides a new method for synchronizing transmissions of real time synchronous data packets over an asynchronous network between two terminal nodes. The synchronization procedure is implemented within intermediating communication devices, which connect between the terminal nodes TDM equipment and the asynchronous network. Each communication device comprises local clocks, which are activated by a Stratum 2/3/3e/4/4e pulse generator. The local clocks synchronization is based on the transmission of a reference timestamp packet through an asynchronous network. Based on this timestamp references, an internal digital PLL is used for attenuating the jitter/wander in data transmission signal in accordance to Stratum 2/3/3e/4/4e accuracy standards.

Abstract: A method for digital audio broadcasting comprising the steps of receiving a plurality of data bits to be transmitted, formatting the plurality of data bits into a plurality of protocol data units, inserting header bits at spaced locations within the protocol data units, and using the protocol data units to modulate a plurality of carriers to produce an output signal. The individual header bits can be positioned at evenly spaced locations in the protocol data units. A first one of the header bits can be offset from an end of the protocol data unit. A method of receiving the digital audio broadcasting signal the transmitters and receivers that operate in accordance with the methods are also provided.

Abstract: A method and apparatus having a modified Reed-Solomon decoder is used for finding a specific code group used by a base station and the frame timing synchronization with the base station. The modified Reed-Solomon decoder uses a standard Reed-Solomon decoder and some reliability measurements computed from the received code word symbols. If the reliability of a received symbol is too low, this symbol is considered as erasure. By selecting code word symbols with higher reliabilities and erasing code word symbols with lower reliabilities, the symbol error probability is reduced and the performance is improved. Several modified Reed-Solomon decoders and a few decoding strategies are introduced in order to decode the received code word sequences with a power- and memory-effective method.

Abstract: A method and apparatus for data retrieval from a storage media, such as magnetic disk drive. A synchronization detector decodes the synchronization information from either the first or second synchronization mark. A later stage detector then carries out several decoding iterations using the synchronization information from the synchronization detector and data stored in the first and second memories. Loss of the data between the first synchronization mark and the second synchronization mark, if there is a problem with the first synchronization mark, is avoided because the bit stream is stored in the first memory.

Abstract: An apparatus is provided that calculates a state at a time of starting an operation of a shift register that generates a PN code. The apparatus includes a system that obtains a parameter “i” that pertains to the state at the time of starting an operation, a system that obtains coefficients of a generator polynomial corresponding to the PN code, and a system that calculates the state at the time of starting an operation, based on the parameter “i” and the coefficients of the generator polynomial.

Abstract: A bit stream demultiplexer that couples a high-speed bit stream media to a communication Application Specific Integrated Circuit (ASIC). The bit stream multiplexer performs its demultiplexing function staged within at least two integrated circuits. The first Integrated Circuit (IC) receives a first bit stream and performs a first demultiplexing function. A second IC performs a second demultiplexing function. The second IC acts as either a slave or a master to the first IC. In a slave mode, the second IC depends upon a transmit data clock from the first IC for latching bit stream data received from the first IC. When the second IC operates in the master mode, the second IC uses the transmit data clock from first IC as a reference input for a PLL to generate a Receive Data Clock. If an LOL or LOS occurs within the first IC, a signal to the second IC indicates these conditions causing the second IC to switch to a local oscillator reference clock to generate the Receive Data Clock.

Abstract: Method and apparatus for synchronizing communication between a battery and an electronic device are disclosed. Bytes consisting of a number of bits are transmitted between the electronic device and the battery. A predetermined bit sequence is appended to at least some of the bytes prior to transmission. The time interval between given shifts in the predetermined bit sequence is used to synchronize the communication.

Abstract: A digital system (100) has two or more nodes (120, 130) and a communication channel (110, 111) for transferring a single stream of ordered data from one node to another. The communication channel (110) has a number of data links (110a-110g) for transferring a plurality of sub-streams of data in a parallel fashion in order to transfer more data than a single data link is capable of transferring. Receivers (132a-132g) each have synchronizing circuitry (200, 202) for synchronizing a byte clock and a frame pulse of each received data sub-stream to the byte clock and frame pulse of a preselected master one of the receivers such that inherent data skew is eliminated.

Abstract: A method and apparatus to improve fax quality when transmitting fax over packet based network with significant delay and packet jitter. The method is based on adjustment to the protocol timing between a “receiving Gateway” and the receiving Group 3 Facsimile Equipment (G3FE). The protocol adjustment is applied when operating facsimile transmission over Internet to increase the success rate for transmission of facsimile via T.38 or similar facsimile relay protocols. The method ensures that network delay and packet jitter do no result in certain violation of timing constraints defined by the T.30 protocol between a “receiving Gateway” and receiving G3 Fax Terminals.

Abstract: The present invention relates to a method in connection with serial data, to recognize a frame synchronization pattern, and for the sake of providing a fast and reliable search algorithm especially for V.110 synchronization pattern, the present invention suggests a method characterized by examining two successive bytes by performing a binary AND operation between the first byte and a check byte made up from the value of the second byte, examining if the AND operation is zero for thereby establishing whether said first byte and second byte qualify as candidates for the synchronization pattern, and further verifying said candidates by checking further criteria given by the frame in question.

Abstract: A method and apparatus for frame-level, sub-second error reporting is disclosed. Trouble profiles are compiled using synchronous constant-frame error detection and, during a transmission hiatus, pseudo-synchronous constant-frame error detection so as to describe transmission integrity down to the millisecond. This provides profiles that can be used to trace the cause(s) of outages to complex networks including outages from network activity. The outage profiles obtained from the described device can be used to determine and confirm the source of sub-second, or more, transmission outages.

Abstract: A system and method for transferring data from a source to a destination are described. Data packets are split into multiple data packet portions and are transferred in parallel over parallel data streams or pipes to grouping circuitry where they are recombined into full data packets. Each packet portion is assigned a synchronization code and a pipe state machine state. The grouping circuitry reads individual packet portions from the parallel streams and analyzes the synchronization codes and the state machine states to determine if the individual packet portions were generated from the same packet. If so, they are recombined into a full packet and are forwarded to the destination. If not, an error is detected. The grouping circuitry automatically realigns the data streams to recover synchronization without the need for any feedback to the individual streams to correct the error.

Abstract: In the present invention, UW gate signal generator generates a UW gate signal for detecting a unique word. Gate circuit masks received signal using UW gate signal. PN detector compares a preset unique word signal set value and the signal output from inverting circuit during the active-high interval of UW gate signal, detects whether or not they are matching, and outputs the result. UW detector compares a preset unique word signal set value and the signal output from gate circuit during the active-high interval of UW gate signal, and outputs UW detection signal. Error detector outputs a detection stop signal for stopping unique word detection based on the signals output from PN detector and UW detector.

Abstract: A method for use in a receiver in an orthogonal frequency division multiplexing-based data transmission system of detecting frame synchronization with respect to a signal received from a transmitter in the system comprises the following steps. First, the received signal is searched at a first predetermined sub-carrier frequency and at least a second predetermined sub-carrier frequency for a previously inserted data pattern. Then a frame boundary in the received signal is identified as a position where the data pattern is detected at both the first predetermined sub-carrier frequency and the second predetermined sub-carrier frequency.

Abstract: A chirp waveform is employed in establishing timing synchronization between nodes of a data communication network. In one embodiment, the chirp waveform is combined with a waveform modulated with data to form a synchronization waveform. The receiver of the synchronization waveform determines an alignment of the chirp waveform to a template chirp waveform to synchronize timing between nodes.

Abstract: A continuously adjusted bandwidth phase-locked loop is used by a B-CDMA™ receiver to correct for any deviation, or offset, that may exist between the received radio frequency (RF) carrier signal and the frequency of the first stage LO that converts the received RF carrier signal to an intermediate frequency (IF). The PLL in the receiver includes a filter with an adjustable bandwidth. A wider bandwidth is used during initial acquisition of the received signal. After the PLL has acquired the received carrier signal using the wider bandwidth, the bandwidth of the filter is gradually narrowed to provide a low steady-state error.

Abstract: A synchronizing arrangement for a closed-loop data transmission system includes a central data switch and a plurality of transceivers which may be interconnected by way of the switch for the transmission of data between them. The central data switch includes a clock generator, and a plurality of ports, each of which includes a transmitter, a receiver, a phase detector and a phase encoder. Each transceiver includes a data transmitter, a data receiver and a synchronizing means operable to maintain synchronism between the transceiver and the data port. A common reference oscillator provides frequency reference signals to the central data switch, each data port and each transceiver.

Abstract: The present invention provides a frame synchronous circuit wherein the number of devices handling a high-speed digital signal is limited to the minimum without deteriorating frame pull-in time and an erroneous synchronization rate. For the sake of it, synchronous word decision devices decide frame synchronization from four lines of low-speed digital signals into which the high-speed digital signal is converted by a serial-parallel converter. An OR circuit synthesizes respective outputs of the synchronous word decision devices, and an aperture circuit applies an aperture to the output synthesized. A selection circuit fetches only one output corresponding to the change of the apparent synchronous word after establishment of synchronization. A frame counter circuit estimates a predetermined position of the next frame at the time of applying a narrow aperture. A leading-edge positioning/column change circuit performs leading-edge positioning and column change of data to the output of the selection circuit.

Abstract: In all wireless systems, the first operation that must take place at the receiver is the acquisition of the carrier and timing. OFDM systems are particularly sensitive to carrier offsets since these can introduce inter-carrier interference and loss of signal power. An algorithm, termed modulo-sub-carrier (ModSC), which can estimate the local oscillator offset in a fast and efficient manner has been devised. The carrier offset can be brought to within one half the carrier spacing within 1 to 10 OFDM symbols. By inserting a null in the center carrier, carrier acquisition can be easily accomplished by locating this null in the FFT bins at the receiver. The offset of this null from the designed position indicates the local oscillator offset in units of number of sub-carriers. An additional carrier tracking algorithm is used to estimate the offset within one half the inter-carrier spacing. Together, the ModSC and carrier tracking algorithms completely estimate the local oscillator offset.

Abstract: A TDMA/CDMA radio communications system provides frequency channels which are formed both by time slots and by broadband frequency ranges, and in which information from a plurality of connections can be simultaneously transmitted between mobile stations and a base station wherein it is possible to distinguish the information from different connections in accordance with a connection-specific fine structure. Frequency channels are repeatedly provided for frequency synchronization of the mobile stations in the downward direction in which a symbol sequence is transmitted. From received signals, the mobile station to be synchronized determines estimated values for the symbol sequence and compares these estimated values with a reference sequence. It is thereby possible to calculate a phase drift in the estimated values with reference to the reference sequence wherein a frequency offset, which is used for frequency synchronization, is determined from the phase drift.

Abstract: In this demodulation method, a receive signal is demodulated estimating the fading distortion of data by detecting the fading distortion of unique word as pilot signal inserted into multiple sections of the receive signal. The method has the steps of: comparing a unique word in the multiple sections of receive signal and a known unique word and thereby detecting the fading distortion of unique word in the multiple sections; calculating a spline interpolation curve based on the fading distortion of unique word in the multiple sections; estimating the fading distortion of data in the receive signal from the spline interpolation curve; and demodulating the data in the receive signal based on the fading distortion of the data.

Abstract: The present invention provides a method to achieve frame synchronization from a received data sequence before the carrier phase and frequency offset recovery for any MPSK modulated signals on the basis of maximum likelihood theory. Two overhead configurations are considered in developing the frame synchronization algorithms. One overhead configuration consists of a unique word followed by a preamble, and the other consists of unique word only. For the first overhead, the frame synchronization can be decoupled from carrier recovery because the preamble following the unique word is a known sequence pattern. In this case, the maximum-likelihood frame synchronization rule is simply a complex correlation. In second overhead, the unique word is immediately followed by random traffic data and thus the coupling effects are generated between frame synchronization and carrier recovery. These coupling effects are not dominant, however, and may be neglected in actual practice.

Abstract: A method for transmission of data in a digital audio broadcasting system includes the steps of providing a plurality of orthogonal frequency division multiplexed sub-carriers, with the sub-carriers including data sub-carriers and reference sub-carriers, and modulating the data sub-carriers with a digital signal representative of information to be transmitted. The reference sub-carriers are modulated with a sequence of timing bits, wherein the sequence of timing bits includes an unambiguous block synchronization word, and the number of bits comprising the block synchronization word is less than one half of the number of bits in said timing sequence. Then the orthogonal frequency division multiplexed sub-carriers are transmitted. Receivers that differentially detect the block synchronization word and use the block synchronization word to coherently detect the digital signal representative of information to be transmitted are also included.

Abstract: A computer implemented method and apparatus utilizing a multi-diversity synchronization technique for improving time synchronization in wireless applications, such as TDMA applications is disclosed. The multi-diversity synchronization technique utilizes cross-correlations between multiple diverse received signals to determine relative offsets between the signals. The signals are then time aligned. An absolute synchronization word location is determined using the time aligned signals and is used along with the relative offsets to determine respective synchronization word locations for each received signal in an accurate, efficient and improved manner.

Abstract: In order to obtain a digital radio communication receiver having a preferable frame-structure decision probability, a frame synchronization state is decided in accordance with separately detected frame-synchronization synchronous words and a frame-structure is decided in accordance with a frame-structure synchronous word and to output the frame synchronization state and the frame structure.

Abstract: A satellite payload processing system for processing an uplink signal consisting of a plurality of single-channel-per-carrier, frequency division multiple access carriers comprises a polyphase demultiplexer processor for separating the uplink signal into a time division multiplexed data stream of symbols. The polyphase demultiplexer processor presents the symbols corresponding to each of a plurality of carriers at respective ones of the frequencies in the uplink signal sequentially to an output of the polyphase demultiplexer processor. A phase shift keying demodulator and differential decoder demodulates the stream of symbols into corresponding time division multiplexed stream of digital baseband bits, which are then rate-aligned with respect to an on-board clock.

Abstract: A method of estimating SNR for a plurality of carriers modulated with digital information, wherein the digital information includes data baud and training baud, comprising the steps of: receiving the plurality of carriers; determining a first SNR for the data baud; determining a second SNR for the training baud; comparing at least one of the first and second SNRs to predetermined selection criteria; and selecting one of the first and said second SNRs based on the comparison step. In the preferred embodiment, the carriers are processed to produce an equalizer output for each of the carriers, and the equalizer output is processed to produce a symbol decision for each of the carriers. The equalizer output is subtracted from the symbol decision when a data baud is received to produce a first difference value, and the first difference value is squared to produce a first signal to noise estimate.

Abstract: According to one embodiment of the present invention a method of operating a data network loop having at least two nodes includes monitoring deletions in an adaptive elasticity first-in, first-out (FIFO) buffer in each node, identifying each adaptive elasticity FIFO buffer that is a deleter, the deleter being an adaptive elasticity FIFO buffer for which information is deleted more often than information is inserted, and reducing a deletion threshold for each adaptive elasticity FIFO buffer that is a deleter. According to another embodiment of the present invention a buffer includes an adaptive elasticity FIFO buffer and a control circuit operatively configured to monitor deletions in the adaptive elasticity FIFO buffer, determine if the adaptive elasticity FIFO buffer is a deleter, and reduce a deletion threshold for the adaptive elasticity FIFO buffer if the adaptive elasticity FIFO buffer is a deleter.