Abstract: A frequency acquisition and compensation device and method for direct sequence spread spectrum communications systems has an identification (ID) sequence in an acquisition frame which is received by a receiving station and an ID sequence stored in an ID register. A received acquisition frame is demodulated using dot product and cross product demodulation. An ID detector detects the ID sequence in the demodulated dot product, cross product, or inverse cross product acquisition frame. When the ID is detected by the dot product demodulator, the receive frame timing is adjusted to coincide with a time interval when the ID was detected. Also, when the ID sequence stored in the ID register matches either the dot product, cross product or inverted cross product of the received ID sequence, the system microcontroller updates the automatic frequency control value.

Abstract: A bus system for the transmission of messages between a device and at least one peripheral unit is proposed, the messages being in each case transmitted via a sequence of high or low bit states. The control device can send high-priority messages and low-priority messages to the peripheral unit. The high-priority messages have a greater amplitude between the high and low bit states than the low-priority messages.

Abstract: An air frame synchronisation signal is transmitted as a data signal over a PCM link from a central unit to a plurality of remote radio transceivers, allowing the remote radio transceivers to recreate the AFS signal with the desired accuracy, compensating for transmission delays.

Abstract: A method, apparatus and article of manufacture are described. In particular two network interface devices that are connected over a path that includes a digital trunk using robbed-bit signaling use a technique to identify the presence of robbed-bit signaling. The network interface devices synchronize to bytes that are subject to robbed-bit signaling. The network interface devices must synchronize to the robbed-bit signaling to avoid transmitting information or receiving information in these signaling positions. The network interface devices then take advantage of the least significant bit positions of frames that are not used for robbed-bit signaling. This results in an increase in data carrying capacity from 56 kps to 62.7 kps.

Abstract: A technique has been devised which may be used to synchronize a receiver clock to a transmitter clock at either end of a transmission network having jitter intrinsic therein. The technique is characterized by a modified least squares linear regressive approach which takes advantage of assumptions particular to such transmission networks. The technique finds advantages in comparison to commonly used phase-locked loop techniques which have long startup phase delays where clocks are not in sync. The modified least squares linear regressive technique of the invention provides excellent isolation of jitter and other timing variations while simultaneously providing for quick startup.

Abstract: An ATM cell synchronization circuit can be realized by a circuit construction operable at low speed. Cell strings developed into eight parallel strings by a serial to parallel development circuit are further developed into 8n parallel strings. A frequency of a clock signal synchronous with bytes of the input cell string is divided into n by a frequency divider circuit for lowering speed to be 1/n. The parallel developed signals are rearranged by a shifted register into a signal string for detection by HEC (Header Error Control) detecting circuit. Then, an HEC byte is detected by the HEC detecting circuit. In order to detect the HEC bytes located at n positions, n in number of HEC detecting circuits are provided, At this time, the HEC byte after n cells becomes the same position. The interval of n cell is fifty-three. Therefore, a counter counting fifty-three is provided. Respectively predetermined values are detected by the decoders to generate detection signals.

Abstract: A device and method for synchronizing a series of data packets in a bitstream using a histogram which accumulates a count of occurrences of a particular synchronization pattern at a given location in each packet and identifies the start of a data packet based on the count of such occurrences stored in the histogram.

Abstract: In a CDMA/TDD cellular system, time necessary for a mobile station to carry out initial synchronization, judgment of the most preferable base station, and acquisition of synchronization of a long code is shortened. A reception base band processing portion 27 reproduces perch channel data from received signals using symbol timing acquired by a synchronous circuit 28. The synchronous circuit 28 detects a unique word from the perch channel data to acquire slot synchronization. A reception level detection circuit 29 judges a base station using a short code of the maximum acquired reception level in the perch channel data to be the nearest. A base station transmits perch channel data in which information with respect to frame timing and information with respect to the kind of a long code used in down communication channel data are interpolated.

Abstract: A de-framer (72) in a communications gateway (22) translates videoconferencing information from a circuit-switched format to a packet-switched format. A demultiplexor (78) extracts a bitstream containing video information that includes error-correction-code fields disposed at predetermined locations with respect to synchronization bits spaced by a synchronization interval and forming a predetermined synchronization sequence. A frame checker (88) for checking the error-correction code finds codeword boundaries by comparing the predetermined synchronization sequence with sequences of synchronization-interval-spaced video-bitstream bits until it finds a match. To do so, the frame checker (88) takes a group of video-bitstream words offset from each other by the synchronization interval. It compares each word in the group with a respective synchronization word consisting of a word-width replication of a respective synchronization bit.

Abstract: A rate alignment apparatus for a satellite includes an on-board clock, an input switch, an output switch and a ping-pong buffer pair including first and second buffers and connected to the input switch and the output switch. The first and second buffers receive a stream of digital baseband symbols recovered from an uplink signal depending on the operation of the input switch and the output switch. The first buffer of the buffer pair receives the bits in accordance with an uplink clock rate obtained from the uplink signal. The second buffer of the buffer pair substantially simultaneously empties the stored contents thereof to a third buffer in accordance with the on-board clock, the operations of the first and second buffers being reversed upon actuation of the input switch and the output switch. First and second correlators generate a spike when a header denoting when a frame in the stream of baseband symbols is detected.

Abstract: There is provided an apparatus for detecting a synchronizing signal, including a first circuit for extracting bit clocks from serial data received, a shift register for shifting the serial data bit by bit on the basis of the bit clocks, and latching the thus shifted serial data, a second circuit for counting the bit clocks, and generating word clocks in accordance with the number of count of the bit clocks for outputting parallel data, a third circuit for detecting a synchronization pattern from the serial data stored in the shift register, and generating a first synchronization-detecting signal, a fourth circuit for detecting a synchronization pattern from the parallel data, and generating a second synchronization-detecting signal, and a fifth circuit for determining whether frame synchronization is made, by the first and second synchronization-detecting signals, and generating a frame synchronization indication signal indicative of whether frame synchronization is made or not.

Abstract: A method, apparatus and article of manufacture are described. In particular two network interface devices that are connected over apath that includes a digital trunk using robbed-bit signaling use a technique to identify the presence of robbed-bit signaling. The network interface devices synchronize to bytes that are subject to robbed-bit signaling. The network interface devices must synchronize to the robbed-bit signaling to avoid transmitting information or receiving information in these signaling positions. The network interface devices then take advantage of the least significant bit positions of frames that are not used for robbed-bit signaling. This results in an increase in data carrying capacity from 56 kps to 62.7 kps.

Abstract: A network interface in a workstation computer includes a pattern matching circuit to enable the workstation computer to wake up to perform prescribed operations requested by a remote workstation. The pattern recognition circuit includes a pattern memory configured for storing a pattern entry for at least a portion of a predetermined pattern. The pattern entry includes a pattern data field and a second field specifying a number of bytes in the input data stream to be ignored prior to comparison with the pattern data field. The pattern matching circuit also includes a comparator for comparing the pattern data field with a selected group of bytes from the data stream. Pattern match logic determines whether the received data packet includes the predetermined pattern based on the comparison result.

Abstract: An object of the invention is to provide data transmission which satisfies specifications for SD-format digital interface in a transmission device using an isochronous transmission mode such as IEEE 1394 digital data transmission and reception. To achieve this object, the device for converting the data transfer rate in communication of digital audio and/or video data comprises a timing simulator and a transmission timing controller. The timing simulator receives some signals and mode signals to generate transmission basis signals for transmitting a stream of the source packets and outputs the transmission basis signals. The transmission timing controller receives the transmission basis signals and transmits packets at every cycle sync, according to fixed rules.

Abstract: A unique word (UW) differential detection system to provide a system that can expand a measurement range for the carrier frequency offset of the quasi-synchronized detection signal while maintaining detection of unique word position at a high accuracy, and maintaining a resolution for the carrier frequency at a low level. In an initial acquisition mode, the detection system uses a first UW differential detection circuit with a symbol delay N (0.5<N.ltoreq.1) and a second differential detection circuit with a symbol delay N/2 to generate a first UW detection signal of a first quasi-synchronized detection signal and first frequency offset information. The first frequency offset information reduces frequency offset of a second quasi-synchronized detection signal for demodulating a data signal.

Abstract: A method for analyzing the channel using the preceding slot synchronization sequence is provided. The method of the invention is for operating a receiver receiving a signal frame in a dynamic channel wherein the signal frame includes a plurality of slots, each including a plurality of data bits. Each of the slots further includes a synchronization sequence wherein at least a predetermined one of the slots is assigned for the receiver. The preceding slot following the receiver assigned slot includes a varying synchronization sequence which is selected from a group of predetermined synchronization sequences postulates. The method includes the steps of calculating from the preceding slot synchronization sequence an estimated taps value for each of the synchronization sequence postulates, calculating from the preceding step synchronization sequence a log likelihood metric value C(y,h) for each of the synchronization sequence postulates and selecting the synchronization word postulate having the best metric value.

Abstract: In a burst mode communications system, bursts of information with a known preamble are transmitted from a burst mode transmitter and are received by a burst mode receiver which uses the preamble to determine the presence of a burst and to determine the correct carrier frequency, carrier phase, symbol clock frequency and symbol clock phase in order to correctly recover the symbols transmitted, and thus the information contained within the burst. The present invention comprises a method of burst transmission using a preamble which contains an initial pulse and a Barker sequence following the initial pulse separated by a dead time period equal to the transmission time of at least one symbol. The preamble can be transmitted on orthogonal carriers and the order of the Barker sequence can be reversed and multiplied by minus one on one of the carriers to reduce the probability that noise events on both carriers make the Barker sequence less detectable on each channel.

Abstract: A parallel integrated frame synchronizer which implements a sequential pipeline process wherein serial data in the form of telemetry data or weather satellite data enters the synchronizer by means of a front-end subsystem and passes to a parallel correlator subsystem or a weather satellite data processing subsystem. When in a CCSDS mode, data from the parallel correlator subsystem passes through a window subsystem, then to a data alignment subsystem and then to a bit transition density (BTD)/cyclical redundancy check (CRC) decoding subsystem. Data from the BTD/CRC decoding subsystem or data from the weather satellite data processing subsystem is then fed to an output subsystem where it is output from a data output port.

Abstract: The invention presents a method of frame synchronization of Digital Video Broadcasting (DVB) data using a temporary storage area (regfile) of substantially smaller dimension than the repetition rate of the sync pattern. Synchronization is achieved by detecting the sync pattern by correlation and determining if the pattern has a fixed repetitive separation. The synchronization scheme of the invention is simple and easily implementable as an integrated circuit, using software and a microprocessor, or as discrete circuitry.

Abstract: Synchronization words, contained within a data transmission are detected by oversampling the incoming data transmission by a factor of M. Each of M samples are stored in a respective register on an ongoing basis and a receiver is activated to monitor the contents of all registers to determine if they contain a synchronization word. Commonly a plurality of registers may detect the presence of a synchronization word simultaneously. The one having the largest amplitude bit samples is selected and the receiver changes mode to monitor the output of that register while another receiver is activated to monitor all registers. This is particularly useful in detecting synchronization words or flags in data packets, particularly in modem to modem communications.

Abstract: A method and apparatus for combined timing recovery, frame synchronization and frequency offset correction in a digital receiver is provided. In general, the present invention provides a pair of correlators that operate on a set of samples output by a discriminator. A positive correlator generates a positive correlation value and a negative correlator generates a negative correlation value. The positive and negative correlation values are used to determine frame synchronization, frequency offset and timing recovery values so that timing recovery, frame synchronization and frequency offset correction may be performed simultaneously.

Abstract: A continuously adjusted bandwidth phase-locked loop is used by a B-CDMA.TM. receiver to correct for any deviation, or offset, that may exist between the received radio frequency (RF) carrier signal and the frequency of the first stage LO that converts the received RF carrier signal to an intermediate frequency (IF). The PLL in the receiver includes a filter with an adjustable bandwidth. A wider bandwidth is used during initial acquisition of the received signal. After the PLL has acquired the received carrier signal using the wider bandwidth, the bandwidth of the filter is gradually narrowed to provide a low steady-state error.

Abstract: A system and method for generating and repetitively transmitting a single modulated symbol during idle periods in user data in a digital subscriber line (DSL) communication system. The modulated symbol to be transmitted is selected such that its spectral properties match those of user data modulated symbols. For an asynchronous DSL system, and variants thereof, a preferred idle symbol is the "superframe" synchronization symbol. A separate modulated symbol would indicate the end of the idle state. In the preferred embodiment, the end-of-idle symbol is the idle symbol shifted by a 180.degree. phase shift. In a preferred embodiment, the transmitter in a DSL modem would calculate the idle state modulated symbol once at the start of the idle period and then simply repeat this symbol until the end of the idle period, in which case the transmitter would invert the final idle symbol. At the receiver, an idle state modulated symbol detector and phase detector are implemented.

Abstract: In a radio apparatus of such as digital cellular which transmit and receive audio signals upon coded, the frequency error can be detected easily and certainly even in the environment of high noise level. The frequency error .theta..sub.e is detected according to the detection result of the complex correlation value between the synchronizing signal and the standard signal.

Abstract: A pattern detector adapted for wireless communication systems includes an error calculator, a comb filter, an averager, and a threshold detector. The pattern to be detected is a sequence of pilot signal patterns whose error calculation is relatively invariant with respect to frequency offset introduced by Doppler and the local oscillator. The pattern detector processes received input samples y.sub.k to determine an error signal from the input samples y.sub.k and estimated input samples y.sub.k. The estimated input samples y.sub.k are determined using an estimated channel impulse response. When a vector of the received input samples is "aligned" with the expected header sync input samples, the level of the error signal is about equal to the level of the noise. The pattern detector determines the average level of the error signals for the last K error signals of each sample position E.sub.

Abstract: A device for synchronizing data processing, which receives input data comprising a plurality of data blocks comprising plural data sequences, and data block boundary detecting means; reference time detecting means for detecting reference time information required for updating a reference of synchronization; demultiplexing means for demultiplexing the input data; N pieces of means for detecting data processing/output time from one of the data sequences that shows a time to process and output data; and means for synchronizing data processing/output, according to the data processing/output time information detected by the N pieces of means for detecting data processing/output time, so that the N pieces of data processing/output means are synchronized with each other and process and output the data in the respective data sequences in correct timings along the temporal order.

Abstract: A radio receiver apparatus and method for decoding a received signal based on a predetermined pattern of synchronization signal which is inserted in a predetermined period comprising demodulating a received signal to a base band signal, decoding the demodulated signal to a data signal, generating a reference signal based on an output of the decoding and detecting a complex correlation value between the data signal and the reference signal wherein the detected synchronizing signal is based on the detected complex correlation value and decoding is based on the detected synchronization signal.

Abstract: A communication-line-quality measuring system includes transmission and terminal equipment. Transmission equipment has a first frame assembling part transmitting a down-link multiplexed frame signal to a down-link line having a first frequency, and a first frame disassembling part disassembling an up-link multiplexed frame signal transmitted through an up-link line having a second frequency. Terminal equipment has a second frame disassembling part disassembling the down-link multiplexed frame signal, and a second frame assembling part transmitting the up-link multiplexed frame signal obtained by frame-multiplexing an output signal of the subscriber unit with a control signal, to the up-link line. A pattern generation part in the first frame assembling part provides a test signal to an available channel of signal frames in the down-link multiplexed frame signal.

Abstract: A base station transmits, in addition to a pilot channel, signals which are multiplexed with pilot symbols inserted in the respective signals in communication channels. As the transmission of the pilot channel as a reference signal for coherent detection is unnecessary with high power so as to attain high reliability, the pilot channel can be transmitted with low power by means of weight in comparison with the communication channel, so that interference with the communication channel of any other station is reduced. Moreover, accurate coherent detection can be made from the pilot symbol inserted in the communication channel on the mobile station side.

Abstract: In a transmission system a sequence of digital symbols including concatenated words, is transmitted by a transmitter (2) via a transmission medium (14) to a receiver (16). In order to reduce the transmission capacity no word synchronizing symbols are introduced in the sequence of digital symbols. In order to achieve word synchronization, a synchronization processor estimates the probability function of one single predetermined string as function of the position of the string in the sequence. The correct position of the words is derived from this probability function.

Abstract: A transmission network having a plurality of transmitter stations receiving signals over different transmission links from a common source. The transmitter stations transmit frames including the same data packets, substantially simultaneously over the same frequency. To ensure that the same data packets are included in each given frame, the source adds frame start codes to the signals transmitted over the links.

Abstract: In a direct sequence spread spectrum digital communication receiver, a system and method for recovering and verifying the timing or phase of a pseudo-random noise (PN) sequence used for despreading received signals. In one embodiment, the method includes steps of: (a) determining an initial value of a received PN phase, (b) setting the receiver's PN phase equal to the initial value of the received PN phase, (c) a first testing to verify that the receiver identifies a SYNC field within a testing time of predetermined duration, (d) a second testing, to verify that temporarily shifting the receiver's PN phase results in a degraded correlation between the receiver's PN sequence and the received signal, and (e) repeating steps (a)-(d) if either of the testings indicate that the receiver's PN sequence is not correct.

Abstract: In a digital communication system for voice signals, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for direct-sequence spreading and despreading of the communicated signals. In one embodiment, a received signal is a time-division duplexing (TDD) or time-division multiple access (TDMA) signal, and a receiver performs a complete "sliding correlator" examination of the received signal in a fixed time by using the timing of the TDMA or TDD frames. This examination allows a rapid initial acquisition of the PN synchronization. In another embodiment of the receiver, the initially acquired PN phase is verified by reading a SYNC field from the received signal and by checking that shifting the receiver's local PN phase results in a degraded correlation between the local PN sequence and the received signal.

Abstract: A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectively complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity.

Abstract: A method and an arrangement for synchronizing a receiver for digital signals are described. The synchronizing information is derived from the center of distribution of the squared channel impulse response, which center of distribution is calculated directly from the sampling values of the channel frequency response. Thus a separate calculation of the channel impulse response via an inverse Fourier transform from the channel frequency response is unnecessary. The channel frequency response can be determined in a simple way by correlation of a received signal with a reference signal stored in memory in the receiver.

Abstract: A sync detect circuit is comprised of two serial data registers (40) and (42), each for storing a single word. A plurality of current sources in current source banks (44) and (46) are operable to convert the bits in the stored sync word to a differential current domain. Depending upon the logic state, the currents are added on two lines (50) and (52). When the differential current falls below a predetermined limit, a frame sync signal is generated to latch the next and following words into a data latch (34). These are then transferred out to a system upon the generation of a system data clock.

Abstract: An audio decoder decodes audio frames included in a Motion Picture Experts Group (MPEG) bitstream for presentation or playing. Each audio frame includes a synchronization code and a frame header, followed by audio data. The synchronization codes are detected, and it is determined that the decoder is synchronized to the bitstream after a first predetermined number, for example three, of successive valid audio frames have been detected. It is similarly determined that the decoder is unsynchronized to the bitstream after a second predetermined number, which can also be three, of successive invalid audio frames have been detected. Each and every frame is determined to be valid if its header parameters are valid, it passes the CRC error check (optional), no syntax errors are detected and its frame length (interval) is as expected.

Abstract: An antenna assembly providing selectable omnidirectional or directional reception of radio transmissions in a frequency band in accordance with the invention includes an electrically conductive reflector (432) defining a cavity (702) having a bottom (708), an opening (714) and a surface (704 and 706) extending from the bottom to the opening and an electrical output (763); an electrically conductive loop (431) coupled to ground and having an electrical outlet (766) for coupling to an RF amplifier (407), the loop being positioned between the bottom opening of the cavity; a RF switch (406) having an input (760) and first and second outputs (762 and 764), the RF switch having a first switching state electrically connecting the input to the first output and a second switching state electrically connecting the input to the second output, the first switch output being electrically coupled to ground and the second switch output being electrically coupled to the output of the electrically conductive loop; and wherein

Abstract: In a method and system for transmitting digital data, a data acceptance clock signal generator that has a controllable clock frequency in a peripheral module is correspondingly adapted to clock frequency information derived from a synchronization pulse train transmitted by a central unit. The same oscillator is used as a frequency source for determining the clock frequency information and for generating the data acceptance clock pulse. In this manner, simple RC oscillators are adequate to fulfill any requirements of long time accuracy of the oscillator. The clock frequency can be changed in that the central unit simply transmits altered clock frequency information. It is also possible to carry out an adjustment or adaptation in the case of deviations of the oscillator frequency in the peripheral unit.

Abstract: An apparatus is disclosed for synchronizing frames in a continuous stream of digital data consisting of a plurality of master frames (M-bits long) containing data and a constant synchronization word and having an associated bit clock. The apparatus includes a FIFO buffer, a synchronization word register (containing the constant synchronization word) and a comparator operably connected to the FIFO buffer and the synchronization word register to generate a sync detect signal representing whether the portion of the continuous stream of data contained in the FIFO matches the constant synchronization word. The apparatus further includes a frame bit counter controlled by the sync detect signal and the associated bit clock, which generates a frame sync signal every M-bits, a counter connected to a first comparator that generates a sync achieved signal upon the counter output value equaling a first predetermined value and means for incrementing the counter upon coincidence of the sync detect and frame sync signals.

Abstract: A data variation detecting system can perform detection of data variation at an arbitrary timing without lowering process performance of a processing unit, and without requiring expansion of a memory region in the processing unit. In the data variation detecting system, a recent data and a preceding data are taken from a shift register, are compared by a comparator circuit for detecting whether data variation is present or not by a data variation detecting circuit. The recent data is stored in a memory of an interface circuit with a data holding circuit. A result of detection by the data variation detecting system is directly stored in the memory in the interface circuit. When data variation is detected, operation of storing the recent data by the shift register and the data holding circuit is disabled via a masking circuit. The occurrence of data variation is detected by the processing unit via the interface circuit, the processing unit obtains the recent data from the interface circuit.

Abstract: A continuous synchronization adjustment algorithm is described, which continuously synchronizes frames used in digital synchronous transmissions. By letting the receiver continuously adjust the assumed frame position, rather than adjusting only once per frame as conventionally done, a significant increase in bit error rate can be achieved. When an incorrect single sync bit is detected in a frame, thereafter during the rest of the frame, the single sync bit positions that would result from an advance or delay of the frame position (e.g., due to a bit slip in the frame) are checked. The frame position is then adjusted immediately, without waiting for the beginning of the next frame. Consequently, there is a significant decrease in the number of data bits that are interpreted incorrectly or disregarded. As such, the bit error rate resulting from the present continuous algorithm is significantly improved over that resulting from prior synchronization algorithms.

Abstract: A burst signal reception method that detects specific data having a constant pattern and arranged at a predetermined position in a burst signal and performs a reception of the burst signal in synchronization with the detected specific data. Received data is thinned and sampled in a sampling period which is smaller than a sampling period of the specific data. The sampled signal and previously prepared data having the same sampling period are compared with each other to detect the specific data.

Abstract: A method is provided for detecting a synchronization word in frames of serially transmitted data. The synchronization word consists of l synchronization bits, which are transmitted one bit per frame at a known position in each frame. The method comprises the steps of: storing each incoming bit in a memory organized as groups of words, each having at least l bits, so that each group of words contains bits from a same position in consecutive frames; rotating each group of words; comparing the group of words, at each rotation, to the synchronization word.

Abstract: A digital radio communications receiver for predicting correctly a frame structure and assuring correct synchronization.

Abstract: A synchronization frame is first formatted and transmitted in accordance with the Global System for Mobile (GSM) 08.60 specification. After an initial synchronization procedure is accomplished between a transcoder/rate adaptor unit (TRAU) and a particular base transceiver station (BTS) serving a mobile station, a modified GSM 08.60 frame is thereafter used to transport greater user data payload across the established communications link. The modified frame replaces the synchronization bits included in the GSM 08.60 formatted data frame with user data to increase data payload from the conventional 13.5 Kbit/s to a more desirable 14.4 Kbit/s without altering the standardized 16 Kbit/s transmission rate supported by the IWF and the BTS.

Abstract: An internal signal within a SONET element has a transport format having overhead and payload mapped in a manner similar to the Synchronous Optical Network standard mapping, except having selected overhead bytes defined differently, including a byte used for communicating odd parity calculated over an odd number of bytes of a frame of the transport format to determine correct or incorrect parity, selected bytes used for inter-module automatic protection switching, and a pointer having a selected fixed value, along with an adjusted virtual tributary pointer in a virtual tributary mode.

Abstract: A receiver unit for receiving a time division multiplexed downlink data stream from a satellite comprises a phase shift keying demodulator for demodulating the downlink data stream into a stream of symbols. The downlink data stream comprises slots and is provided with a predetermined number of prime rate channels in respective ones of the slots by the satellite. A correlator is connected to the demodulator for locating and synchronzing to a master frame preamble inserted in the stream of symbols by the satellite. A demultiplexer is connected to the correlator for locating a time slot control channel in the stream of symbols. The time slot control channel is inserted into the stream of symbols by the satellite to identify which of the slots comprises the prime rate channels corresponding to each of a plurality of broadcast service providers. An input device is provided to allow an operator to select one the broadcast service providers and to provide an output signal to the demultiplexer.

Abstract: A byte aligner and frame synchronizer for 622 Mbit/s high speed data includes a clock divider, a data width extension circuit, a byte alignment controller, a byte alignment circuit, a pattern selector, a continuous pattern detector, a frame pulse generator, a frame sync detector, a frame sync loss detector, and frame sync error detector, and performs byte alignment very fast while also stabilizing frame synchronization by reinforcing an error correction function.

Abstract: In a time division multiple access (TDMA) radiotelephone communications system, a spread spectrum random access channel signal representing a random access message is communicated from a radiotelephone to a central station according to a spreading sequence. In response, a TDMA radiotelephone communications channel is assigned to the radiotelephone. A time division multiplexed radiotelephone communications signal is communicated between the radiotelephone and the central station on the assigned TDMA radiotelephone communications channel over a time division multiplexed carrier frequency band. Preferably, in communicating the spread spectrum random access channel signal, a random access channel signal, representing the random access channel message, is direct sequence modulated according to the spreading sequence to produce a direct sequence modulated random access channel signal. According to a two-stage detection aspect, a synchronization sequence may be associated with a plurality of spreading sequences.