Abstract: A communication function between ports on a node that does not require a common time base to be distributed across the network is disclosed. A data stream received over a first port is placed on an interlace between nodes using the time base of the first port; a second port samples the data stream on the interface and timestamps it using the time base of the second port. The data stream is timestamped by the second port and packetized before transmitted to the second node to another bridge or device. Alternatively, the first port extracts a time stamp from the data stream and calculates an offset using a cycle timer value from the bus connected to the first port. The offset is added to the cycle timer value on the bus connected to the second port and used to timestamp the data stream.

Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.

Abstract: Certain embodiments of the present disclosure relate to a method for tracking of a carrier frequency offset. A soft combined frequency tracking discriminator is proposed as a part of the closed loop structure that can provide fast tracking of the frequency offset in an initial pull-in mode, and can also track small residual frequency variance in a fine-tracking mode.

Abstract: A method for controlling operation of a receiver may include: generating an operation control signal based on a signal-to-noise ratio (SNR) value of an Nth symbol, wherein N is a natural number, of a hopping pattern included in a preamble of a packet; and controlling whether an Nth symbol of each hopping pattern included in a header or payload of the packet may be processed in response to the operation control signal. A receiver may include: an operation control signal generator that may generate an operation control signal based on a signal-to-noise ratio (SNR) value of an Nth symbol, where N is a natural number, of a hopping pattern included in a preamble of a packet; and a receiving unit that may control whether an Nth symbol of each hopping pattern included in a header or payload of the packet is processed in response to the operation control signal.

Abstract: Rapid uplink synchronization is enabled by reducing a 2D search problem to two 1D search problems, which can generally be performed in less time. Advantage is taken of fact that a mobile device sends a ranging code on multiple sub-carriers. Using the assumption that adjacent sub-carriers will have approximately equivalent channel characteristics, phase ambiguity can be removed by differentially combining pairs of adjacent sub-carriers. Once the phase ambiguity is removed, the code, timing, and power level may be determined relatively quickly. In one embodiment, the values of correlations between received signals and possible codes are compared with a threshold.

Abstract: A method of dynamically adjusting the buffer delay of an adaptive jitter buffer of a network node receiving packets of a media stream from a packet switched network. The method comprises inserting packets arriving to the network node into the jitter buffer and executing a jitter buffering procedure once every Trepin, wherein Trepin is equal to the jitter buffer play-out interval. Executing the jitter buffer procedure involves updating a jitter protection time, Tjit, wherein Tjit defines a current target value for the maximum buffering delay, on the basis of the variation of the number of pending packets, N in the jitter buffer.

Abstract: In an example embodiment, a method for synchronizing clocks between a plurality of clocked devices where one of the plurality of clocked devices is not directly synchronized with another of the plurality of clocked devices. Clock offset and a clock drift between a first clock associated with a first device and a second clock associated with a second is directly determined based on signals exchanged between the first and second devices. Clock offset and clock drift between the second clock and a third clock associated with a third device is directly determined based on signals exchanged between the second and third devices. A clock offset and clock drift between the first clock and third clock is determined based on a difference between the clock offset and drift between the first and second clocks and the clock offset and drift between the second and third clocks.

Abstract: Pipeline analog-to-digital converters (ADCs) are commonly used for high frequency applications; however, operating at high sampling rates will often result in high power consumption or tight timing constraints. Here, though, an ADC is provided that allows for relaxed timing (which enables a high sampling rate) with low power consumption. This is accomplished through the use of multiplexed, front-end track-and-hold (T/H) circuits that sample on non-overlapping portions of a clocking signal in conjunction with “re-used” or shared analog processing circuitry.

Abstract: A method of controlling a jitter buffer includes writing, buffering and reading data having a series of voice data frames. Writing and buffering the data is executed synchronously and repeatedly. Writing the data includes detecting whether the data packet is normally received, and calculating a storage address for each of the voice frames. Buffering the data includes buffering the voice frames in a corresponding storage address calculated in the data writing. Reading the data includes transmitting the voice data frames to a voice digital processor (VDSD) for playing.

Abstract: A device is disclosed that makes packetized and encoded speech data audible to a listener, as is a method for operating the device. The device includes a unit for generating a synchronization request for reducing an amount of synchronization delay, and further includes a speech decoder that is responsive to the synchronization delay adjustment request for executing a time-warping operation for one of lengthening or shortening a duration of a speech frame. In one embodiment the speech decoder comprises a code excited linear prediction (CELP) speech decoder, and the CELP decoder time-warping operation is applied to a reconstructed excitation signal u(k) to derive a time-warped reconstructed signal uw(k).

Abstract: A wireless communications device may include a portable housing and a temperature-compensated clock circuit carried by the portable housing. The device may further include a wireless receiver carried by the portable housing for receiving timing signals, when available, from a wireless network, and a satellite positioning clock circuit carried by the portable housing. A clock correction circuit may be carried by the portable housing for correcting the temperature-compensated clock circuit based upon timing signals from the wireless network when available, and storing historical correction values for corresponding temperatures. The clock correction circuit may also correct the temperature-compensated clock circuit based upon the stored historical correction values when timing signals are unavailable from the wireless network, and correct the satellite positioning clock based upon the temperature-compensated clock circuit.

Abstract: An apparatus for reproduction of an image frame in an image receiving system is disclosed. The apparatus includes a demultiplexer for restoring a received signal to a decodable bitstream and generating start information of each image frame of the bitstream, and an image decoder for decoding the bitstream restored by the demultiplexer, thereby generating a reproducible I frame or P frame, which is an image frame; an image reproduction time uniformity processing module for buffering each image frame output from the image decoder, and then outputting the buffered I frame or P frame while delaying the I frame or P frame based on the start information of each image frame provided by the demultiplexer according to a preset delay time. The present delay time has been preset to be greater than a processing time period required for decoding of an I frame and to be less than a time interval between image frames in the image bitstream.

Abstract: A system, method, and computer readable medium for time stamp offset in data packet bundling including filling a globally distributed time stamp based upon a globally distributed time, receiving a signal unit, resolving a difference in time between the globally distributed time stamp and the reception of the signal unit and assigning a time offset based upon the resolved time difference.

Abstract: The present invention relates to the domain of video equipment. In particular, the invention relates to a device able to receive packets in a network. The device comprises: means for receiving packets containing samples realized at a period, means for regenerating a ramp by means of a loop that delivers a clock, means for initializing, at every zero-crossing of the ramp, a counter whose rhythm is determined by the clock, means for generating image cues at every zero-crossing of the counter, and means for reconstituting a synchronization signal from said image cues, means for transmitting the synchronization signal to an item of remote equipment to be synchronized.

Abstract: A clock supply device includes a receiving unit configured to receive frame synchronization packets from an asynchronous network and generate timing signals; a phase comparing unit configured to perform phase comparison by comparing phases of the timing signals generated by the receiving unit and clock signals generated by an internal oscillating unit; a phase variation detection unit configured to detect a frequency variation of the frame synchronization packets based on a trend of a variation amount of a phase difference that is obtained by performing a statistical process on count values obtained as a result of the phase comparison; and an oscillating frequency control unit configured to control an oscillating frequency of the internal oscillating unit when the phase variation detection unit detects the frequency variation of the frame synchronization packets.

Abstract: A jitter buffer system having a jitter buffer configured to buffer traffic and a control system coupled to the jitter buffer and configured to determine a first characteristic of the traffic in the jitter buffer, adjust the size of the jitter buffer by a constant when the first characteristic does not satisfy a first constraint for the first characteristic, determine a rate of adjusting the jitter buffer, and change the constant when the rate does not fall within a specified range.

Abstract: An arrangement is disclosed for offset compensation of a time-interleaved analog-to-digital converter, having a plurality of computing channels and being adapted to convert a signal from an analog domain to a digital domain. The arrangement comprises the time-interleaved analog-to-digital converter, an analog offset estimation and compensation unit adapted to estimate a mean offset for the plurality of computing channels, a digital offset estimation and compensation unit adapted to estimate a residual computing channel specific offset for each of the plurality of computing channels, and offset compensation means. The offset compensation means are adapted to perform offset compensation in the analog domain of each of the plurality of channels based on the estimated mean offset in the analog domain, and to perform offset compensation in the digital domain of each of the plurality of channels based on respective residual computing channel specific offset.

Abstract: Provided is a media player comprising a connector to which a cable for transmitting a media signal from an external source is connected, and a user manipulator, the media player including a signal processor for processing the media signal transmitted through the cable; a UI generator for generating a setting menu for setting characteristics of the cable; and a controller for controlling the signal processor to process the media signal on the basis of the set characteristics of the cable inputted through the setting menu by the user manipulator. The media player and a control method thereof provides a user interface (UI) allowing a user to input information about cable characteristics, and process a signal according to the cable characteristics inputted by a user.

Abstract: A latency control mechanism for a communication system provides a known constant end-to-end delay between an audio source and one or more end node destinations, even in the case where different paths are used to reach the end nodes. A very low jitter time on the end-to-end latency is obtained, and the latency is controllable within a given range in dependence on the constraints imposed by the implementation. A block RX DPLL and latency control unit adjusts the reading moment and position from the RX buffer so that a delay between the time stamp taken at the source side by the transmitter time stamp unit, and the time stamp taken at the receiver side by receiver time stamp unit is constant and equal to a given value.

Abstract: Embodiments of methods, systems and apparatus for analysis and capture of network data items are described herein. Some embodiments include a receiving module which may receive a network data item from a network and which may then duplicate the network data item into two network data items. A capture module may receive one of the network data items for storage in storage device. A statistics or analysis module may in parallel receive the other network data item and may then perform network analysis on that network data item. Other embodiments are described and claimed.

Abstract: A communication terminal includes first and second transmitters, which are coupled to produce respective first and second Radio Frequency (RF) signals that are phase-shifted with respect to one another by a beamforming phase offset, and to transmit the RF signals toward a remote communication terminal. The terminal includes a reception subsystem including first and second receivers and a phase correction unit. The first and second receivers are respectively coupled to receive third and fourth RF signals from the remote communication terminal. The phase correction unit is coupled to produce, responsively to the third and fourth RF signals, a phase correction for correcting an error component in the beamforming phase offset.

Abstract: Embodiments of the present invention provide a method/apparatus to measure the jitter of a timing signal used in an integrated circuit chip. The method/apparatus is used to send data from a launch element using a synchronous data path of the timing signal, receive the data at a capture element using the synchronous data path, wherein the launch element and the capture element are disposed on the same integrated circuit chip upon which the timing signal is generated and/or used, and gather statistics about whether a timing violation has occurred by comparing the sent data with the received data over the course of multiple launch/capture events as the timing is adjusted. Other embodiments may be described and/or claimed.

Abstract: A receiver receiving a transport stream to demodulate the transport stream into a final output stream, wherein the transport stream comprises a plurality of symbols at least one of which carrying at least one program clock reference (PCR) value, and the final output stream comprises a plurality of demodulated symbols each comprising a plurality of packets, is disclosed. The receiver can comprise a Reed-Solomon decoder configured to decode the transport stream to generate a MPEG (Motion Pictures Expert Group) packet, a MPEG memory configured to store the MPEG packet, and a descrambler configured to read the MPEG packet from the MPEG memory with a throughput rate and descramble the MPEG packet into one of the packets of the demodulated symbols of the final transport stream. The throughput rate is decreased to reduce bursts of the packets of the demodulated symbols of the final output stream.

Abstract: An apparatus for controlling utilization of RTCP bandwidth for compound and non-compound RTCP packets is described. This apparatus includes a bandwidth detector determining available RTCP bandwidth and a channel quality detector determining channel quality. A bandwidth divider connected to the bandwidth detector and the channel quality detector divides the available RTCP bandwidth between compound and non-compound RTCP packets based on the determined channel quality.

Abstract: A network statistics processing device comprises a port processing unit for determining an update from a forward statistic metric carried by an input PDU, an arbitration unit for placing the updates into a scheduled stream of updates, and a memory unit for storing statistic totals relating to the network operating parameters. The port processing unit also processes the statistic results retrieved from the memory into reverse statistic metrics that are inserted into an output PDU. A statistics monitoring and processing unit enables performance of high level statistical processing on selected updates and on the results. A method of generating and maintaining statistic totals on a plurality of network operating parameters is also described.

Abstract: A communication system and method is disclosed that performs symbol boundary synchronization by generating a symbol alignment estimate from a partial signal correlation; and then refining the symbol alignment estimate via a carrier phase calculation. To generate the symbol alignment estimate, two methods are disclosed. After an estimate is determined, an embodiment provides for refining the symbol alignment estimate via a carrier phase calculation by determining a carrier phase of two adjacent carriers, determining a phase error as directly proportional to an offset from the start of a symbol, determining a phase difference contribution due to a communication channel and device hardware, and counter-rotating the determined carrier phase by an angle of a constellation point at a transmitter.

Abstract: A communication apparatus that includes a media processing device that includes at least one codec and that encodes data, a packet processing device that transmits and receives packet data, a correlation value computation device that computes a correlation value between jitter of packet data transmitted to a partner communication apparatus and jitter of packet data transmitted from the partner communication apparatus, and a session control device that, in a case where the correlation value computed by the correlation value computation device is equal to or larger than a specified value, performs one of an encoding speed conversion within a codec in use, a transmission packet length conversion, a packet transmission interval conversion, a packet transmission priority conversion, and a codec type conversion from the codec in use to another type of codec, based on QoS information of the packet data transmitted from the partner communication apparatus.

Abstract: A phase error detector in a base transceiver station detects a phase error caused by a Doppler shift in a received wave from a mobile station. A phase rotator rotates a phase of a transmission symbol in a base band region so as to cancel the Doppler shift, which occurs in a downlink from a base transceiver station to a mobile station based on the phase error detected by the phase error detector.

Abstract: A system for the end-to-end delivery of digital television signals. In a preferred embodiment a digital television signal is: received from production equipment, typically in HD format at approximately 1.4 gigabits per second (Gbps); the received signal is transmitted to a venue point-of-presence; converted for transmission via a 270 Mbps local loop; transmitted to a fiber network point of presence/video service edge; packetized into TCP/IP packets in a video gateway; and routed to one or more destination addresses via the fiber network; received at one or more video service edge destinations; converted to a digital television format, typically SDI; and either transmitted via a second 270 Mbps local loop for delivery to a customer site and subsequent conversion to a 1.4 Gbps HD signal, or converted directly to a 1.4 Gbs HD signal at the receiving video service edge.

Abstract: The present invention relates to a sending device able to send packets in a network comprising at least two stations, the said device comprising means for extracting image pips on the basis of a synchronization signal, initializing an image counter on the basis of the image pips, initializing a counter every “m” zero-crossings of the image counter, the counter being regulated by a clock produced by the image counter, sampling the counter every period Tsmp, where Tsmp emanates from a time base synchronized on all the stations of the said network; and sending packets containing the samples of the counter in the network.

Abstract: Disclosed herein is a carrier synchronizing circuit including at least frequency synchronizing means and phase synchronizing means. The phase synchronizing means includes residual frequency error detecting means for detecting a residual frequency error after a frequency synchronizing process by the frequency synchronizing means and supplying the residual frequency error to the frequency synchronizing means, and the frequency synchronizing means performs frequency pull-in for the residual frequency error supplied from the residual frequency error detecting means after first timing.

Abstract: The communication system having a transmitter and a receiver, wherein the transmitter and the receiver are coupled by a clock channel and a data channel, wherein the clock channel is shorter than the data channel and wherein the receiver comprises a delay circuit for extracting a jitter signal from a clock channel signal, delaying the extracted jitter signal, and generating a receiver clock signal for the receiver by the delayed jitter signal.

Abstract: A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

Abstract: An apparatus and method of buffering a media stream is provided. The method may comprise receiving a plurality of IP packets of the media stream, each packet providing a fragment of a portion of the media stream. Thereafter, the portion of media stream may be buffered in a jitter buffer using the fragments provided by the received packets. Further, the portion of the media stream may be buffered in a replay buffer using the fragments provided by the received packets. The replay buffer may be larger than the jitter buffer and a first received fragment and a second received fragment may be combined. The second received fragment may have been discarded by the jitter buffer. A media stream may then be played back using media from the replay and/or jitter buffer.

Abstract: In one embodiment, the present invention comprises a vocoder having at least one input and at least one output, an encoder comprising a filter having at least one input operably connected to the input of the vocoder and at least one output, a decoder comprising a synthesizer having at least one input operably connected to the at least one output of the encoder, and at least one output operably connected to the at least one output of the vocoder, wherein the encoder comprises a memory and the encoder is adapted to execute instructions stored in the memory comprising classifying speech segments and encoding speech segments, and the decoder comprises a memory and the decoder is adapted to execute instructions stored in the memory comprising time-warping a residual speech signal to an expanded or compressed version of the residual speech signal.

Abstract: A time to digital converter is used to determine which edge of the higher frequency clock (oversampling clock) is farther away from the edge of the lower frequency timing signal. At the same time, the oversampling clock performs sampling of the timing signal by two registers: one on the rising edge and the other on the falling edge. Then, the register of “better quality” retiming, as determined by the fractional phase detector decision, is selected to provide the retimed output.

Abstract: Disclosed is an apparatus comprising a jitter buffer that writes and reads packets transmitted via a packet network from a transmission node, a clock correction unit that obtains an inter-packet jitter, based on difference information between time stamp information at the time of reception of the packet on a receiving side and time stamp information attached to the packet at the time of transmission of the packet by a transmission node with regards to packets received before and after and obtains a transmission frequency and a PLL unit that receives frequency information from the clock correction unit and generates a clock of the frequency. A scheduler uses a frequency from the PLL unit as a transmission frequency to transmit a packet from the jitter buffer unit.

Abstract: In a receiving device, time information is separated from received multimedia data, a first difference is calculated between two consecutive pieces of time information, and a second difference is calculated between reception timings of the two consecutive time information. Jitter is calculated from the first difference and the second difference, and a clock for reproducing the multimedia data is adjusted based on the calculated jitter.

Abstract: After detecting the predetermined phase rotation, a receiver can advantageously remove any cyclic shifting delays (CSDs) from the mixed mode packet for each chain. Once any CSDs are removed, the receiver can perform timing offset estimation and decode the mixed mode packet. In another embodiment, a timing offset from a channel for a first chain without any CSDs can be estimated. Compensation for the timing offset in the first chain can then be performed. At this point, the CSDs from other chains can then be removed. After CSD removal, compensation for any timing offsets in the other chains can be performed using the timing offset in the first chain.

Abstract: Methods and systems of employing a dedicated device for position estimation by a WLAN-based positioning system. A device estimates the position of itself in response to gathering wireless signal information from WLAN access points (APs). The device includes a receive-only WLAN radio module for receiving WLAN signals transmitted by WLAN APs in range of said device, extraction logic for extracting information from said received WLAN signals to identify the WLAN APs; and logic to cooperate with a WLAN-based positioning system to estimate the position of the device based at least in part on the extracted information identifying the WLAN APs in the range of said device. In other embodiments, the radio module includes a transmitter but one which is only capable of transmitting probe requests.

Abstract: According to an example embodiment, a circuit may include a first pair of differential input transistors, each coupled between at least an associated first positive clock transistor and ground; the first positive clock transistors coupled between differential output nodes and the differential input transistors associated with the first positive clock transistors, the first positive clock transistors being configured to respond to a positive input from a clock; a first inductor coupled between the differential output nodes and a voltage source; a second pair of differential input transistors, each coupled between at least an associated first negative clock transistor and ground; the first negative clock transistors coupled between the differential output nodes and the differential input transistors associated with the first negative clock transistors, the first negative clock transistors being configured to respond to a negative input from the clock; and the differential output nodes coupled between the first

Abstract: A multi-program multiplexing/demultiplexing method and apparatus for preventing MPEG jitters from being generated in a digital broadcast, and a multi-program receiver using the multi-program multiplexing/demultiplexing apparatus are provided. The multi-program multiplexing method comprises: extracting a plurality of transport stream packets from a plurality of channel decoders; comparing a reference clock value of each transport stream packet with a system clock value latched by the reference clock value, and generating a system clock control value; inserting the system clock value into a local packet of each channel; and multiplexing a plurality of local packets of a plurality of channels and generating a multi-program packet.

Abstract: A packet scheduler reduces or “compresses” the packet transmission delay jitter or delay range where packets experience little or no scheduling delay before transmission. As a result, the number of packets that experience little or no delay is reduced. A preferred example way of compressing the packet transmission delay jitter is to reduce the transmission priority of low delay packets. Compressing the delay jitter is particularly desirable for services like VoIP that require low packet transmission delay jitter.

Abstract: In VoIP systems, there is a tradeoff between reducing number of lost packets and end-to-end delay when dealing with jitters. Increasing the jitter buffer space on a mobile wireless terminal reduces the likelihood of lost packets but increases the end-to-end delay. Decreasing the jitter buffer space shortens the end-to-end delay, but there is a greater likelihood of retransmissions and dropped packets. Optimum solution can be arrived at if the jitter buffer space on the mobile wireless terminal can be matched to the scheduling delay. This is difficult to achieve in conventional system because the scheduling delay introduced by the network is unknown to the mobile wireless terminal. Thus, constant adjustment is required. One way to overcome this problem is to apprise the mobile wireless terminal of the maximum scheduling delay.

Abstract: A method and apparatus for synchronising a serial data signal to a reference clock signal, the data signal comprising frames of equal length each comprising a known frame alignment word (FAW) and a payload, the frame alignment word being in a consistent position within each frame, the method comprising: storing the signal in a FIFO wander buffer as it is received in order to compensate for any wander that may occur; outputting the data signal stored in the FIFO wander buffer synchronised to the reference clock signal; searching for at least a portion of the frame alignment word in the data signal as it is received; and when it is determined that the frame alignment word has been found, realigning the data signal within the wander buffer. The step of realigning the data may comprise replacing at least a portion of the data signal in the wander buffer with a locally-held copy of at least a portion of the frame alignment word. The method may be used in any synchronous serial data stream, such as SDH or SONET.

Abstract: Mechanisms are disclosed for using two or more buffers, at a common receiving node, to reduce the effects of jitter, packet loss, and/or packet latency and/or synchronize different types of packets. Specifically, the two or more buffers can be used to temporarily store packets from different media streams that have a common timestamp and/or sequence number. Characteristics of the two or more buffers can then be independently controlled to accommodate the different media streams.

Abstract: A device and method are disclosed for correctly restoring a read clock when there are a plurality of STM data stream transmission sources. In a CES device of an ATM communication system, ATM cells from respective connections, which are to be delivered to the same outgoing line, are accumulated in a reassembly buffer memory and a PLO control unit aggregates the amount of ATM cells accumulated in the reassembly buffer memory for each connection. Subsequently, the PLO control unit calculates the frequency of a read clock based on the amount of accumulated ATM cells for each connection. A PLO restores the read clock which is applied to read data from the reassembly buffer memory for delivery to an STM network.

Abstract: Systems and methods to measure the performance of a de-jitter buffer are disclosed. In a described example, a method to measure adaptive de-jitter buffer performance includes transmitting a known audio signal via a plurality of packets over a packet-based network, recording a received signal based on the known audio signal, and analyzing the recorded signal to determine one or more of a lower de-jitter buffer size, an upper de-jitter buffer size, a de-jitter buffer expansion speed, or a de-jitter buffer contraction speed based on the recorded signal and the known signal. The example method further includes comparing the one or more of the lower de-jitter buffer size, the upper de-jitter buffer size, the expansion speed, or the contraction speed to a performance requirement, and correcting communication network performance based on the comparison.

Abstract: Disclosed are an apparatus and a method for preventing data read error for OFDM symbol demodulation. An average time synchronization offset estimating unit estimates average time synchronization offset between a pilot symbol of a time synchronized data frame and pilot symbols of data frames next to the time synchronized data frame. A data buffer control unit acquires a start location of a data frame to be read using the estimated average time synchronization offset, and controls reading of written data frames using the acquired start location information of the data frame to be read. In the apparatus and the method, a data buffering using a ring buffer construction may compensate time synchronization offset of samples containing real data in an OFDM symbol and prevent an erroneous read error in order to improve a receiving performance of a receiver.

Abstract: A method and a circuit for obtaining asynchronous demapping clock. The method includes: obtaining a smoothed clock with even gaps in accordance with data to be demapped and a corresponding clock signal; performing phase locking in accordance with a signal reflecting writing and reading conditions of data of a First In First Out (FIFO), to obtain a clock signal required for demapping. The method can effectively filter off jittering created during asynchronous mapping/demapping processes and may ensure a high-performance clock output. Furthermore, the method is applicable to not only mapping from OTN to SDH but also other asynchronous demapping processes, e.g., mapping from SDH to OTN, and thereby effectively improving the performance of data demapping.