Particular Confinement Layer Patents (Class 372/45.01)
  • Patent number: 9755403
    Abstract: Methods are provided for modifying the emission wavelength of a semiconductor quantum well laser diode, e.g. by blue shifting the emission wavelength. The methods can be applied to a variety of semiconductor quantum well laser diodes, e.g. group III-V semiconductor quantum wells. The group III-V semiconductor can include AlSb, AlAs, Aln, AlP, BN, GaSb, GaAs, GaN, GaP, InSb, InAs, InN, and InP, and group III-V ternary semiconductors alloys such as AlxGai.xAs. The methods can results in a blue shifting of about 20 meV to 350 meV, which can be used for example to make group III-V semiconductor quantum well laser diodes with an emission that is orange or yellow. Methods of making semiconductor quantum well laser diodes and semiconductor quantum well laser diodes made therefrom are also provided.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: September 5, 2017
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Boon Siew Ooi, Abdul Majid Mohammed, Rami Afandy, Ahmad Aljabr
  • Patent number: 9748426
    Abstract: A monolithic multiple solar cell includes at least three partial cells, with a semiconductor mirror placed between two partial cells. The aim of the invention is to improve the radiation stability of said solar cell. For this purpose, the semiconductor mirror has a high degree of reflection in at least one part of a spectral absorption area of the partial cell which is arranged above the semiconductor mirror and a high degree of transmission within the spectral absorption range of the partial cell arranged below the semiconductor mirror.
    Type: Grant
    Filed: January 17, 2016
    Date of Patent: August 29, 2017
    Assignee: Azur Space Solar Power GmbH
    Inventors: Matthias Meusel, Gerhard Strobl, Frank Dimroth, Andreas Bett
  • Patent number: 9739943
    Abstract: A rectangular optical waveguide, an optical phase shifter and an optical modulator each formed of a semiconductor layer are formed on an insulating film constituting an SOI wafer, and then a rear insulating film formed on a rear surface of the SOI wafer is removed. Moreover, a plurality of trenches each having a first depth from an upper surface of the insulating film are formed at a position not overlapping with the rectangular optical waveguide, the optical phase shifter and the optical modulator when seen in a plan view in the insulating film. As a result, since an electric charge can be easily released from the SOI wafer even when the SOI wafer is later mounted on the electrostatic chuck included in the semiconductor manufacturing apparatus, the electric charge is less likely to be accumulated on the rear surface of the SOI wafer.
    Type: Grant
    Filed: March 12, 2016
    Date of Patent: August 22, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuya Usami, Keiji Sakamoto, Hiroyuki Kunishima
  • Patent number: 9741888
    Abstract: A monolithic multiple solar cell includes at least three partial cells, with a semiconductor mirror placed between two partial cells. The aim of the invention is to improve the radiation stability of said solar cell. For this purpose, the semiconductor mirror has a high degree of reflection in at least one part of a spectral absorption area of the partial cell which is arranged above the semiconductor mirror and a high degree of transmission within the spectral absorption range of the partial cell arranged below the semiconductor mirror.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: August 22, 2017
    Assignee: Azur Space Solar Power GmbH
    Inventors: Matthias Meusel, Gerhard Strobl, Frank Dimroth, Andreas Bett
  • Patent number: 9735549
    Abstract: Photonic integrated circuits (PICs) are based on quantum cascade (QC) structures. In embodiment methods and corresponding devices, a QC layer in a wave confinement region of an integrated multi-layer semiconductor structure capable of producing optical gain is depleted of free charge carriers to create a low-loss optical wave confinement region in a portion of the structure. Ion implantation may be used to create energetically deep trap levels to trap free charge carriers. Other embodiments include modifying a region of a passive, depleted QC structure to produce an active region capable of optical gain. Gain or loss may also be modified by partially depleting or enhancing free charge carrier density. QC lasers and amplifiers may be integrated monolithically with each other or with passive waveguides and other passive devices in a self-aligned manner. Embodiments overcome challenges of high cost, complex fabrication, and coupling loss involved with material re-growth methods.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: August 15, 2017
    Assignees: Massachusetts Institute of Technology, Pendar Technologies, LLC
    Inventors: Anish K. Goyal, Laurent Diehl, Christian Pfluegl, Christine A. Wang, Mark Francis Witinski
  • Patent number: 9735545
    Abstract: A vertical cavity surface emitting laser (VCSEL) including a substrate and a bottom distributed Bragg reflector (DBR) having a plurality of layers deposited on the substrate. The VCSEL also includes a first charge confining layer deposited on the bottom DBR, an active region deposited on the first charge confining layer, and a second charge confining layer deposited on the active region. A current blocking layer is provided on the second charge confining layer, and a top epitaxial DBR including a plurality of top epitaxial DBR layers is deposited on the current blocking layer. A top electrode is deposited on the top epitaxial DBR, a bottom electrode is deposited on the bottom DBR and adjacent to the active region, and a top dielectric DBR is deposited on the top epitaxial DBR and the top electrode.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: August 15, 2017
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Yaochung Chen, Vincent Gambin, Xianglin Zeng
  • Patent number: 9726818
    Abstract: A photonic waveguide for conducting light having first and second wavelengths, the waveguide comprising superposed first and second strips of light conducting semiconductor materials having first and second refractive indexes, wherein the second wavelength is shorter than the first wavelength and the second refractive index is higher than the first refractive index, wherein the width and height of the first strip of light conducting semiconductor material are such that the first strip of light conducting semiconductor material is adapted to confine an optical mode of the first wavelength and the width and height of the second strip of light conducting semiconductor material are such that the second strip of light conducting semiconductor material is adapted to confine an optical mode of the second wavelength but is too narrow to confine an optical mode of the first wavelength.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: August 8, 2017
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel Yap, Troy Rockwood, Kevin Geary, Sarabjit Mehta
  • Patent number: 9722396
    Abstract: A surface emitting laser element capable of emitting a main beam and a sub-beam, and a monitoring light detection element capable of detecting a light intensity of the sub-beam are included, the surface emitting laser element is a PCSEL, the main beam and the sub-beam are emitted in an upward direction of the surface emitting laser element and are inclined to each other at a predetermined angle, and respective changes in a peak light intensity of the main beam and a peak light intensity of the sub-beam with respect to a value of a driving current of the surface emitting laser element are correlated with each other. Therefore, if an output of the monitoring light detection element indicating the peak light intensity of the sub-beam is used, the peak light intensity of the main beam can be estimated.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: August 1, 2017
    Assignees: KYOTO UNIVERSITY, HAMAMATSU PHOTONICS K.K.
    Inventors: Akiyoshi Watanabe, Yoshitaka Kurosaka, Kazuyoshi Hirose, Takahiro Sugiyama, Susumu Noda
  • Patent number: 9705044
    Abstract: To suppress or prevent erosion (decrease in film thickness), water absorption, or cracking of a DBR film surface in washing or etching treatment in a downstream process. The DBR film structure of a DBR film 7D includes a pair of or a plurality of pairs of a deposited SiO2 film and a deposited TiO2 film. Such a top layer of DBR film structures has hitherto been a deposited SiO2 film that provides high reflectance. In order to prevent erosion while maintaining high reflectance, the top layer herein is a high-refractive-index thin film (for example, a deposited TiO2 film) having a thickness in the range of 1 to 13 nm, and a tapered DBR end portion (a slope having a taper angle in the range of 15 to 45 degrees) is formed by vapor deposition in a lift-off process. The high-refractive-index thin film is overlaid with a reflective metal film 8D serving as a first layer.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: July 11, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroshi Sasaki
  • Patent number: 9705034
    Abstract: A light-emitting diode, a method of manufacturing the same, a lamp and an illumination device. A light-emitting diode (100) is provided with a compound semiconductor layer (10) including a light-emitting layer (24) provided on a substrate (1); an ohmic contact electrode (7) provided between the substrate and compound semiconductor layer; an ohmic electrode (11) provided on the side of the compound semiconductor layer opposite the substrate; a surface electrode (12) including a branch section (12b) provided so as to cover the surface of the ohmic electrode and a pad section (12a) coupled to the branch section; and a current-blocking portion (13) provided between an under-pad light-emitting layer (24a) arranged in an area of the light-emitting layer that overlaps the pad section (12a) and a light-emitting layer arranged in an area except the area that overlaps the pad section, to prevent current from being supplied to the under-pad light-emitting layer.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: July 11, 2017
    Assignee: SHOWA DENKO K.K.
    Inventors: Atsushi Matsumura, Yuu Tokunaga
  • Patent number: 9691941
    Abstract: Optoelectric devices that comprise a semiconductor superlattice heterostructure. One or more individual layers within the semiconductor superlattice heterostructure can further comprise layers of differing thicknesses. In at least one embodiment, an optoelectric device with specially engineered layers can generate an output wavelength of between 3 ?m to 15 ?m at output power levels of 0.01 mW to 100 mW.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: June 27, 2017
    Assignee: Terahertz Device Corporation
    Inventor: Mark S. Miller
  • Patent number: 9660420
    Abstract: A laser diode with an improved kink level in the L-I characteristic and capable of obtaining a stable high output in a horizontal transverse mode is provided. The laser diode includes an active layer made of nitride III-V compound semiconductor containing at least gallium (Ga) in 3B-group elements and at least nitrogen (N) in 5B-group elements, an n-type compound semiconductor layer provided on one of faces of the active layer, and a p-type compound semiconductor layer provided on the other face of the active layer. A region closest to the active layer, in the n-type compound semiconductor layer is a high-concentration region whose impurity concentration is higher than that of the other n-type regions.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: May 23, 2017
    Assignee: Sony Corporation
    Inventors: Toshiyuki Obata, Hidekazu Kawanishi
  • Patent number: 9653647
    Abstract: Various embodiments of SST dies and solid state lighting (“SSL”) devices with SST dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a SST die includes a substrate material, a first semiconductor material and a second semiconductor material on the substrate material, an active region between the first semiconductor material and the second semiconductor material, and a support structure defined by the substrate material. In some embodiments, the support structure has an opening that is vertically aligned with the active region.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: May 16, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Odnoblyudov, Martin F. Schubert
  • Patent number: 9654283
    Abstract: An optical device comprising: a substrate; a cavity structure on the substrate, comprising a quantum emitter in contact with one or more semiconductor layers; wherein the or all of the semiconductor layers in contact with the quantum emitter have a thickness larger than the height of the quantum emitter.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: May 16, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Joanna Krystyna Skiba-Szymanska, Richard Mark Stevenson, Andrew James Shields, Jan Henning Huwer
  • Patent number: 9653440
    Abstract: An optoelectronic component includes an optoelectronic semiconductor chip having a first surface on which a first electrical contact and a second electrical contact are arranged, wherein the first surface adjoins a molded body, a first pin and a second pin are embedded in the molded body and electrically conductively connect to the first contact and the second contact, and a protection diode is embedded in the molded body and electrically conductively connect to the first contact and the second contact.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: May 16, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Jürgen Moosburger, Lutz Höppel, Norwin von Malm
  • Patent number: 9653883
    Abstract: There is provided a surface emitting semiconductor laser including: a substrate; and a semiconductor layer including: a first semiconductor multilayer film having plural sets of specific layers, a second semiconductor multilayer film having plural sets of specific layers, and an active layer provided between them, so as to constitute a resonator.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: May 16, 2017
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Junichiro Hayakawa, Akemi Murakami, Takashi Kondo, Kazutaka Takeda, Naoki Jogan, Jun Sakurai
  • Patent number: 9647063
    Abstract: A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: May 9, 2017
    Assignees: GLOBALFOUNDRIES INC., KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGY
    Inventors: Maha M. Khayyat, Devendra K. Sadana, Brent A. Wacaser
  • Patent number: 9640712
    Abstract: A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure includes a multiple quantum well structure formed by a plurality of well layers and barrier layers stacked alternately. One well layer is disposed between every two barrier layers. The barrier layer is made of AlxInyGa1-x-yN (0<x<1, 0<y<1, 0<x+y<1) while the well layer is made of InzGa1-zN (0<z<1). Thereby quaternary composition is adjusted for lattice match between the barrier layers and the well layers. Thus crystal defect caused by lattice mismatch is improved.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: May 2, 2017
    Assignee: Genesis Photonics Inc.
    Inventors: Yen-Lin Lai, Shen-Jie Wang
  • Patent number: 9618699
    Abstract: Embodiments herein describe disposing a waveguide adapter onto an SOI device after the components on a silicon surface layer have been formed. That is, the waveguide adapter is disposed above optical components (e.g., optical modulators, detectors, waveguides, etc) formed in a surface layer. In one embodiment, a waveguide in a bottom layer of the waveguide adapter overlaps a silicon waveguide in the surface layer such that the silicon waveguide and the waveguide in the bottom layer are optically coupled. The waveguide adapter also includes other layers above the bottom layer (e.g., middle and top layers) that also contain waveguides which form an adiabatic optical system for transmitting an optical signal. At least one of the waveguides in the multi-layer adapter is exposed at an optical interface of the SOI device, thereby permitting the SOI device to transmit optical signals to, or receive optical signals from, an external optical component.
    Type: Grant
    Filed: March 15, 2015
    Date of Patent: April 11, 2017
    Assignee: Cisco Technology, Inc.
    Inventors: Ravi Sekhar Tummidi, Mark Webster, Vipulkumar Patel
  • Patent number: 9620676
    Abstract: In various embodiments, light-emitting devices incorporate smooth contact layers and polarization doping (i.e., underlying layers substantially free of dopant impurities) and exhibit high photon extraction efficiencies.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: April 11, 2017
    Assignee: CRYSTAL IS, INC.
    Inventors: James R. Grandusky, Leo J. Schowalter, Muhammad Jamil, Mark C. Mendrick, Shawn R. Gibb
  • Patent number: 9617656
    Abstract: A method of making an aluminum nitride (AlN) buffer layer over a silicon wafer for a light emitting diode (LED) includes preflowing a first amount of ammonia that is sufficient to deposit nitrogen atoms on the surface of a silicon wafer without forming SiNx, before flowing trimethylaluminum and then a subsequent amount of ammonia through the chamber.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: April 11, 2017
    Assignee: Toshiba Corporation
    Inventors: William E. Fenwick, Jeff Ramer
  • Patent number: 9605337
    Abstract: A substrate structure with invisible inner electrode patterns is provided. The substrate structure includes a substrate, an electrode pattern, a first laminated structure, and a passivation layer. The electrode pattern is disposed on the substrate. The first laminated structure is disposed on the electrode pattern, in which the first laminated structure includes a first upper layer, a second upper layer, and a third upper layer. The first upper layer is adjoined to the electrode pattern and the substrate. The first upper layer, the second upper layer, and the third upper layer are stacked sequentially. The passivation layer is disposed on the first laminated structure. The refractive indexes of the electrode pattern, the first upper layer, the second upper layer, the third upper layer, and the passivation layer are decreased sequentially.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: March 28, 2017
    Assignee: TPK Touch Solutions (Xiamen) Inc.
    Inventors: I-Chung Hsu, Kuo-Shu Hsu, Ting-Hsiang Lee, Guowei Zeng, Changqing Gao
  • Patent number: 9601905
    Abstract: An optical semiconductor device outputting a predetermined wavelength of laser light includes: a quantum well active layer positioned between a p-type cladding layer and an n-type cladding layer in thickness direction; a separate confinement heterostructure layer positioned between the quantum well active layer and the n-type cladding layer; and an electric-field-distribution-control layer positioned between the separate confinement heterostructure layer and the n-type cladding layer and configured by at least two semiconductor layers having band gap energy greater than band gap energy of a barrier layer constituting the quantum well active layer.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: March 21, 2017
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Junji Yoshida, Hirokazu Itoh, Satoshi Irino, Yuichiro Irie, Taketsugu Sawamura
  • Patent number: 9577408
    Abstract: A monolithically integrated thermal tunable laser comprising a layered substrate comprising an upper surface and a lower surface, and a thermal tuning assembly comprising a heating element positioned on the upper surface, a waveguide layer positioned between the upper surface and the lower surface, and a thermal insulation layer positioned between the waveguide layer and the lower surface, wherein the thermal insulation layer is at least partially etched out of an Indium Phosphide (InP) sacrificial layer, and wherein the thermal insulation layer is positioned between Indium Gallium Arsenide (InGaAs) etch stop layers.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: February 21, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventors: Hongmin Chen, Xuejin Yan, Rongsheng Miao, Xiao Shen, Zongrong Liu
  • Patent number: 9568677
    Abstract: Embodiments of forming a waveguide structure are provided. The waveguide structure includes a substrate, and the substrate has an interconnection region and a waveguide region. The waveguide structure also includes a trench formed in the substrate, and the trench has a sloping sidewall surface and a substantially flat bottom. The waveguide structure further includes a bottom cladding layer formed on the substrate, and the bottom cladding layer extends from the interconnection region to the waveguide region, and the bottom cladding layer acts as an insulating layer in the interconnection region. The waveguide structure further includes a metal layer formed on the bottom cladding layer on the sloping sidewall surface.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao Tseng, Ying-Hao Kuo, Hai-Ching Chen, Tien-I Bao
  • Patent number: 9564738
    Abstract: A semiconductor laser device includes an n-type clad layer, a first p-type clad layer and a ridge stripe. The device also includes an active layer interposed between the n-type clad layer and the first p-type clad layer, and a current-blocking layer formed on side surfaces of the ridge stripe. The ridge stripe of the device includes a second p-type clad layer formed into a ridge stripe shape on the opposite surface of the first p-type clad layer from the n-type clad layer. The ridge stripe is formed such that a first ridge width as the width of a surface of the second p-type clad layer exists on the same side as the first p-type clad layer and a second ridge width as the width of a surface of the second p-type clad layer exists on the opposite side from the first p-type clad layer.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: February 7, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Yoshito Nishioka, Yoichi Mugino, Tsuguki Noma
  • Patent number: 9564739
    Abstract: A semiconductor laser device capable of high output is provided. A semiconductor laser diode includes: a substrate; and a semiconductor stacked structure, which is formed on the substrate through crystal growth. The semiconductor stacked structure includes: an n-type (Alx1Ga(1-x1))0.51In0.49P cladding layer and a p-type (Alx1Ga(1-x1))0.51In0.49P cladding layer; an n-side Alx2Ga(1-x2)As guiding layer and a p-side Alx2Ga(1-x2)As guiding layer, which are sandwiched between the cladding layers; and an active layer, which is sandwiched between the guiding layers. The active layer is formed of a quantum well layer including an AlyGa(1-y)As(1-x3)Px3 layer and a barrier layer including an Alx4Ga(1-x4)As layer that are alternatively repetitively stacked for a plurality of periods.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: February 7, 2017
    Assignee: ROHM CO., LTD
    Inventors: Tsuguki Noma, Minoru Akutsu, Yoshito Nishioka
  • Patent number: 9557484
    Abstract: Embodiments describe high-efficiency optical waveguide transitions—i.e., creating heterogeneous transitions between Si and III-V semiconductor regions or devices with minimal reflections. This is advantageous for III-V device performance, e.g. for an on-chip lasers achieving lower relative intensity noise (RIN) and lower phase noise by avoiding reflections, higher gain and reduced gain-ripple from an semiconductor optical amplifier (SOA) by avoiding internal reflections in the SOA. Furthermore, in some embodiments, generated photocurrent can be used as a monitor signal for control purposes, thereby avoiding the use of separate tap-monitor photodetectors, which provide additional link loss.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: January 31, 2017
    Assignee: Aurrion, Inc.
    Inventors: Erik Johan Norberg, Jonathan Edgar Roth
  • Patent number: 9553423
    Abstract: A miniature structured light illuminator is provided. The miniature structured light illuminator uses a semiconductor surface emitting array including VCSEL or RC-LED array and an array of microlens elements to generate a wide range of structured light illumination patterns. The emission beam from a surface emitter array may be selectively directed, steered, focused or expanded, by applying a lateral displacement of the microlens array, such that centers of the emission beam and microlens array are misaligned. Emitted beams may be directed through small optical components to project the structured light pattern to a distant plane. The surface emitting arrays may be configured in addressable form to be activated separately for continuous or pulsed operation with very fast pulses having <100 ps risetime. A compact structured light illuminator module with projection optics is provided in very small physical size (˜6×6×3 mm3) suitable to configure in a handheld device.
    Type: Grant
    Filed: February 27, 2016
    Date of Patent: January 24, 2017
    Assignee: PRINCETON OPTRONICS INC.
    Inventors: Tong Chen, Chuni L Ghosh, Jean-Francois Seurin, Laurence S Watkins
  • Patent number: 9543731
    Abstract: An embodiment of the invention relates to a method for generating short optical pulses comprising the steps of: operating a single section semiconductor laser in a nonlinear regime to emit chirped optical pulses at an output facet of the laser cavity, and compressing the chirped optical pulses outside the laser cavity using a dispersive element in order to generate the short optical pulses.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: January 10, 2017
    Assignee: Technische Universität Berlin
    Inventors: Ricardo Rosales, Dieter Bimberg
  • Patent number: 9525033
    Abstract: A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: December 20, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: David F. Brown, Miroslav Micovic
  • Patent number: 9520696
    Abstract: A set of VCSEL fabrication methods has been invented which enhance the performance and long time reliability of VCSEL devices and arrays of devices. Wafer bow caused by growing a large number of epitaxial layers required to fabricate VCSEL device generates strain and results in bowing/warping of the device wafer. The stress so generated is eliminated by applying a stress compensation layer on the substrate to a surface opposite to the epitaxial layer surface. New oxidation equipment designs and process parameters are described which produce more precision apertures and reduce stress in the VCSEL device. An ultrathin fabrication procedure is described which enables high power VCSELs to be made for high power operation at many different wavelengths. A low temperature electrical contacting process improves VCSEL long term reliability.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: December 13, 2016
    Assignee: PRINCETON OPTRONICS INC.
    Inventors: Qing Wang, Jean-Francois Seurin, Chuni L Ghosh, Laurence S Watkins
  • Patent number: 9488897
    Abstract: The invention relates to a single-photon generator and a single-photon generating method, which theoretically makes it possible to precisely generate a single photon in real time. A three-level lambda system is formed of a coupled quantum dots group, which is a set of a number of coupled quantum dots where a couple of quantum dots having different ground quantum levels are coupled. The entirety is made in an exciton ground state through illumination with first excitation light. Then, the number of photons in the Raman scattering light through illumination with second excitation light is detected, and a single excited Dicke state is achieved. After that, a single photon is generated accompanying the transition from the single excited Dicke state to the exciton ground state through illumination with third excitation light.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: November 8, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Toshio Oshima
  • Patent number: 9484715
    Abstract: A quantum cascade laser is configured with a semiconductor substrate and first and second active layers provided in series on the substrate. A unit laminate structure of the first active layer has a subband level structure having an emission upper level and an emission lower level, and is configured so as to be able to generate light of a first frequency ?1, a unit laminate structure of the second active layer has a subband level structure having a first emission upper level, a second emission upper level, and a plurality of emission lower levels, and is configured so as to be able to generate light of a second frequency ?2, and light of a difference frequency ? is generated by difference frequency generation from the light of the first frequency ?1 and the light of the second frequency ?2.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: November 1, 2016
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Kazuue Fujita, Tadataka Edamura, Naota Akikusa
  • Patent number: 9478943
    Abstract: A single pulse semiconductor laser operating in the gain-switching regime comprises a plane asymmetric waveguide and an active layer in the waveguide, the ratio of a thickness of the active layer to an optical confinement factor of the laser being extremely large, larger than about 5 ?m, for example.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: October 25, 2016
    Assignee: Oulun Yliopisto
    Inventors: Boris Ryvkin, Juha Kostamovaara
  • Patent number: 9466947
    Abstract: A semiconductor laser diode (LD) with a shortened cavity length is disclosed. The LD provides a rectangular substrate and, on the substrate, a cavity structure including a mesa with facets forming the laser cavity. The facets of the mesa are stood back from the side of the substrate. Pads to provide electrical signals are arranged in both sides of the mesa close to the sides of the substrate.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: October 11, 2016
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Nobumasa Okada
  • Patent number: 9450053
    Abstract: Photonic integrated circuits (PICs) are based on quantum cascade (QC) structures. In embodiment methods and corresponding devices, a QC layer in a wave confinement region of an integrated multi-layer semiconductor structure capable of producing optical gain is depleted of free charge carriers to create a low-loss optical wave confinement region in a portion of the structure. Ion implantation may be used to create energetically deep trap levels to trap free charge carriers. Other embodiments include modifying a region of a passive, depleted QC structure to produce an active region capable of optical gain. Gain or loss may also be modified by partially depleting or enhancing free charge carrier density. QC lasers and amplifiers may be integrated monolithically with each other or with passive waveguides and other passive devices in a self-aligned manner. Embodiments overcome challenges of high cost, complex fabrication, and coupling loss involved with material re-growth methods.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: September 20, 2016
    Assignees: Massachusetts Institute of Technology, Pendar Technologies, LLC
    Inventors: Anish K. Goyal, Laurent Diehl, Christian Pfluegl, Christine A. Wang, Mark Francis Witinski
  • Patent number: 9444011
    Abstract: In the nitride semiconductor device of the present invention, an active layer 12 is sandwiched between a p-type nitride semiconductor layer 11 and an n-type nitride semiconductor layer 13. The active layer 12 has, at least, a barrier layer 2a having an n-type impurity; a well layer 1a made of a nitride semiconductor that includes In; and a barrier layer 2c that has a p-type impurity, or that has been grown without being doped. An appropriate injection of carriers into the active layer 12 becomes possible by arranging the barrier layer 2c nearest to the p-type layer side.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: September 13, 2016
    Assignee: NICHIA CORPORATION
    Inventor: Tokuya Kozaki
  • Patent number: 9438011
    Abstract: Single-mode, distributed feedback interband cascade lasers (ICLs) using distributed-feedback gratings (e.g., lateral Bragg gratings) and methods of fabricating such ICLs are provided. The ICLs incorporate distributed-feedback gratings that are formed above the laser active region and adjacent the ridge waveguide (RWG) of the ICL. The ICLs may incorporate a double-ridge system comprising an optical confinement structure (e.g., a RWG) disposed above the laser active region that comprises the first ridge of the double ridge system, a DFB grating (e.g., lateral Bragg grating) disposed above the laser active region and adjacent the optical confinement structure, and an electric confinement structure that passes at least partially through the laser active region and that defines the boundary of the second ridge comprises and the termination of the DFB grating.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: September 6, 2016
    Assignee: California Institute of Technology
    Inventors: Clifford F. Frez, Carl E. Borgentun, Ryan M. Briggs, Mahmood Bagheri, Siamak Forouhar
  • Patent number: 9429693
    Abstract: A rib waveguide type high-order mode filter includes a plate-like slab region 1; a projection portion 2 formed in a stripe along a waveguiding direction of light on the slab region 1; and a mesa region 4 having a bottom surface positioned at the same level as that of the bottom surface of the slab region 1 and a top surface positioned at a higher level than that of the top surface of the slab region 1, on at least one side of the slab region 1, wherein the projection portion 2, the slab region 1, and the mesa region 4 are made of the same material; and the mesa region 4 includes a doped area 4a in which an optical-absorption function is added by impurity doping into the material.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: August 30, 2016
    Assignee: NEC CORPORATION
    Inventor: Shigeki Takahashi
  • Patent number: 9417389
    Abstract: A method and system for coupling optical signals into silicon optoelectronic chips are disclosed and may include coupling one or more optical signals into a back surface of a silicon photonic chip through a light path in a region where silicon is removed from said silicon photonic chip, wherein photonic devices may be integrated in layers on a front surface of the silicon photonic chip. Optical couplers, such as grating couplers, may receive the optical signals in the front surface. The optical signals may be coupled into the back surface of the chips via optical fibers and/or optical source assemblies. The region where silicon may be removed from said silicon photonic chip may comprise silicon dioxide. The chip may be bonded to a second chip. Optical signals may be reflected back to the optical couplers via metal reflectors, which may be integrated in dielectric layers on the chips.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: August 16, 2016
    Assignee: Luxtera, Inc.
    Inventors: Thierry Pinguet, Attila Mekis, Steffen Gloeckner
  • Patent number: 9412911
    Abstract: Light emitting semiconductor junctions are disclosed. An exemplary light emitting junction has a first electrical contact coupled to a first side of the junction. The exemplary junction also has a second electrical contact coupled to a second side of the junction. The exemplary junction also has a region of set straining material that exerts a strain on the junction and alters both: (i) an optical polarization, and (ii) an emission wavelength of the junction. The region of set straining material is not on a current path between said first electrical contact and said second electrical contact. The region of set straining material covers a third side and a fourth side of the light emitting junction along a cross section of the light emitting junction. The light emitting semiconductor junction device comprises a three-five alloy.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: August 9, 2016
    Assignee: The Silanna Group Pty Ltd
    Inventor: Petar Atanackovic
  • Patent number: 9406835
    Abstract: Embodiments of the invention include an n-type region, a p-type region, and a light emitting layer disposed between the n-type region and the p-type region. The light emitting layer is a III-V material comprising nitrogen and phosphorus. The device also includes a graded region disposed between the light emitting layer and one of the p-type region and the n-type region. The composition of materials in the graded region is graded.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: August 2, 2016
    Assignee: Koninklijke Philips N.V.
    Inventor: Stephane Turcotte
  • Patent number: 9401447
    Abstract: The present invention pertains to a semiconductor light-receiving element and a method for manufacturing the same, enabling operation in a wide wavelength bandwidth and achieving fast response and high response efficiency. A PIN type photodiode made by sequentially layering on top of the substrate a Si layer of a first conductivity type, a non-doped Ge layer and a Ge layer of a second conductivity type that is the opposite type of the first conductivity type and a Ge current-blocking mechanism is provided in at least part of the periphery of the PIN type photodiode.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: July 26, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Shigekazu Okumura
  • Patent number: 9396941
    Abstract: Disclosed herein is a method of: depositing a patterned mask layer on an N-polar GaN epitaxial layer of a sapphire, silicon, or silicon carbide substrate; depositing an AlN inversion layer on the open areas; removing any remaining mask; and depositing a III-N epitaxial layer to simultaneously produce N-polar material and III-polar material. Also disclosed herein is: depositing an AlN inversion layer on an N-polar bulk III-N substrate and depositing a III-N epitaxial layer to produce III-polar material. Also disclosed herein is: depositing an inversion layer on a III-polar bulk III-N substrate and depositing a III-N epitaxial layer to produce N-polar material. Also disclosed herein is a composition having: a bulk III-N substrate; an inversion layer on portions of the substrate; and a III-N epitaxial layer on the inversion layer. The III-N epitaxial layer is of the opposite polarity of the surface of the substrate.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: July 19, 2016
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Jennifer K. Hite, Francis J. Kub, Charles R. Eddy, Jr., Nelson Garces
  • Patent number: 9397253
    Abstract: Disclosed are a light emitting diode having an n-doped ohm contact buffer layer and a manufacturing method therefor. In the present invention, a highly n-doped ohm contact buffer layer with an electronic concentration up to 1×1018 cm3 is formed on the n side of a light emitting epitaxy layer; when a growth substrate is removed, the n-type ohm contact buffer layer on the surface is exposed, which is a no-nitride polarity-face n-type GaN base material with a lower energy gap; an n-type ohm contact electrode is prepared on the n-type ohm contact buffer layer and follows the Ti/Al ohm contact electrode, which can overcome the problem of the existing vertical gallium nitride-based vertical light emitting diode that the voltage of the thin film GaN base light emitting device is unreliable because the ohm contact electrode on the nitride-face GaN base semiconductor layer is easy to crack due to temperature.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: July 19, 2016
    Inventors: Meng-Hsin Yeh, Jyh-Chiarng Wu, Shaohua Huang, Chi-Lun Chou
  • Patent number: 9385507
    Abstract: A semiconductor laser light source comprising an edge-emitting semiconductor body (10) is provided. The semiconductor body (10) contains a semiconductor layer stack (110) having an n-type layer (111), an active layer (112) and a p-type layer (113) which is formed for generating electromagnetic radiation which comprises a coherent portion (21). The semiconductor laser light source is formed for decoupling the coherent portion (21) of the electromagnetic radiation from a decoupling surface (101) of the semiconductor body (10) which is inclined with respect to the active layer (112). The semiconductor body (10) comprises a further external surface (102A, 102B, 102C) which is inclined with respect to the decoupling surface (101) and has at least one light-diffusing sub-region (12, 12A, 12B, 12C, 120A, 120B) which is provided in order to direct a portion of the electromagnetic radiation generated by the semiconductor layer stack (110) in the direction towards the further external surface (102A, 102B, 102C).
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: July 5, 2016
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Christoph Eichler, Andreas Breidenassel, Alfred Lell
  • Patent number: 9379521
    Abstract: A group III nitride semiconductor laser device comprises a laser structure including a support base of the group III nitride and first and second end facets for a laser cavity, and the first and second end facets intersect with an m-n plane defined by the m-axis of the group III nitride and an axis normal to a semipolar primary surface of the support base. A +c axis vector for a c-axis of the group III nitride forms an angle ALPHA in a range of 71 to 79 degrees with the normal axis. The +c axis vector is inclined at an angle ?1 of 10 to 25 degrees with one normal vector defined at one edge of the first end facet, and is inclined at an angle ?1 of zero to 5 degrees with another normal vector defined at the other edge of the first end facet.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: June 28, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Shimpei Takagi
  • Patent number: 9373937
    Abstract: A semiconductor laser includes a layer structure with superimposed layers with at least the following layer structure: an n-doped outer layer, a third wave-guiding layer, an active zone in which light-generating structures are arranged, a second wave-guiding layer, a blocking layer, a first wave-guiding layer, a p-doped outer layer. The first, second and third wave-guiding layers have at least AlxInyGa (1?x?y) N. The blocking layer has an Al content which is at least 2% greater than the Al content of the adjacent first wave-guiding layer. The Al content of the blocking layer increases from the first wave-guiding layer towards the second wave-guiding layer. The layer structure has a double-sided gradation. The double-side gradation is arranged at the height of the blocking layer such that at least one part of the blocking layer or the entire blocking layer is of greater width than the first wave-guiding layer.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: June 21, 2016
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Uwe Strauβ, Teresa Wurm, Adrian Stefan Avramescu, Georg Brüderl, Christoph Eichler, Sven Gerhard
  • Patent number: RE46059
    Abstract: A method of manufacturing a laser diode array capable of inhibiting electric cross talk is provided. The method of manufacturing a laser diode array includes a processing step of forming a peel layer containing an oxidizable material and a vertical resonator structure over a first substrate sequentially from the first substrate side by crystal growth, and then selectively etching the peel layer and the vertical resonator structure to the first substrate, thereby processing into a columnar shape, a peeling step of oxidizing the peel layer from a side face, and then peeling the vertical resonator structure of columnar shape from the first substrate, and a rearrangement step of jointing a plurality of vertical resonator structures of columnar shape obtained by the peeling step to a surface of a metal layer of a second substrate formed with the metal layer on the surface.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: July 5, 2016
    Assignee: Sony Corporation
    Inventors: Osamu Maeda, Masaki Shiozaki, Takahiro Arakida