Abstract: A receiver circuit receives an incoming signal and accordingly provides an internal signal, and includes an equalizer, a slicer module and a counter module. The equalizer provides a signal level according to the incoming signal, the slicer module compares if the internal signal exceeds a level range; according to comparison result, the counter module provides a signal quality indication capable of indicating whether a bit error rate of signal receiving is greater than a predetermined reference bit error rate. One of an upper bound and a lower bound of the level range can equal the signal level, a distance between the upper bound and the lower bound is set according to a reference signal-to-noise ratio which associates with the reference bit error rate.

Abstract: An unrolled decision feedback equalizer (DFE) as disclosed herein has a reduced number of compensation factors while keeping a suitable performance level for a given application. The KN possible DFE correction levels are reduced or compressed into fewer levels (R), merging together the levels that are the closest together where K represents the number of possible symbols in each baud, or the number of bits encoded into each baud, and N represents the DFE depth in number of bauds. A mapping function is then provided to convert the KN combinations of previous history bits into R sampler selections.

Abstract: One or more embodiments describe a decision feedback equalizer utilizing symbol error rate biased adaptation function for highly spectrally efficient communications. A method may be performed in a decision feedback equalizer (DFE). The method may include determining values of tap coefficients used by the DFE based. The tap coefficients may be determined based on an error signal that is based on an estimated inter-symbol-correlated (ISC) signal. The tap coefficients may be determined based on a set of error vector(s), where each error vector in the set represents a difference between estimated symbols generated in the receiver and expected symbols. Determining the values of the tap coefficients may include using a symbol error rate function that estimates the actual symbol error rate in the receiver, wherein the symbol error rate function receives as input the set of error vector(s).

Abstract: An equalization adaptation circuit comprises an equalizer, a transition determination circuit, a phase error circuit, a sequence recovery circuit, a phase error accumulator circuit, a transition accumulator circuit, and a controller circuit. The equalizer has adjustable parameters. The transition determination circuit determines observed transitions in an equalized signal output from the equalizer. A phase error circuit determines phase errors of the observed transitions. A sequence recovery circuit generates recovered digital data sequences. A phase error accumulator circuit accumulates the phase errors in respective association with pre-defined patterns matching the recovered digital data sequences containing observed transitions corresponding to the phase errors. A transition accumulator circuit accumulates a number of the observed transitions. A controller circuit controls the adjustable parameters of the equalizer based upon the accumulated phase errors and number of observed transitions.

Abstract: A decision feedback equalizer, transceiver, and method are provided, the equalizer having at least one comparator, the at least one comparator comprising a first stage, comprising a main branch having two track switches with a resistive load, an offset cancellation branch, a plurality of tap branches with transistor sizes smaller than the main branch, in which previous decisions of the equalizer are mixed with the tap weights using current-mode switching, and a cross coupled latch branch; and a second stage, comprising a comparator module for making decisions based on the outputs of the first stage and a clock input, and a plurality of flip-flops for storing the output of the comparator module.

Abstract: A method and a circuit for controlling an equalizer and an equalizing system are disclosed. The method includes providing a first level from a set of levels as a peaking level of the equalizer; equalizing a transmission signal by using the equalizer with the first level to obtain a first signal; providing a second level from the set of levels as the peaking level of the equalizer; equalizing the transmission signal by using the equalizer with the second level to obtain a second signal; determining a first frequency of the first signal; determining a second frequency of the second signal; comparing the first frequency and second frequency to obtain a comparing result; and determining the peaking level of the equalizer for following equalization of the transmission signal in accordance with the comparing result.

Abstract: Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller automatically adjusts the compensation provided by the equalizer based on comparisons of one or more portions of the compensated video signal to one or more reference voltage levels. One or more values indicative of one or more levels of compensation provided by the equalizer are stored in memory and/or registers for each time, of a plurality of times. A monitor monitors for changes in the cable and/or the video signal transmitted over the cable based on the stored values.

Abstract: A configurable analog equalizer is set to a first high-pass frequency response that is intentionally too moderate to compensate for a low-pass frequency response of a physical link coupling a transmitter and a receiver. A Feed Forward Equalizer (FFE) is activated at the receiver; the FFE includes a set of coefficients having a minimum configuration of a cursor coefficient and a first pre-cursor coefficient. A Decision Feedback Equalizer (DFE) is activated at the receiver; the DFE includes a set of coefficients having a minimum configuration of a first post-cursor coefficient. The configurable analog equalizer is then set to a high-pass frequency response that is more intense than the first high-pass frequency response, until the first post-cursor coefficient of the DFE substantially equals an absolute value of a quotient obtained by dividing the first pre-cursor coefficient of the FFE by the cursor coefficient of the FFE.

Abstract: An equalizer is disclosed, and associated operational method. The equalizer has a configuration that balances performance and complexity by obtaining samples that are strongly correlated with future and past transmitted bits, and are weakly correlated with future and past bit transitions, and is useful for timing recovery circuits. Samples are only obtained or collected at time intervals more than one sample period away from the reference sample. Samples are shifted by a delay value less than the sample period, and are obtained at a sample period of one unit interval. A means to adjust the sampling point delay is also disclosed. In an implementation, samples that are within the sample period away from the reference sample are obtained and used for implementing a timing shift, not for equalization of the timing recovery signal. Embodiments are also disclosed for optimizing performance for data recovery.

Abstract: An apparatus comprising an inter symbol interference (ISI) cancellation circuit and a detector circuit. The inter symbol interference (ISI) cancellation circuit may be configured to minimize ISI at data sampling and crossing sampling points in a symbol interval of an input signal. The detector circuit may be configured to generate data samples and crossing samples at the data sampling and crossing sampling points in the symbol interval of the input signal.

Abstract: A tap coefficient control circuit and a method for controlling a tap coefficient for a decision feedback equalizer are disclosed. The method includes adjusting a correction voltage applied to the tap coefficient based on a first tap quantization and detecting a decision feedback equalizer tap convergence. After the decision feedback equalizer tap convergence is detected, the method adjusts the correction voltage applied to the tap coefficient based on a second tap quantization, wherein the second tap quantization is different from the first tap quantization.

Abstract: A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.

Abstract: A decision feedback equalizer includes: L equalization calculation circuits to perform an equalization calculation of a first sample of input data for each of M combinations of data decision values of a second sample sampled from the input data before sampling the first sample; a first logic circuit to generate first M logical values by selecting and arranging calculation values of M calculation values calculated by at least one equalization calculation circuit among the L equalization calculation circuits based on a data decision value for a third sample sampled before sampling the first data; and a selection circuit to select one of the first M logical values based on a data decision value for a fourth sample sampled before sampling the third sample, and to output the selected logical value as a data decision value of the first sample.

Abstract: One embodiment relates to an equalizer circuit for a data link. The equalizer circuit including a continuous-time linear equalizer, a first circuit loop, and a second circuit loop. The continuous-time linear equalizer receives a received signal and outputs an equalized signal. The first circuit loop determines a first average signal amplitude. The first average signal amplitude may be an average signal amplitude of the equalized signal. The second circuit loop a second average signal amplitude. The second average signal amplitude may be an average signal amplitude of a high-frequency portion of the equalized signal. Other embodiments and features are also disclosed.

Abstract: Provided is a receiver for processing VSB signal. The receiver includes a first equalizer/decoder unit and a second equalizer/decoder unit. The first equalizer/decoder unit performs a first equalizing operation, first TCM decoding and first RS decoding on a received symbol to output a first dibit. The second equalizer/decoder unit performs a second equalizing operation, second TCM decoding and second RS decoding on the received symbol to output a transport stream. The first dibit is provided as a priori information for a soft-decision operation of the second TCM decoding.

Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

Abstract: Computationally efficient methods and related systems, for use in a test and measurement instrument, such as an oscilloscope, optimize the performance of DFEs used in a high-speed serial data link by identifying optimal DFE tap values for peak-to-peak based criteria. The optimized DFEs comply with the behavior of a model DFE set forth in the PCIE 3.0 specification.

Abstract: Methods of efficient calculation of initial equaliser coefficients are described. In a first stage, a channel matched filter is generated based on an estimate of CIR and then used to filter the CIR estimate. In a second stage, initial FFE coefficients are calculated from a portion of the match filtered CIR and then these initial FFE coefficients and the estimate of CIR may be used to generate initial DFE coefficients. In various embodiments, a window is applied to the CIR estimate before the matched filter is generated. In various embodiments, the second stage is iterated to minimise the pre-echoes following the FFE.

Abstract: Efficient methods and apparatus for tracking decision-feedback equaliser (DFE) coefficients are described. In an embodiment, updated coefficients for a feed-forward equaliser (FFE) are generated using conventional methods and then these are used, along with an averaged updated value of channel impulse response (CIR) estimate to generate updated DFE coefficients. In an embodiment, the updated DFE coefficients are generated by multiplying the updated CIR estimate (in the frequency domain) and the updated FFE coefficients (also in the frequency domain). The resultant updated DFE coefficients in the frequency domain may then be converted into the time domain before outputting to the DFE.

Abstract: The present invention relates to a method for generating impairment covariances for equalization in a receiver of a wireless communication system, as well as an covariance estimator, a receiver and a wireless communication system associated therewith, where the receiver is equipped with multiple antennas, and an impairment covariance matrix is used to calculate equalization weighting vector for signals transmitted by a transmitter, the method comprising the steps of: calculating a raw impairment covariance estimate between a first antenna and a second antenna of the multiple antennas on each of subcarriers allocated to the transmitter in frequency domain, transforming the raw impairment covariance estimates into time domain, masking the transformed impairment covariance estimates by a triangle window with a width defined by a maximum delay spread, determining a threshold based on the transformed impairment covariance estimates for the subcarriers and thresholding the masked impairment covariance estimates wit

Abstract: A method and system of adaptation of a linear equalizer using a virtual decision feedback equalizer (VDFE) are disclosed. In one embodiment, a method of adjusting a setting of a linear equalizer includes determining a change to a decision feedback equalizer (DFE) tap weight value of a predefined metric according to a data signal and an error signal (e.g., the change may be generated according to an average of a specified plurality of data signals and the error signal); using the change in the DFE tap weight value to algorithmically generate a modification in a linear equalizer setting; and adjusting the linear equalizer setting. The linear equalizer is located in a feed-forward path and/or a feedback path of data transmission. The linear equalizer may be located in a transmitter and/or a receiver. The linear equalizer may be a continuous time linear equalizer and/or a Finite Impulse Response (FIR) linear equalizer.

Abstract: An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.

Abstract: Equalization techniques are provided for high-speed data communications and, more specifically, DFE (decision feedback equalizer) circuits and methods are provided which implement a high-order continuous time filter in a DFE feedback path to emulate structured elements of a channel response.

Abstract: A Method and Apparatus for Channel Equalization in High Speed S-RIO based Communication Systems have been disclosed. By adjusting equalizer coefficients based on 8B10B error counts and an error threshold, a receiver may be dynamically adjusted. By adjusting transmitter pre-emphasis based on 8B10B error counts and an error threshold, a transmitter may be dynamically adjusted. Both the transmitter and receiver may be adjusted dynamically based on 8B10B error counts and different error thresholds.

Abstract: An apparatus comprising an equalizer circuit, a converter circuit and an adaptation circuit. The equalizer circuit may be configured to generate an intermediate signal in response to an input signal and a gradient value. The converter circuit may be configured to generate a digital signal comprising a plurality of symbol values, including a main cursor symbol value, in response to the intermediate signal. The adaptation circuit may be configured to generate the gradient value in response to a plurality of the symbol values before the main cursor symbol value, a plurality of symbol values after the main cursor symbol value, and an error value.

Abstract: Techniques are disclosed for turbo decoding orthogonal frequency division multiplexing OFDM symbols. Techniques for combined turbo decoding and equalization are disclosed. The disclosed techniques can be implemented in receivers that receive wired or wireless OFDM signals and produce data and control bits by decoding the received signals.

Abstract: Systems and methods are provided for adjusting gain of a receiver. Adaptation circuitry is operable to identify, based on a matrix representation of a receiver's output generated from horizontal and vertical sweeps of the receiver's output, an eye opening of the receiver's output. The adaptation circuitry is also operable to determine whether a size of the eye opening needs to be changed. When it is determined that the size of the eye opening needs to be changed, the adaptation circuitry is operable to generate a digital signal to change a gain setting of the receiver. When the signal at the receiver's output is under-equalized, the AC gain of the receiver is increased. When the signal at the receiver's output is over-equalized, the AC gain of the receiver is decreased.

Abstract: An exemplary receiver equalizer includes a first decision feedback equalizer (DFE) sampler coupled to a summer, the first DFE to latch an equalized output of the summer. The first branch includes a second DFE sampler coupled to the first DFE sampler, the second DFE to latch an output of the first DFE sampler. The first branch includes a third DFE sampler coupled to the second DFE sampler, the third DFE to latch an output of the second DFE sampler. The summer coupled to the first, second, and third DFE samplers of the first branch, the summer to integrate the output of said DFE samplers, the received signal, and equalized outputs from one or more other branches, wherein the integrating occurs over a plurality of unit intervals (UIs).

Abstract: A receiver and a method for equalizing signals, the method includes: receiving input signals; sampling the input signals to provide oversampled samples; processing the oversampled samples to provide symbol spaced samples and to provide fractionally spaced samples that represent the oversampled samples; calculating taps of a fractionally spaced equalizer based on the symbol spaced samples; feeding the taps to the fractionally spaced equalizer; and filtering the fractionally spaced samples by the fractionally spaced equalizer to provide equalized samples.

Abstract: A system generates a set of candidate signals based on a received signal, whereby each candidate signal represents an adjustment of the signal for a different amount of potential noise. The system selects one of the candidate signals based on a selected subset of previous samples and the values of the selected subset of samples. The subset of previous samples is selected based on a predicted noise pattern.

Abstract: Described embodiments apply equalization to an input signal to a receiver such as a serial-deserializer. The receiver has an analog-to-digital converter (ADC), an M-way parallelizer, N serial buffers, N prefix buffers, and N decision feedback equalizers (DFEs), where M and N are greater than one. The ADC digitizes the input signal to form digitized symbols. The parallelizer assembles the digitized symbols into parallel sets of M digitized symbols. Each serial buffer has slots of M locations per slot and stores one set of M digitized symbols in one of the slots. The DFEs are responsive to common tap weight coefficients and produce parallel sets of M recovered data bits. Each DFE is first trained using sets of past digitized symbols loaded into a corresponding one of the prefix buffers and then processes digitized symbols stored in a corresponding one of the serial buffers.

Abstract: One embodiment relates to a receiver with both decision feedback equalization and on-die instrumentation. A clock data recovery loop obtains a recovered clock signal from an input signal, and a first sampler, which is triggered by the recovered clock signal, generates a recovered data signal from the input signal. A phase interpolator receives the recovered clock signal and generates a phase-interpolated clock signal. A second sampler is triggered by the recovered clock signal in a decision feedback equalization mode and by the phase-interpolated clock signal in an on-die instrumentation mode. Other embodiments and features are also disclosed.

Abstract: Described embodiments adjust configurable parameters of at least one filter of a communication system. The method includes conditioning, by an analog front end (AFE) of a receiver in the communication system, an input signal applied to the receiver. Sampled values of the conditioned input signal are generated and digitized. An error detection module generates an error signal based on digitized values of the input signal and a target value. A decision feedback equalizer generates an adjustment signal based on the digitized values of the input signal and values of the error signal. A summer subtracts the adjustment signal from the conditioned input signal, generating an adjusted input signal. An adaptation module determines a conditional adaptation signal based on a comparison of sampled values of the adjusted input signal and values of the error signal. The adaptation module adjusts a transfer function of at least one filter based on the conditional adaptation signal.

Abstract: An apparatus includes an error sample generating circuit and an adaptation circuit. The error sample generating circuit is generally configured to generate error samples at a plurality of phases. The adaptation circuit may be configured to adjust one or more equalizer settings based upon a data sample and the error samples.

Abstract: In an embodiment of the present invention, a feedback technique is used to track a reference signal with a DFE summing node common mode voltage. For example, in an embodiment implemented in CML, the feedback signal shifts both differential signals (e.g., the summing node common voltage and the reference voltage) by the same amount. In such an embodiment, the feedback technique preferably changes the reference common mode but not its differential mode.

Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for clock recovery.

Abstract: Embodiments of the present invention disclose a co-channel dual polarized microwave device and a method. Frame synchronization is performed on a first receive signal processed by cross polarization interference cancellation and phase noise immunization is performed on the first receive signal processed by frame synchronization. Frame synchronization is performed on a second receive signal not processed by cross polarization interference cancellation and phase noise immunization is performed on the second receive signal processed by frame synchronization. The first receive signal processed by phase noise immunization and the second receive signal processed by phase noise immunization are selectively received according to a frame synchronization state signal and a signal quality signal. Delay alignment is performed on a selectively received signal according to the frame synchronization state signal to implement lossless switching in a selective receiving process.

Abstract: Equalization techniques are provided for high-speed data communications and, more specifically, DFE (decision feedback equalizer) circuits and methods are provided which implement a high-order continuous time filter in a DFE feedback path to emulate structured elements of a channel response.

Abstract: Methods and systems adaptively equalizing an analog information signal, the method including sampling the analog information signal to provide analog samples including post-transition samples and steady-state samples, and equalizing the analog samples to produce equalized analog samples. The equalizing includes determining a difference between an average post-transition amplitude associated with at least one of the post-transition samples and an average steady-state amplitude associated with at least one of the steady-state samples, and adjusting an equalization coefficient to adjust the difference between the average post-transition amplitude and the average steady-state amplitude.

Abstract: An OFDM receiver for processing an OFDM received signal to perform OFDM reception in presence of Doppler effects is provided. The receiver has at least two parallel processing chains, each processing chain has a time domain windowing for processing an OFDM block. The processing consisting of the multiplication, element by element of the OFDM block, by a set of predetermined coefficients. The receiver also has a DFT block (such as FFT) for demodulating said windowed OFDM symbol into the frequency domain equivalent wherein the windowings of the at least two parallel processing chains have complementary profiles so as to avoid any loss of information throughout the OFDM sample. The invention also provides a process to be used in an OFDM receiver.

Abstract: Linear distortion and interference estimation using decision feedback equalizer coefficients. Processing of different respective groups of equalizer coefficients may be made to determine the residual frequency response of an equalizer and/or device in which the equalizer is implemented. Such an equalizer may be implemented within any of a number of respective communication devices including those operative within satellite, wireless, wired, fiber-optic, and/or mobile communication systems. A first group of equalizer coefficients corresponds to certain filtering characteristics of the equalizer and/or device in which the equalizer is implemented. The equalizer is implemented to process a signal to generate a second group of equalizer coefficients.

Abstract: An apparatus comprising an equalizer circuit, a converter circuit and an adaptation circuit. The equalizer circuit may be configured to generate an intermediate signal in response to an input signal and a gradient value. The converter circuit may be configured to generate a digital signal comprising a plurality of symbol values, including a main cursor symbol value, in response to the intermediate signal. The adaptation circuit may be configured to generate the gradient value in response to a plurality of the symbol values before the main cursor symbol value, a plurality of symbol values after the main cursor symbol value, and an error value.

Abstract: A data equalizing circuit includes an equalizer configured to output data according to a control code; and a detection unit configured to divide the data into N number of calculation periods, count data transition frequencies for the N calculation periods, calculate dispersion values of the data transition frequencies for the N calculation periods, and output the control code corresponding to a largest dispersion value, in response to a counting interruption signal and a counting completion signal, wherein n is equal to or greater than 2, N is greater than n, and the data is divided to n number of unit intervals (UI), and wherein a phase shift of each of the calculation periods with respect to its corresponding UI is different from a phase shift of any of the other calculation periods with respect to its corresponding UI.

Abstract: An equalizer and a related equalizing method for equalizing signal reflection caused by a stub at a transmitting end are provided. The equalizer includes a summing device and a delay device. The summing device is utilized for adding a feedback delay signal to the input signal to generate the equalized signal. The delay device is coupled to the summing device, and utilized for delaying the equalized signal to generate the feedback delay signal. Wherein the delay device has a variable delay time and the variable delay time is a non-integer multiple of a bit time of the input signal.

Abstract: A device implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit that sets the tap weights that are used for adjustment of a received data signal. The tap weight adapter circuit sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

Abstract: Apparatuses, methods, and other embodiments associated with adaptively determining equalizer setting for 10GBASE-KR transmitter are described. According to one embodiment, an apparatus for tuning an equalizer configured to undo the effects of a channel connecting a transmitter communicating to a receiver via a backplane includes a tuning logic configured to adaptively determine equalizer settings for the equalizer. The tuning logic includes a symmetric search logic configured to determine a desired boost setting for the equalizer, and an asymmetric search logic configured to determine a desired phase response for the equalizer.

Abstract: A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.

Abstract: A decision feedback equalizer (DFE) for equalizing PAM-N signals comprises a coefficient setting unit for setting a first group of most significant feedback coefficients of the DFE to a predefined value selected from a group of predefined values; a coefficients computation unit coupled to the coefficient setting unit for computing values of feedback coefficients of a second group of feedback coefficients other than the first group of most significant feedback coefficients; a feedback (FB) unit for mitigating, using a complete group of feedback coefficients, effects of interference from data symbols that are adjacent in time to an input data symbol, wherein most significant feedback coefficients of the first group are set to an optimal value computed during an initialization of the DFE and feedback coefficients of the second group are computed by the coefficients computation unit.

Abstract: A method for removing distortions in a transmitted signal transmitted by a high power amplifier in a satellite communications system. The method characterizes the high power amplifier to define a series of Volterra coefficients and uses those coefficients in an equalizer in a receiver in the communications system to remove the distortions. The equalizer is a non-linear soft interference cancellation and minimum mean square error equalizer that employs three processing operations including parallel soft interference cancellation, minimum mean square error filtering and a priori log-likelihood ratio calculations.

Abstract: A circuit includes a first wireless interface circuit that communicates packetized data to a first external device in accordance with a first wireless communication protocol. A second wireless interface circuit communicates packetized data to a second external device in accordance with a second wireless communication protocol. A plurality of signal lines communicate at least four lines of cooperation data between the first wireless interface circuit and the second wireless interface circuit, wherein the cooperation data relates to cooperate transceiving in a common frequency spectrum.