Abstract: An apparatus including a frame buffer memory; a set of frame synchronizers coupled to the frame buffer memory; and, a set of receivers coupled to the buffer memory and a corresponding frame synchronizer in the set of frame synchronizers. Each receiver is configured to receive a data stream having a first clock rate, and detect changes in the data stream using a second clock rate.

Abstract: The semiconductor integrated circuit comprises a plurality of delay elements that delay in a stepped manner a master clock signal generated internally to obtain a plurality of clock signals with differing phases, and a multiplexer which sequentially selects any one of the clock signals with differing phases at a time and outputs the selected signal to a plurality of receiver integrated circuits through a common clock line.

Abstract: A system and method for providing a clock signal and data signal delay match to improve setup and hold times for integrated circuits is disclosed. In a simplified embodiment, the system comprises a clock receiver capable of removing noise from a received clock signal. A clock buffer is connected to the clock receiver and is capable of driving the received clock signal to a register. A data receiver is located within the system which is capable of removing noise from received data. In addition at least one miniature clock buffer is located within the system, wherein the at least one miniaturized clock buffer is a scaled version of the clock buffer having a scaling factor of K, the scaling factor representing a number of miniature clock buffers utilized to minimize negative variations experienced by the clock buffer.

Abstract: A method and related apparatus for high speed digital data conmunications from multiple distributed modems to a single central modem or a common transmission medium. In one embodiment, multiple downhole modems, with each modem associated with a geophone, transmit data to a surface modem over a single transmission medium. In a second embodiment, multiple transmission mediums are used and a plurality of downhole modems associated with geophones communicate to the surface modem over the downhole modem's respective transmission medium.

Abstract: An apparatus and method for extending the service area in a mobile communication system is provided, in which the service area is defined with a normal mode or an extension mode based on a distance between the base station and the mobile station and, in case of the extension mode, a transmission clock used by the mobile station for transmitting signals is changed, thus extending the service area. The access is attempted in the normal mode, and the transmission clock for transmitting the mobile signal is advanced the initial delay in the extension mode when the access fails. The access is reattempted with repeating the control of the transmission clock until the number of times of the access attempt reaches a predetermined number of times. When the number of times of the access currently attempted is greater than the predetermined number of times, the extension mode is converted to the normal mode, returning to the initial state.

Abstract: A method and apparatus is provided that computes an optimal estimate of known clock frequency error between the transmitter and receiver using a known pilot signal and the statistics of the noise process. The estimate is computed such that the residual clock error is below the least count (the smallest frequency correction that can be imparted) of the VCXO that controls the receiver sample clock. A tracking technique based on a measure of drift in taps of frequency domain equalizers of different sub-carriers is disclosed. This tracking ensures that the residual mean square error is within a predefined bound. Finally, the least count effects in digitally controlled oscillators (DAC controlled VCXOs and Numerically Controlled Oscillators (NCXO)) are addressed by a dithering mechanism. The dithering mechanism involves imparting positive and negative clock corrections for different lengths of time in such a manner that the residual clock error becomes zero mean.

Abstract: Synchronization is effected in a cellular telecommunications network between a timing unit located at control node (e.g., RNC) of the network and a slave timing unit (STU) located at a controlled node (e.g., base station) of the network. Upon determining that a synchronization adjustment of the slave timing unit is necessary, an adjustment signal (e.g., voltage signal) is caused to be input to the oscillator of the slave timing unit in order to change the frequency of the slave's oscillator. Frame counter(s), in communication with the oscillator at the slave timing unit, will thus follow the oscillator continuously with smooth phase adjustments. By avoiding a direct adjustment of the frame counter(s), undesirable phase jumps or steps are avoided that can potentially disturb the air-interface between a base station and mobile station (MS).

Abstract: An enhanced synchronization status messaging capability for synchronous networks is provided in a messaging format that is compatible with existing synchronization messaging standards. Additional messages, which are based on the same predefined code words used in existing synchronous status messages, are differentially coded and carried in available, but unused message positions, in the existing messaging scheme. In one illustrative embodiment, a two part message format is used for carrying information between network elements and between a network element and a co-located BITS clock in-a synchronous network. A first part of the message format carries the traditional quality level information of synchronization references using the set of code words predefined in the applicable standards. For example, the quality information of a synchronization reference is conveyed using 7 out of 10 “like” messages selected from the group of predefined code words set forth in the standards.

Abstract: A system and method for establishing ad hoc communication sessions between remote communication terminals is disclosed. A base station transmits a beacon signal including information about the identity and system clock of the base station. Remote terminals within range lock to the base station, synchronizing their system clocks with the base station's clock and setting their hop sequence and hop sequence phase based on information in the beacon signal. To establish an ad hoc communication session, a master terminal first establishes a link to the base station, which establishes a link to a desired slave terminal. The base terminal exchanges information between remote terminals that enables the master terminal to establish a direct communication session with a slave terminal.

Abstract: Apparatus for communication between a neural network and a user system via a bus includes an activity/frequency converter for each neurone of the network. The activity/frequency converter produces activity pulses which are encoded by encoders and then placed on the communication bus. Arbitration arrangements for each converter include an inhibition control circuit and a blocking circuit connected in common to all the converters to transmit a temporary blocking command to them. Each control circuit detects the presence of a pulse at the output of its associated converter and, while any such pulse is present, activates the blocking circuit so that it transmits the command for temporarily blocking their operation to the other converters.

Abstract: Systems and methods are described for carrier-frequency synchronization for improved AM and TV broadcast reception. A method includes synchronizing a carrier frequency of a broadcast signal with a remote reference frequency. An apparatus includes a reference signal receiver; a phase comparator coupled to the reference signal receiver; a voltage controlled oscillator coupled to the phase comparator; and a radio frequency output coupled to the voltage controlled oscillator.

Abstract: Analog video tape recording (VTR) and video cassette recording (VCR) systems/apparatuses with novel converter of a frequency modulated signal into the pulse-frequency-modulated (PFM) signal during readback are described. The novel converter provides effective filtering function in itself and suppresses all carrier harmonics of the PFM signal. This reduces combination noise at the input to the PFM filter-demodulator by 20-25 db. Therefore, filtering requirements to PFM demodulator are greatly reduced and it can be of very simple design. The novel converter provides significant improvement in performance and reduces cost of analog VTR/VCRs.

Abstract: Method and apparatus for transmitting encoded signals with increased data speed in communications system using system clock synchronization and bit robbing techniques to attain high transmission rates is provided.

Abstract: A time error compensation arrangement (TCOMP) that compensates for a time error (&egr;, &Dgr;k) between a transmitter sample clock in a multi-carrier transmitter and a receiver sample clock (CLK) in a multi-carrier receiver (RX1, RX2) includes a digital time correction filter (FILTER, FILTER′), operative in time domain, to compensate for a linearly increasing contribution (&Dgr;k) in the time error (&egr;, &Dgr;k) and rotation means (ROTOR), operative in frequency domain, to compensate for a second, remaining contribution (&egr;) in said time error (&egr;, &Dgr;k).

Abstract: A device for detecting a predetermined waveform in a received signal and synchronizing the detected waveform to the predetermined waveform is disclosed. The device includes a memory element for storing a reference set of encoded values. The reference set representing an encoded version of the predetermined waveform. An encoder is used to PCM encode the signal to obtain sets of encoded values representing the received signal. A processor calculates the statistical correlation coefficient of the reference set and the signal sets. The processor then determines the maximum statistical correlation coefficient. The predetermined waveform is detected in the signal if the maximum statistical correlation coefficient is greater than or equal to a predetermined threshold value. The device provides a compact, inexpensive, and fast method for detecting a known reference waveform in a received signal.

Abstract: Interface apparatus for interfacing data to a plurality of different clock domains where the clock signals in the different domains are phase locked together and respective clock signals have different frequencies includes a plurality of cascade connected first and second latches coupled between respective clock domains. One of the latches is a clocked Data Latch and the other is a clocked and Enabled Data Latch. A timing generator provides respective domain clock signals, wherein a domain clock signal of a domain providing a data signal is applied to the clock input connection of the first latch of a respective cascade connected set of latches and a domain clock signal of a domain receiving said data signal is applied to the second latch. The timing generator also provides a common Enable Signal phase locked to the domain clocked signals. The common Enable Signal is applied to the enable input terminal of one of the latches of each set of cascade connected latches.

Abstract: The invention relates to a wireless network which includes at least one base station (1 to 3) and a plurality of associated terminals (4 to 14) for the exchange of useful data and control data. According to the invention, the base station (1 to 3) is arranged to transmit the starting instant of a signaling sequence to at least one terminal (4 to 14). In order to evaluate the signaling sequences transmitted by the terminals, the base station (1 to 3) includes a device (21, 22) for correlating a received signaling sequence and for detecting the pulse arising from a received and correlated signaling sequence.

Abstract: A clock signal transmission line in the semiconductor integrated circuit device includes a plurality of straight portions arranged side by side in a predetermined direction and a plurality of bent portions connecting the respective straight portions. At least two of a plurality of signal lines to which a clock signal is transmitted are connected to different straight portions. Consequently, a semiconductor integrated circuit device which can reduce a clock skew when transmitting a clock signal to a plurality of signal lines is provided.

Abstract: A system for transmitting digital information over a synchronous network includes at least one source node and at least one sink node both coupled with the synchronous network. The source node provides source information sampled at a source sample rate (Fsi) to the synchronous network in the form of digital information. The synchronous network operates on a network master clock rate (Fn) with a frequency that may be higher, lower or equal to the source sample rate (Fsi). The digital information is transmitted over the network to the sink node. The sink node processes the digital information to generate synthesized source information.

Abstract: The present invention relates to a method and to an arrangement for synchronising at least one local oscillator (21) with a central time-generating unit (11). The local oscillator (21) serves a so-called element (2) included in a network (A), and the time-generating unit (11) is included in a so-called main unit (1) also included in the network (A). The frequency of the local oscillator (21) can be controlled by periodic and automatic calibration. The physical requirements within a part of the network (A) that includes the main unit (1) and all elements (2, 3, 4) concerned, said part being referred to here as a limited network (B), are so well defined that the transmission time of a time stamp from the main unit (1) to an element (2) will be known with a given degree of certainty. The inter-arrival time of the time stamps is used to calibrate the local oscillator (11) together with the known transmission time.

Abstract: A synchronization device for a synchronous digital message transmission system producing a synchronous output signal including successive transport modules synchronized to a frame clock from a digital input signal. The synchronization device includes a receiver unit for receiving the input signal, a packet assembly device for packaging the input signal into subassemblies of the transport modules, a buffer memory, a writer for writing data bits of the input signal out of the subassemblies into the buffer memory with a write clock, a reader, for reading data bits out of the buffer memory with a read clock in order to form the output signal, and a sending unit (SO) for sending synchronous output signals. The effective bit rate of the subassemblies compared to the standardized value is either lowered or raised by selecting the write clock lower than the read clock.

Abstract: An apparatus that may be configured to generate a wireless radio signal in response to one or more first data signals. The wireless radio signal may comprise a single frequency hopping sequence configured to support one or more peripheral wireless network devices. The apparatus may also be configured to generate the one or more first data signals in response to the wireless radio signal.

Abstract: A process and interface for interconnection of multiprocessor modules by point-to-point serial-to-parallel links. Data processing or data communication modules (A and B) are interconnected by means of high-speed point-to-point serial links conveying multiplexed information organized into frames comprising a start-of-frame recognition pattern. The process, on transmission and on reception, performs an analog synchronization of the basic clocks of the modules to a reference clock generated by one of the modules designated as a reference module, called the master module, the other modules being called slave modules, and a digital synchronization of the start-of-frame of each slave module to the start-of-frame sent by the master module.

Abstract: A self-adjusting path is created by utilizing a phase detector and modifying a clock path and a data path to enable the passing of data in either phase of the clock. The new input path is controlled by the output of the phase detector. Each time a command is issued, the phase of the clock is detected and latched. The phase of the clock at the time the command issues is thus captured and can propagate through the pipeline along with the data. Accordingly, each stage along the data path can be synchronized to a different phase of the clock to reduce data corruption.

Abstract: A data link network system comprising a central node airborne station and a plurality of ground stations each having multi-channel transmitter/receiver capable of transmitting quadrature phase spread spectrum signals and in phase spread spectrum signals both of which contain data. One of said quadrature channels is maintained as a master channel which provides a master time of day clock in the airborne platform of the network system and the other channel is employed as an adjustable time of day clock channel for resynchronizing ground stations after an outage. When an outage occurs between the airborne station and one of the ground stations the airborne station calculates the propagation time to the ground station and shifts the adjustable channel to transmit a spread spectrum data signal which will arrive in synchronization with the time of day in the ground station that had the outage.

Abstract: For restraining jitter amount of a transmission clock signal (16) generated by a digital PLL (8), a data transmission apparatus comprises a {fraction (1/24)} clock generator (6) for dividing frequency of a receiving clock signal (4), a clock multiplier (7) for generating a reference frequency signal (18) by multiplying frequency of the output of the {fraction (1/24)} clock generator (6), and a control unit (28) for controlling a frequency multiplying ratio of the clock multiplier (7) and controlling a frequency dividing ratio of a frequency divider provided in the digital PLL (8). According to jitter amount detected by a jitter detection signal generator (19), the frequency of the reference clock signal (18) is selected among {fraction (1/12)}, ⅛ and ⅙ of the frequency of the receiving clock signal.

Abstract: A digital bus arrangement and an associated method are disclosed. The bus arrangement includes an input synchronization layer and an output synchronization layer. Data transfer between the modules is synchronized using a master clock signal such that data originated by one module is latched and placed on the bus in one clock cycle. Thereafter, in a second or subsequent clock cycle, the data is synchronously latched at the other modules of the system such that the data is available to an intended module. No logic circuitry is present between the input and output synchronization layers.

Abstract: A telecommunications system (18) is provided that includes a first controller (20) and a second controller (22) coupled using a packet-switched network (32). The controllers provide a low cost means of coupling isochronous telecommunication devices. The first controller (20) receives one or more isochronous input channels from a common control shelf (24), such as a private branch exchange (PBX), over a circuit-switched network (27). The first controller (20) encapsulates an isochronous frames from the common control shelf (27) into a data frame that is transferrable over the packet-switched network (32). The second controller (22) is configured to receive the data frame and extract the isochronous frame, which is then transmitted to a peripheral shelf (26), such as a line trunk unit (LTU), using an isochronous circuit-switched network (38). The controllers contain identical functionality, permitting bi-directional transmission of data between the common control and peripheral shelves.

Abstract: The present invention relates to a synchronization method and apparatus, wherein a first end point entering a connection mode change state transmits a request message to a second end point. The second endpoint enters the connection mode change state in response to the receipt of the request message and transmits an acknowledgment and a numbered frame to the first end point. Having received the acknowledgment, the first endpoint leaves the connection mode change state and transmits an acknowledgment acknowledging the numbered frame to the second end point which leaves the connection mode change state in response to the receipt of the acknowledgment.

Abstract: In a fiber-to-the-curb telecommunications system a method of network synchronization is presented in which data is transmitted from a broadband network unit to devices in a residence on a downstream carrier frequency, where the downstream data rate and the downstream carrier frequency are integer multiples of a sub-harmonic of a master clock. In the upstream direction, where data is transmitted from the devices to the broadband network unit, upstream data is transmitted on an upstream carrier frequency and the upstream data rate and upstream carrier frequency are integer multiples of a sub-harmonic of a master clock. Digital downconversion is performed on the data received at the broadband network unit to produce baseband samples.

Abstract: A system and method of synchronizing a pair of communication devices using a carrier signal from a global positioning system (GPS). The method comprises the steps of: receiving a GPS carrier signal at a first device; at the first device, deriving from the carrier signal a transmitter clock signal having a predetermined frequency; transmitting data at the predetermined frequency from the first device; receiving the data at a second device; receiving the GPS carrier signal at the second device; and at the second device, deriving from the carrier signal a receiver clock signal having the predetermined frequency.

Abstract: The disclosure concerns an inter-base station frame synchronization system for use in a mobile communication system having at least one master base station and a plurality of slave base stations. The master base station is arranged to transmit a control channel signal to the slave base stations located around the master base station in synchronization with a reference frame timing. The slave base stations set a control channel signal observation period. The slave base stations are arranged to generate frame timing based on timings of a received control channel signal from the master base station or other slave base stations when the received control channel signal is received during the control channel signal observation period.

Abstract: A method and apparatus for interfacing a central processing unit to a network switch with an external memory that transfers data to the network switch at a different clock speed than transfers of data to the central processing unit provides an interlocking mechanism to prevent overwriting of data and underflows from occurring. The interlocking of the state machines, accomplished by the idling and advancing of a processor state machine and an external memory state machine, prevents either one of the separate state machines from outrunning the other state machine.

Abstract: Methods and arrangements are provided for allowing various devices to communicate data over standard twisted pair wire within a confined region, such as a home environment. The methods and arrangements employ radio frequency (RF) communication techniques to modulate and transmit data signals over existing twisted pair phone lines at RF frequencies. The RF transmitted data can be detected over limited distances by other similarly configured devices. The RF transmitted data is then received and demodulated to regenerate the original data. The methods and arrangements also allow the data transmission to be conducted in accordance with conventional CSMA/CD techniques/protocols. Thus, for example, Ethernet network configured devices can be seamlessly interconnected using the methods and arrangements of the present invention without requiring that additional and/or upgraded wiring be installed in the home environment.

Abstract: A system and method for synchronizing clocks related to telecommunications throughout s point-to-multipoint optical network utilizes downstream data timed using a high frequency transmission clock to distribute timing information of a central telecom-based clock to remote terminals. In an exemplary embodiment, the point-to-multipoint optical network system is an Ethernet-based passive optical network (PON) system that operates in accordance with a Gigabit Ethernet standard. The timing information of the central telecom-based clock is extracted from the downstream data at each remote terminal by recovering the high frequency transmission clock and then, deriving a reference clock, which is synchronized with the central telecom-based clock, from the recovered transmission clock. The reference clock is then used to generate one or more telecom-related clocks that are needed by the remote terminal.

Abstract: In a synchronous code division multiple access (SCDMA) time division duplex (TDD) communication system, a remote terminal uses both open loop and closed loop techniques for synchronization with a base station. The timing of reception of information by tile remote terminal is performed with an open loop technique, while the timing of transmissions from the terminal is performed with a closed loop technique. Furthermore, a clock locked loop in the terminal compensates for differences between clocks of the terminal and the base station. The clock locked loop responds to signals from both the aforesaid open loop and closed loop techniques.

Abstract: The present invention provides a method and apparatus for accurate packet time stamping in a network. The apparatus includes a time stamping logic, where the time stamping logic detects when a packet is transmitted or received; and a time source, where time information from the time source is latched when the time stamping logic detects the packet. In the preferred embodiment, the time stamping logic monitors packet traffic on a bus. When the time stamping logic detects a packet, a time stamping signal is generated which latches time information from the time source. The time information may then be used to measure the transmission delay for the packet for synchronizing the clocks at the transmitting and receiving nodes.

Abstract: The present invention is directed to providing frequency hopping medium access control among a plurality of nodes (e.g., communication stations) in a wireless communication system. The present invention is directed to decentralized control of synchronization among the plural nodes. In accordance with exemplary embodiments, a node used to control synchronization of the communication system can switch from a first master node to a second master node.

Abstract: Synchronization of a powerline modem network (10) with a plurality of devices is provided. A plurality of devices (16 and 18) each include a powerline modem (20) and a clock circuit (22) for synchronizing a data rate. The powerline modem permits data transmission between the plurality of devices over a powerline network on data carriers (28). A synchronization signal is transmitted over the powerline network. The synchronization signal includes a carrier (30) operating at a frequency different from the data carriers. The synchronization signal provides each of the plurality of devices a time reference to synchronize the data rate.

Abstract: An out-of-synchronization condition for a Universal Mobile Telecommunications System (UMTS) is defined for a situation in which it may be difficult to distinguish an out-of-synchronization condition in a downlink dedicated channel from interference on that channel. A request is sent on an uplink from a user equipment (UE) to a base station transceiver (BST) for increased power on a downlink channel experiencing a possible frames out-of-synchronization condition, which may instead be a possible interference condition, so as to attempt to eliminate the possible interference. After a first selected period of time without eliminating the possible interference problem, the uplink is terminated unless a broadcast downlink channel is determined to be experiencing interference below a selected level, in which case the UE is allowed to continue to send the request for increased power. Only after a second selected period of time without eliminating the possible interference problem is the uplink terminated.

Abstract: A new algorithm for clock offset estimation for resources distributed across a network (such as the Internet). By exchanging a sequence of time-stamped messages between pairs of network nodes and separately estimating variable delays for each message direction, present inventive embodiments provide estimates for clock offset between node pairs and the bias of such estimates, thereby to permit more accurate correction. Present inventive algorithms operate in a variety of peer and server network configurations while providing significant improvement in convergence speed and accuracy.

Abstract: Methods to create a cellular-like communication system, such as a Wireless Private Branch Exchange (WPBX), which includes mobile devices such as standard cordless phones (handsets), particularly, mobile devices utilizing the Bluetooth short-range wireless communication protocol. The methods provide seamless and reliable handoff of sessions between Base Stations while the mobile device is moving between picocells, by implementing a high-level of synchronization between the Base Stations and the Switch. Base Stations of picocells having small coverage areas communicate with the handsets. The communication protocol is divided into a low-level protocol performed by the Base Stations and a high-level protocol performed by the Switch connected to all the Base Stations. The methods support mobile computing or telephony devices and communication protocols, which are not specified to handle handoffs of sessions while moving between Base Stations coverage areas in a data, voice or telephony wireless network.

Abstract: The invention relates to a synchronous, clocked communication system, for example a distributed automation system, the stations of which can be arbitrary automation components which are coupled to one another via a data network (1) for the purpose of mutual data exchange. In this arrangement, all possible bus systems such as, e.g. field bus, professional field bus, Ethernet, industrial Ethernet etc. are available for use as the data network (1) of the communication system. One station of this communication system is designated as timing generator and ensures the distribution and maintenance of the communication clock used to and by all stations. The timing generator can also introduce a relative clock (9) in the entire communication system at all stations via the same mechanism. This station is thus also the master of the relative clock (9) or the applicable relative time (16).

Abstract: Satellite positioning system enabled mobile receivers (310) and cellular communication network base stations (330) synchronized with satellite positioning system clocks and method therefore. In a network-assisted embodiment, a variable propagation delay for transmission of an assistance message (232) from the base station to the mobile receiver is determined for correcting the handset clock (318). In others embodiments, local clock drift of mobile receivers (310) and/or base stations (330) are determined by a ratio of local and satellite time differences, based on sequential time snapshots, for use in correcting the local clocks.

Abstract: Methods and an arrangement for synchronizing communication of framed data via asynchronous base stations (BS1, BS2) in a cellular communication system are presented. The synchronization methods are performed continuously by sending out certain system frame counter states from a central node in the system to all its connected base stations (BS1, BS2). Each base station (BS1, BS2) includes a local frame counter (LFCBS1, LFCBS2), which generates local frame counter states (t1(1)-t1(4), t2(1)-t2(4)) correlated to the system frame counter states. Transmission of information via the base stations (BS1, BS2) is synchronized by assigning each data frame (DR(1)-DR(4)) a particular frame number, which is given by the local frame counter states (t1(1)-t1(4), t2(1)-t2(4)), so that data framed (DF(1)-DF(4)) having identical numbers contain copies of a certain data packet.

Abstract: A muticarrier transceiver is provided with a sleep mode in which it idles with reduced power consumption when it is not needed to transmit or receive data. The full transmission and reception capabilities of the transceiver are quickly restored when needed, without requiring the full (and time-consuming) initialization commonly needed to restore such transceivers to operation after inactivity.

Abstract: A digital system includes a master device, a set of slave devices, and a clock generator to generate a clock signal. A transmission channel includes a clock-to-master path extending from the clock generator, through the set of slave devices, to the master device. The transmission channel also includes a clock-from-master path extending from the master device and through the set of slave devices. The transmission channel also includes a slave-to-master path positioned between a first slave device of the set of slave devices and the master device. A master-to-slave path is positioned between the master device and the first slave device. The cumulative length of the slave-to-master path and the master-to-slave path creates a master routing phase shift between a clock signal on the clock-to-master path and a clock signal on the clock-from-master path. A first lead samples the clock signal on the slave-to-master path. A second lead samples the clock signal on the master-to-slave path.

Abstract: A digital subscriber line network allows a plurality of remote modems to communicate without interfering with the communication to the central office. Each symbol of a superframe is converted to a tone vector, and the tone vectors are integrated over a plurality of superframes. The tone vectors of the data symbols are random, and tend to cancel each other out. The tone vector of the synchronization symbol remains constant among the plurality of superframes, and the sum of these tone vectors over a plurality of superframes becomes large. By identifying the largest integrated tone vectors, the network may identify the position of the synchronization symbol. The modems may then align using the position of the synchronization symbol.

Abstract: Automatic switching between clock sources in synchronous networks is accomplished using Synchronous Status Message transmitted over the network and a control circuit positioned between SASE (Stand Alone Synchronization Equipment) and a network element (SDH-NE, Synchronous Digital Hierarchy Network Element).

Abstract: Four (4) unshielded twisted pairs of wires connect a hub and a computer in an Ethernet system: one (1) pair for transmission only, another for reception only and the other two (2) for transmission and reception. The signals in the wires are in packets each having timing signals defining a preamble and thereafter having digital signals representing information as by individual ones of three (3) amplitude levels. The signals received at the computer are provided with an automatic gain control (AGC) and then with digital conversions at a particular rate. A control loop operative upon the digital conversions regulates the AGC gain at a particular value. An equalizer operative only during the occurrence of the digital signals in each packet selects an individual one of the three (3) amplitude levels closest to the amplitude of each digital conversion at the time assumed to constitute the conversion peak.