Abstract: A system and method for providing a clock signal and data signal delay match to improve setup and hold times for integrated circuits is disclosed. In a simplified embodiment, the system comprises a clock receiver capable of removing noise from a received clock signal. A clock buffer is connected to the clock receiver and is capable of driving the received clock signal to a register. A data receiver is located within the system which is capable of removing noise from received data. In addition at least one miniature clock buffer is located within the system, wherein the at least one miniaturized clock buffer is a scaled version of the clock buffer having a scaling factor of K, the scaling factor representing a number of miniature clock buffers utilized to minimize negative variations experienced by the clock buffer.

Abstract: The invention relates to a multimode communication terminal comprising a first modulation/demodulation circuit adapted to communicate with a first radio access network and at least a second modulation/demodulation circuit adapted to communicate with a second radio access network different from the first radio network. The terminal according to the invention comprises a synchronization module provided with means for determining a frequency difference between the first modulation/demodulation circuit and the first radio access network and means for synchronizing the second modulation/demodulation circuit with the second radio access network so as to allow said terminal to compare permanently transmission qualities over the first and second radio access networks.

Abstract: A communication system is provided in which normal communications can be ensured even upon a loss of synchronization on a part of transmission paths configuring a network. The system is to perform data communications within a network configured by a plurality of devices. A synchronization detecting section detects a loss of synchronization for data transmission between devices connected to each other via the network. Upon detection by the synchronization detecting section of the loss of synchronization, a control information retaining section and a switching section included in the first device cause a connection with the second device to be cut off, and then again cause a connection with the device. Upon connection caused by the switching section between the devices, a connection processing section 16 performs a connecting process for enabling data communications between these devices.

Abstract: A system for bi-directional power distribution line communication. The system is configured for data communication with an endpoint transceiver located at a customer premise. The system comprises a time server in electrical communication with the transceiver, the time server configured to retrieve the time. A substation controller is in electrical communication with a power distribution line. The substation controller includes a transceiver and a programmable circuit. The programmable circuit includes a substation clock. The programmable circuit is programmed to periodically retrieve the time from the time server to calibrate the substation clock to the retrieved time, and to control the transceiver to transmit the time to the endpoint transceiver.

Abstract: A method for synchronizing data utilized in a redundant, closed-loop feedback control system is disclosed. In an exemplary embodiment, the method includes configuring a plurality of control nodes within the control system, with each of the plurality of control nodes transmitting and receiving data through a common communication bus. At each of the plurality of control nodes during a given control loop time T=N, the receipt of externally generated data with respect to each control node is verified, the externally generated data having been generated during a preceding control loop time T=N?1. At each of the plurality of control nodes during the given control loop time T=N, output control data is calculated using the externally generated data. During the given control loop time T=N, the calculated output control data from each individual control node is further transmitted over the communication bus to be later utilized by other control nodes during a subsequent control loop time T=N+1.

Abstract: A system and method is provided for timing synchronization of receivers in a wireless network to improve the accuracy of real time location tracking methods utilize time difference of arrival methods. The synchronization signals are provided over the wired network which connects the wireless receiver base stations. The timing signals may be transmitted on an unused pair of wires, or may be superimposed on a pair of wires which are used for Ethernet data signals or a pair of wires used for Ethernet DC power signals.

Abstract: Respective nodes N1 to N3 only detect a carrier, and the node N3 sets a random time between a time after a certain period of time t1 and a time until a certain period of time t2 after the carrier of data D11 is gone as a waiting time so as to transmit data within this waiting time. The node N2 transmits ACK data D12 with respect to the data D11 to the node N1 before the certain period of time t1 after the carrier of the data D11 is gone. The node N3 detects the carrier of the ACK data D12 and again sets a random time after the certain period of time t1 until the certain period of time t2 to transmit the data.

Abstract: A communication system, source and destination ports of the communication system, and methodology is provided for transporting data in one of possibly three different ways. Data is transported across the network at a frame sample rate that can be the same as or different from the sample rate or master clock within the source port or the destination port. If the sample rate of the source port is known, the sample rate of the destination port can be created using a PLL within the destination port and simply employing a phase comparator in the source port. Where economically feasible, sample rate conversion can be used at the source. However, sample rate conversion at the destination is preferred if the source sample rate is forwarded across the network relative to the frame transfer rate of the synchronous network. Again, however, sample rate conversion compares relative phase difference changes similar to the phase difference compared in the digital PLL mode.

Abstract: A method for acquiring frame synchronization of a broadcast channel (BCH) in an asynchronous mobile telecommunication system. The method according to the invention includes steps of acquiring a system timing through a synchronous channel (SCH), demodulating a primary common control physical channel (PCCPCH) based on the system timing, checking a cyclic redundancy check (CRC) by decoding a predetermined time interval of the demodulated PCCPCH, and acquiring frame synchronization of the BCH by reference to the CRC checked result.

Abstract: A method and apparatus for maintaining an ideal frequency ratio between numerically-controlled frequency sources provides a mechanism for maintaining coherence between multiple synchronization references where a known ideal rational relationship between the sources is known. Multiple numerically controlled oscillators (NCOs) generate the multiple synchronization references, which may be clock signals or numeric phase representations and the outputs of the NCOs are compared with a ratiometric frequency comparator that determines whether there is an error in the ratio between the NCO outputs. The frequency of one of the NCOs is then adjusted with a frequency correction factor provided by the ratiometric frequency comparator. The NCO inputs can represent ratios of the synchronization reference frequencies to a fixed reference clock and the NCOs clocked by the fixed reference clock.

Abstract: A method of providing precise common timing in a wireless communications network including at least one timing marker unit with a precise common time source, e.g., GPS. Wireless mobile units and/or timing marker units periodically measure transmission timing differences between pairs of neighboring base stations and each provide the measurements to a base station or central network entity. Timing marker units measure timing associations and return the results. An absolute transmission timing difference (ATD) is determined for each base station timing difference measurement. ATDs are collected and combined for each pair of base stations. A timing relationship is developed for all base stations from the combined ATDs, relating transmission timing of non-reference base stations to reference base stations. Timing associations are extracted for non-reference base stations from these timing difference relationships and the timing associations for the reference base stations.

Abstract: A memory buffer for a memory module board which is connected via a signal line (10-i) to a plurality of memory modules (2-i) mounted on said memory module board having different signal line lengths, wherein the memory buffer (1) comprises for each signal line (10-i) a corresponding integration circuit (18-i) for integrating the transmission time of a measurement pulse transmitted via said signal line (10-i) between said memory buffer (1) and a memory module (2-i) connected to said signal line (10-i).

Abstract: A process for transmission of information between at least two devices comprises: generating a serial message coded by means of a time sequence of binary transitions called bits; reducing the time length of all bits in the message by changing them into shorter bits, in order to insert additional bits whose half duration falls at the moment in time where the transitions between unchanged bits occurred when no additional bits are inserted; keeping the half duration point of all reduced data bits to the same place as they were in the unchanged message; keeping the total duration of the message containing the additional bits identical to the total length of the unchanged message. The process is compliant with the MIDI standard and allows the increase of the amount of various distinct messages which it is able to convey.

Abstract: A method for synchronizing a time architecture of a mobile network that includes a plurality of network components, each having a time subsystem clock that is updated using a network time protocol (NTP) program. The method includes operating the components in a hierarchical fashion and booting up all the network components such that execution of a NTP sub-program for making small incremental changes to the each component time subsystem clock is delayed. Additionally, the method includes iteratively executing a NTP sub-program for making large changes to each component time system clock until each component time sub-system clock establishes an initial synchronization with a parent component time sub-system clock. Furthermore, the method includes iteratively executing the NTP sub-program for making small incremental changes once initial synchronization is established such that each component time sub-system clock maintains synchronization with the parent component time sub-system clock.

Abstract: A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a phase shift relative to the input clock signal that is a function of the current and future data signals. The clock synchronization circuit may also generate a plurality of phase shifted clock signals, with each phase shifted clock signal having a respective phase shift that is a function of the current and future logic states of groups of the other data signals.

Abstract: A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.

Abstract: A communication access protocol improves the accessibility of devices operating on an asynchronous network (100), while supporting reduced power consumption. The network (100) includes a mediation device (130) for facilitating communications among network devices. Generally, each network device periodically transmits beacon signals to advertise its presence, and listens for communication signals targeted at the network device (532, 534). A device initiating communication with another operates in one of at least two operating modes in order to establish communications (536, 537, 538). In one mode, the initiating device communicates with the mediation device in order to derive timing information for the other device (537). In another mode, the initiating device listens to receive beacon signals directly from the target device in order to synchronize communications with the device (538).

Abstract: A system for determining a timing offset between a first clock and a second clock at respective first and second points in a communications network. A series of request signals is transmitted from the first point in the network to the second point in the network. A series of reply signals is transmitted from the second point in the network to the first point in the network. Each reply signal and a corresponding reply signal having a minimum round trip delay time are identified and a minimum single leg delay time is determined from the minimum round trip delay time. A timing offset between the clock values of the first clock and the second clock at a first instance is estimated, the estimation being based upon the minimum single leg delay time, and a transmission time and a reception time of one of the identified request signal and the corresponding reply signal, as given by the respective clocks at the transmission and reception points of the signal.

Abstract: A clock synchronization method and apparatus is disclosed for use in a communication system including a plurality of wireless nodes communicatively coupled via a wireless network, each of the plurality of wireless nodes having a local time base, and one of the plurality of wireless nodes being designated as a master node having a master time base which serves as a master clock against which the local time bases are synchronized. The clock synchronization method includes the steps of periodically transmitting synchronization frames to the plurality of non-master nodes so as to adjust the slave clocks associated with the respective non-master nodes. The synchronization frames are distributed from the master node at near-periodic intervals and includes a cycle time value that corresponds to the end of the previously transmitted synchronization frame. The slave clocks (i.e.

Abstract: A clock control circuit for use in a multi-channel baud-rate timing recovery loop includes a control circuit responsive to a phase error signal from at least one phase detector for generating at least one clock control signal, wherein said control circuit propagates adjustments required for frequency correction in a synchronous fashion across all of the N-channels.

Abstract: The demodulation unit demodulates a received signal. The detection circuit detects the final data contained in a received data stream supplied from the demodulation unit. When detecting the final data, the detection circuit outputs the final data notification signal. The standby period timer sets the standby time in accordance with the final data notification signal output from the detection circuit.

Abstract: A changeover arrangement for the clock signals of parallel transmission connections of an assured data transmission link, wherein a clock signal is sent for the transmission paths by parallel outdoor units (OU) located in succession to a common indoor unit (IU), the clock signal is received by a corresponding set of second outdoor units, where phase locked loop signals are used to achieve the lock to the signal, and subsequent to which a second IU receives information of the mode of the phase lock. In addition, when errors are caused in the employed connection, the receiving unit selects a transmission path that has fewer errors based on mode information obtained from the outdoor unit.

Abstract: A wireless digital telephone system containing at least one emulated base station plus one or more subscriber stations, the emulated base station comprising a station similar to the subscriber station but having the capability of initiating a synchronization process whereby it is enabled to assign time slots to the subscriber station within the frame pattern of an amplitude signal by means of monitoring for positive edges in the signal.

Abstract: A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a phase shift relative to the input clock signal that is a function of the current and future data signals. The clock synchronization circuit may also generate a plurality of phase shifted clock signals, with each phase shifted clock signal having a respective phase shift that is a function of the current and future logic states of groups of the other data signals.

Abstract: A receiver includes clock termination circuitry that is capable of applying either a terminating impedance or a high impedance to a transmission path that carries a clock signal. When multiple of these receivers are used to service data links that share a clock signal, one of the clock termination circuits applies the terminating impedance to the transmission path that carries the clock signal while the other clock termination circuit(s) applies a high impedance to the transmission path. The receiver also includes a plurality of high rate serial bit stream buffers and a clock signal buffer along with the clock termination circuitry. In other embodiments, the receiver includes a deserializer and may include a controller. The receiver may service a dual link Digital Visual Interface.

Abstract: A controller arrangement for effectuating data transfer across a clock boundary between a core clock domain and a bus clock domain, wherein the core clock domain is operable with a core clock signal and the bus clock domain is operable with a bus clock signal. A bus clock synchronizer controller portion is operable to generate a set of clock relationship control signals, at least a portion of which signals are used in generating a set of bus domain synchronizer control signals towards bus-to-core and core-to-bus synchronizers. A core clock synchronizer controller portion is provided for generating a set of core domain synchronizer control signals towards the synchronizers. The core clock synchronizer controller portion is operable responsive to the clock relationship control signals as well as configuration information signals indicative of different skew tolerances and latency values associated with the clock signals.

Abstract: A high-speed digital interface circuit for use with an N bit digital data signal is disclosed. The circuit comprises a source device that initially receives the N bit digital data signal, and a sink device that receives the N bit digital data signal from the source device. The N bit digital data signal has a skew when received by the sink device. A skew detection circuit in the sink device detects the skew in the N bit digital data signal and generates a skew detection signal. A line supplies the skew detection signal to the source device. A compensation circuit in the source device receives the skew detection signal and compensates for the skew in the N bit digital data signal.

Abstract: A data transmission process with auto-synchronised correcting code, auto-synchronised coder and decoder, corresponding transmitter and receiver. According to the invention, synchronisation management signals (HS, SS, ID) are formed and, under the control of these signals, a header is inserted before a data group and after it a correcting code. At receive end, these synchronisation management signals are reconstituted, the presence of a header is detected and any erroneous symbols are corrected. The invention also provides for an auto-synchronised coder and a decoder and for a transmitter and a receiver using them.

Abstract: A method and apparatus for plesiochronous synchronization of an integer N plurality of subscriber networks to a hub network. Each subscriber network including a sub's clock, and the hub network includes a hub's clock.

Abstract: The present invention is a receiver having a radio frequency (RF) front end, a pulse detector operatively coupled to the RF front end, and a data recovery unit operatively coupled to the pulse detector. The data recovery unit is configured to receive spread spectrum RF signals having different pulse repetition frequencies and using different modulation techniques. The receiver may operate in conjunction with a transmitter as a transceiver. The receiver may also operate in a networked environment in which a network of transceiver node devices comprise a first slave transceiver having a receiver configured to receive spread spectrum signals, and a second slave transceiver configured to communicate with the first slave transceiver. Additionally, a master transceiver is in communication with the first slave transceiver and the second slave transceiver. The master transceiver is configured to manage data transmissions and synchronization between the first slave transceiver and the second slave transceiver.

Abstract: The present invention is a system and method for enabling multicast synchronization of initially unicasted content. Multiple unicast streams are synchronized in order to convert the unicast streams into a multicast stream. Each unicast stream may be accelerated or slowed down in relation to a reference stream to a common point within each stream upon which the unicast streams are replaced by a multicast stream of the same content.

Abstract: A method for controlled synchronization to an astable clock system, and reception unit corresponding thereto are disclosed. Soft synchronization using a slight change in the period duration of the clock signal produced makes it possible to alter said clock signal such that a phase difference between the stable clock signal produced by a phased locked loop upon a synchronization signal and the clock signal produced for an application is slowly reduced until the two clock signals are in synchronization with one another after a period of time.

Abstract: A method for synchronizing a plurality of sub-systems, comprising the steps of measuring a relationship between a divider associated with each of the plurality of sub-systems; and adjusting a phase of one or more of the dividers to a known relationship with one of the dividers. A command is issued synchronous to a divider associated with one of the plurality of sub-systems. The command is received at one of the sub-systems and is acted upon synchronous to a divider associated with the one of the sub-system receiving said command.

Abstract: A method of synchronizing or initiating channel lock in a serial loop formed by an initializing transceiver and subject transceivers disclosed. Should a transceiver in the serial loop detect that its receiving serial channel is desynchronized, it sends an unlock signal to the next transceiver in the loop. The unlock signal guarantees that the next transceiver's receiving serial channel will be desynchronized. Only the initializing transceiver may initiate a channel lock sequence.

Abstract: A system and method for establishing and maintaining node clock synchronization in a wireless network. The system and method calculates the clock shift, clock drift and propagation delay values using a series of message exchanges and control algorithms between a selected reference node and a client node in a wireless network, then uses these values to synchronize the client node clock to the reference node clock.

Abstract: A method for synchronizing communications in a wireless communications network wherein time synchronization is performed between a clock master and a clock slave. To achieve synchronization between the clock master and the clock slave, several time synchronization passes are initiated by the clock slave to the clock master. For every pass, each clock slave component generates and transmits a first timing cell containing a transmission time based on the clock slave's component clock, to the clock master. Upon receipt of the first timing cell, the clock master generates and transmits to the clock slave component a second timing cell containing the time the clock master received the first timing cell and the time the clock master transmitted the second timing cell. Upon receipt of the second timing cell, the clock slave component will obtain its reception time and calculate a transmission delay based on the reception time and the timing information contained in the timing cells.

Abstract: Decoders process a digital input word to derive thermometer-coded signals for controlling one cell of an array of cells, commencing operation at the rising edge of a first clock signal. Each cell has a first latch clocked by a second clock signal, delayed by a preselected delay time ?1 relative to the first clock signal, and a second, transparent latch clocked by a third clock signal whose rising edge coincides with the rising edge of the first clock signal and whose falling edge coincides with the rising edge of the second clock signal. The rising edge of the third clock signal is not affected by jitter associated with a delay element used to delay the first clock signal by ?1. The falling edge is affected by such jitter, but is prevented from feeding through to final outputs because the second latch is non-transparent at that falling edge.

Abstract: The present invention relates to a method of synchronisation between communication networks exchanging information by frame of informations, each communication network having clock and the number of clock pulses is monitored by a counter. The synchronisation is made by reading information representing the counted clock pulses of the clock of the first network at the appearance of a reference event, inserting at least said information or calculated information on the basis of said information into the frame of information as the synchronisation information, transferring said frame of information from the first to the second network, reading information representing the number of counted clock pulse of the clock of the second network at the appearance of reference event, reading synchronisation information inserted in received frame of information from the first network, calculating a difference between information and synchronising the second network.

Abstract: According to the present invention, a three-line bus is used for communication between a first digital unit (1) and two other digital units (3). The three-line bus includes a system clock line (SCL) as well as a data transmission line (SD) through which data is sent from the two other units (3), i.e. transmitting units, to the first unit (1), i.e. receiving unit. The system uses an authorization line (WS) for determining which of the two transmitting units (3) is capable of writing data on the data transmission line (SD) and when it can do so. The communication from the first unit (1), now operating as a transmitter, to the two other units (3), now operating as receivers, is made possible by the fact that data signals are also injected in the authorization line (WS) and transmitted through the line together with the authorization control signals.

Abstract: A method for providing a message-time-ordering facility is disclosed. The method comprises initiating the message-timer ordering facility for a message at a sender system. Initiating includes setting a delay variable to zero. The message is sent to a receiver system in response to initiating the message-time-ordering facility. Sending the message includes marking the message with a first departure time-stamp responsive to a sender system clock and transmitting the message to the receiver system. The message is received at the at the receiver system, receiving includes delaying the processing of the message until the time on a receiver system clock is greater than the first departure time-stamp and recording a time associated with the delaying the processing of the message in the delay variable. A response to the message is sent to the sender system in response to receiving the message.

Abstract: An improved receiver architecture is disclosed comprising a latching mechanism coupled to receive a data stream, and a signal generator for generating latching control signals for controlling the operation of the latching mechanism. The signal generator generates one latching control signal per data period of the data stream, with each latching control signal coinciding approximately with the midpoint of a corresponding data period. The signal generator generates the latching control signals based upon a reference signal, which in one embodiment, coincides approximately with the midpoint of a data period of the data stream. The receiver may further comprise an adjustable delay element and a delay adjustment control. The adjustable delay element receives a clock signal and imposes a variable delay thereon to derive the reference signal used to generate the latching control signals. The magnitude of the variable delay is controlled by the delay adjustment control.

Abstract: To avoid signal quality degradation in resynchronization procedures, a base station and a mobile station do not adjust their timing simultaneously. Generally, a timer or a clock in each of the mobile and base stations is not adjusted at the same time. For example, the timing of the base station may be changed during a first time interval while that of the mobile station may be changed during a second, different time interval. In one example, non-limiting embodiment, a radio network controller determines the difference between the base station timing and the timing of the radio network controller. If that difference exceeds a threshold, the radio network controller determines a timing adjustment based upon the difference. The timing adjustment is communicated to the base station which incrementally adjusts its timing during a first set of time intervals. The mobile station detects the base station timing and adjusts its own timing during a second set of intervals.

Abstract: A technique for synchronizing clocks in a network is disclosed. In one exemplary embodiment, the technique may be realized as a method for synchronizing clocks in a network. The method comprises receiving a first timestamp and a second timestamp, each indicating a respective time instance as determined by a first clock signal within the network. The method also comprises measuring a first time interval between the first timestamp and the second timestamp. The method further comprises generating a difference signal representing a difference between the first time interval and a second time interval, and generating a second clock signal based upon the difference signal such that the second clock signal is synchronized with the first clock signal.

Abstract: A clock architecture employing redundant clock synthesizers is disclosed. In one embodiment, a computer system includes first and second clock boards. The first clock board may act as a master, generating a system clock signal, while the second clock board acts as a slave. The first clock board may monitor a phase difference between a first crystal clock signal and a feedback clock signal. If the phase difference exceeds a limit, the first crystal clock signal may be inhibited, preventing the first clock board from generating the system clock signal. The second clock board may monitor the system clock board in reference to a feedback clock signal. If the second clock board detects a predetermined number of consecutive missing clock edges, it may enable a second crystal clock signal, which may be used to generate a system clock signal.

Abstract: A method and an apparatus are provided for synchronizing clock signals in spatially distributed nodes in large, synchronous electronic, optical, optoelectronic or wireless systems, such as systems comprising arrays of microprocessors and memories, and telecommunication systems. The nodes comprise a master node and a plurality of slave nodes. The master node generates first and second identical pulse trains and propagates them to the slave nodes via a first and second propagation channels, respectively, so that a pair of pulses, one from each pulse train, arrive at each slave node substantially simultaneously, travelling in opposite directions. Each slave node generates a clock signal event in response to the substantially simultaneous arrival of each pair of pulses. The master node maintains the rate of the two pulse trains such that there are “pN” pulses in each propagation channel at any time, where “N” is the number of nodes and “p” is an integer.

Abstract: A method and a system for reliably supplying information about an electronic device employed as a primary information signal receiver device to an electronic device employed as a primary information signal sender device via an existing analog transmission line or digital serial transmission line. A set top box (STB) employed as the primary information signal sender device and a VTR (video tape recorder) employed as the primary information signal receiver are connected to each other via an analog transmission line.

Abstract: A method of synchronizing nodes of a telecommunication network in which a master node is coupled to a Primary Reference Clock (PRC) and a plurality of slave nodes are each arranged to synchronize their internal clocks to the PRC using data received on incoming data links. The method includes propagating Synchronization Status Messages through the network from the master node, with each node through which a message passes incorporating into the message its own identity, thereby generating in each message a node path which has been followed by the message. For each incoming link of each node, the path or path length of a Synchronization Status Message received on that link is registered as an attribute for that link.

Abstract: A method for synchronizing a timing device of a client station via a communications network is disclosed. A plurality of packets is sent from a time server to the client station via the communications network. Upon receipt of the plurality of packets at the client station a time indicative of a local time of receipt of the plurality of packets is determined and the plurality of packets are returned to the time server via the communications network. Upon receipt of the plurality of packets at the time server data in dependence upon round trip delay of the packets and variance in packet spacing are determined and compared to threshold values. If the determined data are within the threshold values data indicative of a time correction are determined and sent from the time server to the client station.

Abstract: Synchronization and desynchronization of a data signal transported in a synchronous frame across a synchronous communications network, such as SONET/SDH, reduces waiting-time jitter. A timing estimate (F) indicative of a relationship between a data rate (f1) of the data signal and a reference frequency (f2) of the synchronous communications network is calculated and communicated through the synchronous communications network, for example in the Synchronous Payload Envelope of a SONET frame. The data signal is recovered using a desynchronizer Phase-Locked Loop steered by the timing estimate (F). The timing estimate (F) can be any one or more of: a ratio between the data rate (f1) and the reference frequency (f2); a difference between the data rate (f1) and the reference frequency (f2); and a phase difference between a recovered data clock signal associated with the data rate (f1) and a reference clock signal associated with the reference frequency (f2).

Abstract: A method for synchronizing a data exchange between a data source and a control device is provided. A synchronization request signal is first transmitted via the bus system to the data source, which then measures a signal propagation time from the control device to the data source. In the data source, a transmission delay time is set which is dependent on the measured signal propagation time. Data which are to be transmitted are delayed by the transmission delay time. A bus system for synchronizing a data exchange is also provided. After receiving a synchronization request signal, the data source measures signal propagation times and sets a transmission delay time in a transmission delay device on the basis of the measured signal propagation times.