Abstract: The invention relates to a synchronous, clocked communication system, for example a distributed automation system, the stations of which can be arbitrary automation components which are coupled to one another via a data network (1) for the purpose of mutual data exchange. In this arrangement, all possible bus systems such as, e.g. field bus, professional field bus, Ethernet, industrial Ethernet etc. are available for use as the data network (1) of the communication system. One station of this communication system is designated as timing generator and ensures the distribution and maintenance of the communication clock used to and by all stations. The timing generator can also introduce a relative clock (9) in the entire communication system at all stations via the same mechanism. This station is thus also the master of the relative clock (9) or the applicable relative time (16).

Abstract: The present invention discloses a method and system for synchronizing processing modules. More specifically the present invention utilizes a master clock signal and associated synchronization information to coordinate the function dictated by packets within a synchronization stream. The master clock has multiple sources. Each module in the system is connected to each clock source to ensure that if one source fails, the module will not fail. The clock signal to each module is further passed through a locked oscillator, which will continue to maintain the clock signal should the master clock signal fail. Each module contains a sync decoder to decode the SYNC packets in the synchronization stream, into system time events. The system time events are then passed to a plurality of event receivers. Each event receiver contains at least one flywheeling counter to ensure that each event receiver remains in synchronization with the system time events being passed by the sync decoder.

Abstract: In a CDR (clock data recovery) deserializer, a clock divider receives a recovered clock signal (SCLK) and generates a divided clock signal (RPCLK). The frequency of the divided clock signal is lowered with each cycle of the divided clock signal being generated for each count of cycles of the recovered clock signal up to a predetermined ratio number. A serial-to-parallel shift register shifts in recovered serial data bits with each cycle of the recovered clock signal and outputs the predetermined ratio number of the shifted recovered serial data bits at a predetermined transition of every cycle of the divided clock signal. A SYNC (synchronization) detect logic asserts a VRS (diVider ReSet) signal coupled to the clock divider for controlling the clock divider to generate the predetermined transition for a cycle of the divided clock signal when the VRS signal is asserted.

Abstract: A multicast radio data communication system comprising a master and a plurality of slave stations uses a retransmission protocol. Data is transmitted by the master station and received by the slave stations. Slave stations having the weakest radio link are designated primary stations, and all other slaves are designated secondary stations. Any slave station may transmit a negative acknowledgement but only the primary stations may transmit a positive acknowledgement. Positive acknowledgements are transmitted in separate time slots, but negative acknowledgements transmitted by the secondary stations overlap the positive acknowledgements transmitted by primary stations. These negative acknowledgements corrupt reception of the positive acknowledgement by the master station, thereby ensuring that the data is retransmitted.

Abstract: A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.

Abstract: An improved signal synchronizing circuit for prohibiting signals traveling from a first clock domain operating with a first clock to a second clock domain operating with a second clock when the first clock is not active. The synchronizing circuit comprising at least one signal receiving module for receiving at least one selected signal in the first clock domain, a detection circuit producing a detection signal indicating that the first clock is active, and at least one output selection module for passing the selected signal from the first clock domain to the second clock domain when the first clock is active.

Abstract: The present invention provides a transceiver couplable to a communications network having a jitter control processor and methods of operating the same. In one aspect of the present invention, the jitter control processor of the transceiver includes a transmitter stage that controls a transmit signal. In one embodiment, the transmitter stage includes a transmit time error measurement system configured to generate a transmit time error signal as a function of timing synchronization associated with a communications network clock and a transceiver master clock, a transmit filter circuit configured to develop a filtered time error signal as a function of the transmit time error signal, and a stuffing control system configured to insert a stuffing control signal into the transmit signal as a function of the transmit time error signal and the filtered time error signal.

Abstract: The present invention is a method for adjusting a timing of at least one first base station to maintain synchronization with a neighboring base station. An estimation of a timing accuracy associated with each said at least one first base station with respect to said neighboring base station is determined. For each of the first base station having its timing accuracy over a threshold, a first message to transmit a communication burst is received by the first base station. The communication burst is then received by the neighboring base station and a measurement of an estimated time difference between the first base station and the neighboring base stations in response to a second message is made. The first base station's timing is then adjusted in response to the measurement.

Abstract: A clock system is disclosed for distributing and generating a digital clock signal for a plurality of electronic assemblies. The clock system includes a remote fixed-frequency clock for generating a first clock signal of a first frequency and a plurality of local clock modules. The local clock modules are respectively disposed on the plurality of electronic assemblies and each include synthesizer circuitry for creating a variable clock signal of a different frequency than the first frequency. Fanout circuitry is coupled between the remote fixed frequency clock and the plurality of local clock modules to distribute the first clock signal.

Abstract: A method of controlling data sampling clocking of asynchronous network nodes, each asynchronous network node having a local clock and transmitting and receiving packets to and from an asynchronous network according to an asynchronous network media access protocol. An asynchronous network node capable of transmitting and receiving packets on the asynchronous network is designated as a master node. Each non-master asynchronous network node which desires to synchronously transport packets across the asynchronous network is designated as a slave node. A master node clock of the master node is synchronized with a slave node clock of each slave node. Each slave node clock is continuously corrected compared with the master node clock to smooth slave clock error to an average of zero compared with the master clock as a reference using timestamp information from the master node.

Abstract: A wireless network includes a plurality of base stations that provide a wireless communication capability for a plurality of mobile stations. Each base station includes a local clock unit with a clock divider that generates local clock signals from a master clock signal received from a master clock source. The base stations are partitioned into a plurality of clusters. A sync pulse is propagated to each base station of the wireless network in order to reset their respective clock dividers. resetting of the clock dividers provides synchronization of local clock signals among the base stations. The sync pulse is propagated to all bases stations within a first cluster wherein one of the base stations in the first cluster is also a member of a second cluster. The base station that is part of the first and second clusters then propagates the sync pulse to other base stations in the second cluster and so on until the sync pulse has been delivered to all base stations in the wireless network.

Abstract: A method and apparatus for communicating between a plurality of asynchronous transmitting and receiving systems using digital streams arranged in multiple access frames comprises a master system, which cycles a counter using a clock reference to generate a master count, and uses the master count to establish a master frame count. A slave system cycles a counter using a clock reference to generate a main count, and uses the main count to establish a main frame count. From a difference between the master frame count and the main frame count of the slave system, a frame count offset value is determined. A slave frame count for the slave system is then established by adding the offset value to the main frame count, and thereby aligning the slave frame count of the slave system with the master frame count and incrementing the slave frame count when the main count is incremented.

Abstract: An apparatus that may be configured to generate a wireless radio signal in response to one or more first data signals. The wireless radio signal may comprise a single frequency hopping sequence configured to support one or more peripheral wireless network devices. The apparatus may also be configured to generate the one or more first data signals in response to the wireless radio signal.

Abstract: A terminal device is provided for communicating data signals with a central communication device via a first signal carrying line and a second signal carrying line. The first signal carrying line is arranged for transporting a first signal and the second signal carrying line is arranged for transporting a second signal, wherein the first and second signals have equal content. The first signal carrying line has a first propagation time and the second signal carrying line has a second propagation time, such that the first propagation time is shorter than the second propagation time. The terminal device includes a signal quality comparison element for determining a first signal quality of the first signal and a second signal quality of the second signal, for comparing the first and second signal qualities, and for accepting the one of the first and second signals that has a better quality.

Abstract: A master-slave system includes a clock and phase signal generator to produce a clock signal at a given frequency and a phase signal at an effective frequency, where the phase signal may or may not be periodic and has an effective frequency less than the given frequency. A clock line is connected to the clock and phase signal generator to carry the clock signal. A phase line is connected to the clock and phase signal generator to carry the phase signal. The phase line includes a phase-to-master path to carry a phase-to-master phase signal and a phase-from-master path to carry a phase-from-master phase signal. A master device is connected to the clock line and the phase line. A data bus is connected to the master device. A slave device is connected to the data bus, the clock line and the phase line. The slave device processes data on the data bus in response to the clock signal and the phase signal.

Abstract: An apparatus including a frame buffer memory; a set of frame synchronizers coupled to the frame buffer memory; and, a set of receivers coupled to the buffer memory and a corresponding frame synchronizer in the set of frame synchronizers. Each receiver is configured to receive a data stream having a first clock rate, and detect changes in the data stream using a second clock rate.

Abstract: The present invention is a system and method for time synchronizing a plurality of base stations in a wireless communication system. The system determines an estimate of a timing accuracy associated with each base station. When a base stations's timing accuracy is over a threshold, the system determines if there is a neighboring base station with a better timing accuracy. The base station over the threshold is adjusted in response to an estimated difference between that base station and the neighboring base station.

Abstract: A data transmission module for transmitting data between a radio communication network that transmits data at a specified rate and data processing means includes network interface radio means for interfacing the data processing means with the radio communication network, data adapter means interposed between the network interface radio means and the data processing means through which data flows under the control of a sequencer means, wherein the sequencer means includes means for frequency-locking the sequencer means to the rate of the network. The data transmission process of the module includes the steps of locking the sequencer means to the rate of the network and synchronizing the flow of the data through the adapter means with the network.

Abstract: A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal.

Abstract: A method of providing improved accuracy of the calculation of the long-term average arrival rate (AAR) of an ATM packet stream is disclosed. Using this method, accurate synchronization of a receiver clock to a network clock is achieved. The invention measures the variable time interval, T, required to complete the arrival of a known and fixed number of data packets, C. Using a predetermined and relatively large number of data packets, a time interval measurement is accurately measured to very precise values. Because the time interval measurement is triggered precisely by the arrival of the first data packet to the complete arrival of the last data packet in the session, there is no quantization error with respect to the first and last data packet. AAR is then calculated as (C*S)/T, where S is the number of samples per data packet.

Abstract: The present invention relates to a communication system comprising devices (2a-2d) having means for short range communication using a certain frequency band. The frequency band is divided into communication channels. In the communication system some of said communication channels are predefined for establishment of the connection and other communication channels are predefined for data transfer between at least two devices. The present invention also relates to a communication device for communication in a communication system, the device having means for short range communication using a certain frequency band, which is divided into communication channels. The present invention further relates to a method for performing communication in a communication system comprising devices, which have means for short range communication using a certain frequency band, which is divided into communication channels.

Abstract: In one aspect the present invention describes an electronic circuit for transmitting voice packet data over a wireless network with an upstream transmission mode and a downstream transmission mode. The circuit comprises a first phase-lock loop (PLL) for locking a first clock to a time stamp signal, wherein the first clock synchronizes upstream data transmission over the wireless network; and a second PLL for locking a second clock to the time stamp signal, wherein the second clock is used for sampling voice data for downstream voice data transmission over the wireless network.

Abstract: An information collecting portion collects predetermined information. A position detecting portion detects the position of a portable terminal device at the present time. A managing portion manages the predetermined information collected by the information collecting portion and the information of the position, detected by the position detecting portion when the information collecting portion collects the predetermined information, together.

Abstract: In a method of estimating the relative frequency uncertainty between two parts of a mobile radio system able to communicate via two mobile radio networks at first and second particular frequencies, each part of the mobile radio system has a clock from which the particular frequency is derived and the uncertainty is estimated by measuring the number of pulses of each of the clocks during a time window of duration T starting at a time t. The method includes the following steps, with the time window T sliding: a) measuring the number of pulses of each of the clocks at n intermediate times t+(T/n), t+(2T/n), . . . , t+(nT/n), where n is a positive integer, b) storing the numbers of clock pulses thereby obtained in memory, c) calculating the relative frequency uncertainty at time t+T from the numbers of clock pulses stored in memory.

Abstract: Serpentine trace patterns are used to add length to traces for matching delays to groups of signals on separate transmission pathways on circuit boards. By providing reverse coupling by patterning the traces in concentric fashion, this invention enables closer spacing between adjacent trace segments of the serpentine pattern.

Abstract: The invention relates to a communications network (1) comprising a plurality of network nodes (2), which include each a synchronization circuit (5) for generating a global clock signal (GT) from a local clock signal (LT) formed by a clock generator (4) in dependence on a time of reception of a message. The synchronization circuit (5) includes a divider arrangement (8) for dividing the local clock signal (LT) in dependence on a correction term (KT) and at least one divider factor which is produced by a scaler arrangement (9). The comparator circuit (10) is provided for forming the correction term by comparing the instant of reception of a message and of the local clock signal LT. Furthermore, the synchronizing circuit (5) includes a divider control (7) which may perform a change of at least one divider factor when the correction term (KT) exceeds a predefined first threshold.

Abstract: A digital subscriber line network allows a plurality of remote modems to communicate without interfering with the communication to the central office. Each symbol of a superframe is converted to a tone vector, and the tone vectors are integrated over a plurality of superframes. The tone vectors of the data symbols are random, and tend to cancel each other out. The tone vector of the synchronization symbol remains constant among the plurality of superframes, and the sum of these tone vectors over a plurality of superframes becomes large. By identifying the largest integrated tone vectors, the network may identify the position of the synchronization symbol. The modems may then align using the position of the synchronization symbol.

Abstract: A wireless communication apparatus, a wireless communication method thereof, and a wireless communication system employing the same. A master device of the wireless communication system requests one slave device of a network to perform a function of a master device for a predetermined time, and sends Piconet information about other slave devices of the network, while the one slave device receives the Piconet information from the master device and communicates with the other slave devices of the network for a predetermined time as a temporary master device. Accordingly, the one slave device becomes a dynamic master device and communicates with the other slave devices by using a frequency hopping sequence and a clock of a previous master device as they are, there is no need to transmit the frequency hopping sequence and the clock of the new master device to the slave devices, and accordingly, much time can be saved.

Abstract: A data and clock signals from a source (12) are transmitted from a location (10) to a distant location (40) together with a phase signal which estimates the difference in phase between a data clock signal and a reference clock signal generated by a reference clock (24) at location (10). At the second location (40), the phase signal is used to address coefficients stored in a read only memory (56) which are used to condition a resample or interpolate filter (50) which generates resampled data signals.

Abstract: A wireless network is disclosed including at least one base station and a plurality of assigned terminals for exchanging user data and control data. The base station is arranged for transmitting the start time of at least one signaling sequence of at least terminal. For evaluating the signaling sequences transmitted by the terminals, the base station includes a device for correlating a received signaling sequence and for detecting the pulse evolving from a received and correlated signaling sequence. A terminal generates a signaling sequence by folding two code sequences.

Abstract: A synchronization system in accordance with the principles of the invention includes a central synchronizing management unit, at least one synchronization distribution unit, and at least one network element. Each synchronization distribution unit receives synchronization and management information from the central synchronization management unit. This information may be transmitted directly from the central synchronization management unit, or it may be transmitted though another synchronization distribution unit in a group of a daisy-chained synchronization distribution units. The daisy-chained arrangement employs both active and passive optical paths. The central synchronizing management unit may query any synchronization distribution unit within the system to obtain performance statistics.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of synchronizing two ends of a bi-directional network communication path includes the following. A sequence of predetermined characters are repeatedly transmitted from an end of a bi-directional network communication path if reception is lost at that end. Synchronization or resynchronization occurs from both ends if the sequence of predetermined characters is received at the other end.

Abstract: The invention concerns a method of checking the synchronization between at least two nodes Ni?1, Ni, with i=1, . . . , n in a network, each of said nodes having respectively an internal clock having a respective clock frequency Fi?1, Fi, wherein said method includes the following steps: a) transmitting the frequency Fi?1 of the internal clock from the node Ni?1 to the node Ni, b) comparing the frequency Fi?1 of the internal clock of the node Ni?1 transmitted to the node Ni with the frequency Fi of the internal clock of said node Ni, c) checking the synchronization between the nodes Ni?1 and Ni using the result of the comparison between the frequencies Fi?1 and Fi.

Abstract: Systems and methods are described for a core sync module. A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal. An apparatus includes a first input clock digital phase-locked loop; a second input clock digital phase-locked loop; a stratum clock state machine coupled to the first input clock digital phase-locked loop and to the second input clock digital phase-locked loop; and a main clock phase-locked loop coupled to the first input clock digital phase-locked loop, to the second input clock digital phase-locked and to the stratum clock state machine.

Abstract: Systems and methods for wide offset frequency synchronization in OFDM communications. Frequency domain OFDM bursts include training symbols having known transmitted values in known frequency domain positions. Received values at the known training symbol positions are correlated from burst to burst. The magnitudes are used to establish and correct small integer frequency offsets as measured in frequency domain symbol widths. The phase of the correlation result is used to determine and correct integer frequency offsets that exceed the training tone spacing. Use of the phase to correct large frequency offsets greatly extends the acquisition range required for low cost analog components.

Abstract: Systems and techniques are disclosed for establishing a reference corresponding to the timing of a received signal from the first source, determining the timing for each received signal from a plurality of second sources, adjusting the reference to the timing of the received signal from one of the second sources, the timing of the received signal used to adjust the reference being closest in time to the unadjusted reference, and synchronizing a signal to the reference for transmission. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A memory interface for a switching router in a network communications system. The interface operates at 200 MHz PLL clock using high speed transistor logic I/O buffers. The interface allows transfer of clock synchronization signals along with the data signals. This allows the setup/hold times to be optimized for an inbound or outbound data pipeline. During writes, data is at least driven one clock cycle after the address. The interface provides flexibility by utilizing at least two clock cycles in order to accommodate a myriad of memory devices (e.g., burst mode SSRAMs having HSTL I/O). In operation, most of the data transfers through the interface are either direct reads or lookup reads. The interface stores writes are stored in a buffer in order to reduce bus turn around penalties.

Abstract: Synchronization of a powerline modem network (10) with a plurality of devices is provided. A plurality of devices (16 and 18) each include a powerline modem (20) and a clock circuit (22) for synchronizing a data rate. The powerline modem permits data transmission between the plurality of devices over a powerline network on data carriers (28). A synchronization signal is transmitted over the powerline network. The synchronization signal includes a carrier (30) operating at a frequency different from the data carriers. The synchronization signal provides each of the plurality of devices a time reference to synchronize the data rate.

Abstract: A method for switching between multiple clock signals in a digital circuit is provided that includes providing to a clock selector at least three distinct clock signals for the circuit. A master clock signal for the circuit is generated with the clock selector based on a first one of the distinct clock signals. The master clock signal is asynchronously blocked. The master clock signal for the circuit is generated with the clock selector based on a second one of the distinct clock signals. The master clock signal is synchronously unblocked.

Abstract: A system and method is provided for synchronizing time of day information between and among communication adapters. Time of day information, which is desired for proper message packet ordering and delivery, is recovered in a process in which a master adapter, connected to a master node, periodically broadcasts current time of day information to slave adapters which operate to determine whether or not drift correction is to be applied.

Abstract: A digital data network uses network nodes incorporating infrared transceivers. Each node includes a plurality of infrared transceivers having transmitter and receiver optics designed to facilitate line-of-sight infrared optical communications in a residential or business neighborhood. New nodes are installed with at least one selected transceiver having line-of-sight access to at least one existing transceiver. Automated tracking and acquisition processes are used to align transceivers to enable data communication and to acquire newly installed nodes into the network.

Abstract: The generation and upstream transmission of voice packets in an HFC network is controlled by including a synchronization circuit in the broadband terminal interface unit. The synchronization circuit is used to generate the timing signals for the codec, DSP and host microprocessor so that as the host microprocessor receives an upstream grant, the remaining components will assemble and forward the packets in synchronization with the grant.

Abstract: A method and apparatus are provided that allows a coarse timing approximation to be determined from analyzing only a portion of a received burst. The coarse timing can be refined by focusing on the coarse timing approximation. According to one aspect of the present invention, the invention includes receiving a burst having a known repeating core training sequence, selecting an analysis window to be substantially the same size as a multiple of a single repetition of the core training sequence, and over sampling the received burst for the portion overlapping the analysis window.

Abstract: An exciter (10) is located along an information stream path of a transmission system (12). The exciter (10) supplies an information signal as a drive to an amplifying arrangement (14). A coder (28), programmable to be operative in any of several I/O formats, outputs the information signal that conveys data in a desired code arrangement. A filter (30), programmable to be operative in any of several I/O formats, confines the information signal energy to a predetermined channel bandwidth. A modulator (32), programmable to be operative in any of several I/O formats, modulating the information signal. A corrector/equalizer (34), programmable to be operative in any of several I/O formats, pre-corrects the modulated signal for errors induced in the transmission system. A controller (38) provides program control of the coder (28), the filter (30), the modulator (32), and the corrector/equalizer (34). Thus, the exciter (10) is configurable to handle several formats, such as MPEG2, DVIDEO, and AES3.

Abstract: There is no common clock between two system over an asynchronous interface, such as an asynchronous network or bus. The rate of data transmission of constant bit rate data from one system can be considered constant when averaged over time. A receive system can synchronize its system clock by using timing information derived by counting received packets over a predetermined period of time.

Abstract: A first base station, which is coupled to a first switching system part is set up within radio range of a second base station, which is coupled to a second switching system part. After initial synchronization of the first base station to the first switching system part and of the second base station to the second switching system part, the second base station receives radio frames transmitted from the first base station and determines their time error with respect to its own radio frame clock. The determined time error is then transmitted to the second switching system part. In response to this, the second switching system part transmits a synchronization signal to the second base station, with the transmission time being chosen as a function of the transmitted time error such that the radio frame clock of the second base station is synchronized with the radio frames of the first base station by time alignment with the synchronization signal.

Abstract: An apparatus for reproducing a system clock provided with a reproducing unit for reproducing a first time reference clock T1, a generating unit for generating a system clock Sck, a generating unit for generating a second time reference clock T2, a synchronization control unit for minimizing, based on the clocks T1 and T2, the deviation between these clocks, a first calculating unit for calculating a difference between counts of the clock T1 counted in a predetermined time interval, and a second calculating unit for calculating a difference between counts of the clock T2 counted in a predetermined time interval, the outputs of the calculation of the differences being input to the synchronization control unit to minimize the deviation between the clocks, whereby it becomes possible to reproduce high quality data even when switching channels from one node to another node when reproducing digital data from a plurality of sending side nodes at a receiving side node.

Abstract: A system and method for distributing data in a system. The system comprises a control register logic circuits located at scattered locations in the system, where a location is defined as scattered if the propagation delay of data sent from the control register is more than approximately one clock period. The system also comprises one or more shift registers coupled to the control register and the logic circuits. A section of each shift register is placed in proximity to each logic circuit and data is shifted serially from the control register through the shift registers to the logic circuits. A synchronizer circuit is coupled to the shift registers to synchronize data arriving at each section of the shift registers with a shift control signal arriving at the same section of the shift register.

Abstract: When signals for two mobile stations PS-A and PS-B are multiplexed using path division, a clock generating unit 52 generates a clock signal so as to delay the timing for transmitting symbols to the mobile station PS-B by 0.5 symbol periods relative to the transmission of symbols to the mobile station PS-A. If the transmission timing is adjusted in this way, a mobile station that picks up symbols which are spatially multiplexed with the signal for the present mobile station but are intended for another mobile station will not be synchronized with the symbols for the other mobile station.

Abstract: The invention refers to a ranging system for determining ranging information of a spacecraft carrying a component of a communication channel. In order to provide a ranging system for determining ranging information of a satellite carrying a transponder as well as to provide a method thereof which yield a sufficient accuracy without causing further costs when narrow spot beams by the transponder are used, a ranging system according to the invention comprises a plurality of receiving stations at different locations on earth, wherein each receiving station is arranged for receiving a reference signal from said component; synchronisation means for providing a synchronised time base between the plurality of receiving stations; calculation means for calculating said ranging information in accordance with the propagation time of each received reference signal and with the synchronised time base; wherein at least one receiving station comprises a correlation receiver for receiving the reference signal.