Abstract: The invention refers to a ranging system for determining ranging information of a spacecraft carrying a component of a communication channel. In order to provide a ranging system for determining ranging information of a satellite carrying a transponder as well as to provide a method thereof which yield a sufficient accuracy without causing further costs when narrow spot beams by the transponder are used, a ranging system according to the invention comprises a plurality of receiving stations at different locations on earth, wherein each receiving station is arranged for receiving a reference signal from said component; synchronisation means for providing a synchronised time base between the plurality of receiving stations; calculation means for calculating said ranging information in accordance with the propagation time of each received reference signal and with the synchronised time base; wherein at least one receiving station comprises a correlation receiver for receiving the reference signal.

Abstract: Methods include receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal.

Abstract: A communication system is provided for interconnecting a network of digital systems. The communication system includes a communication line and a transceiver placed between the communication line and each digital system. The transceiver includes a receiver which can be selectively powered down whenever activity within the communication line ceases. The external conductors extending from each transceiver integrated circuit to an associated digital system are minimal, and the status of a clock/status signal conductor will indicate if the digital system is in a low power state (no clocking signal) or whether the digital system will be in a normal or protected clocking state. When a communication system is initially started, activity within the communication line will not lock the recovery circuits of the transceiver and, therefore, the transceiver will forward the received signal back out the transceiver without causing that signal to enter the associated digital system.

Abstract: Conventional networks, for example, a network of microprocessor controlled devices such as computer, printers, etc., have relied upon physical wire connections between each device on the network. Recently, however, has seen the emergence of wireless networks, in which the network connections are provided, typically, by a wireless radio link. One of these such networks is described in the Specification of the Bluetooth System v 1.0 B. However, synchronisation between independent wireless networks has some drawbacks which result in reduced bandwidth availability. The present invention aims to overcome these drawbacks.

Abstract: A method and apparatus for synchronizing with a network without connecting to the network by shadowing a slave device while a master device connects the slave device to the network. The master device maintains a system clock time. The master and slave devices exchange communication traffic during time slots on channels in a channel hopping sequence derived from the system clock time. The method and apparatus obtain a slave clock time in an inquiry response packet from a slave device when the master and slave devices are not connected in the network and then use the slave clock time for shadowing the slave device for receiving a master page frequency hop synchronization (FHS) packet having the system clock time.

Abstract: A communication device comprises reception means for receiving externally supplied first time information representing time, time information generation means for generating second time information representing time, time difference detection means for detecting a time difference between the times represented by the received first time information and the second time information generated at a time point at which the first time information is received, and correction means for correcting the second time information generated by said time information generation means based on the received first time information when the time difference is greater than a predetermined value.

Abstract: In one embodiment, the invention is directed to methods and system for converting an analog signal to digital samples for transmission over a communication network, and for converting digital samples received over a communication network to an analog signal. According to one feature, the system of the invention generates encoding and decoding master clocks from local oscillators, thus enabling the system of the invention to operate in environments where reliable timing signal are not available from the communication network. According to another feature, the system of the invention adjusts the frequencies of the encoding and decoding master clocks based on a connect rate to the communication network.

Abstract: An apparatus, method, communications device and computer readable medium for phase aligning two clocks and providing a graceful switch between active and standby circuitry is disclosed. A reporting circuit receives a measured phase difference between a first clock signal and a second clock signal, a selection circuit selects a configurable phase adjustment according to the measured phase difference, and a granularity adjustment circuit adds the configurable phase adjustment to the first clock signal generating a phase adjusted clock signal. The measured phase difference is compared to a maximum allowable phase difference value such that a phase adjustment is added to the first clock signal if the measured phase difference is greater than the maximum allowable phase difference value. The process is repeated until the measured phase difference is not greater than the maximum allowable phase difference value.

Abstract: A protocol management system is capable of detecting certain message protocols and applying policy rules to the detected message protocols that prevent intrusion, or abuse, of a network's resources. In one aspect, a protocol message gateway is configured to apply policy rules to high level message protocols, such as those that reside at layer 7 of the ISO protocol stack.

Abstract: SYNC parsing for Cable Modem Clock Synchronization is implemented using software processing with hardware assist in a manner that achieves the cost benefits of software SYNC parsing with the time accuracy of hardware SYNC parsing. Hardware scans for the arrival of new MPEG frames. Whenever any MPEG frame arrives, the MPEG frame is processed to extract MAC packets. If a SYNC packet is discovered during this processing, the software determines the SYNC arrival time, a comparison is made between the time the SYNC arrival time and the SYNC time value, and the software uses the difference to adjust the Cable Modem clock. Implementation variations include different approaches to when timestamps are recorded, the calculation of the SYNC arrival time, the use of software to process the MPEG frame and MAC packets, and the use of software to perform the time comparison.

Abstract: The synchronous digital communications system according to the invention serves to transmit electric signals optically. The electric signals to be transmitted are converted from electrical to optical form (E/O1, E/O2, E/On) and then transmitted using wavelength division multiplexing (WDM) or dense wavelength division multiplexing (DWDM). A synchronization manager and a connection manager are provided. The synchronization manager is adapted to configure dedicated optical synchronization links. The connection manager is adapted to configure switched optical communication links from a pool of wavelengths, taking account of the dedicated synchronization links only. This has the advantage that independently of the switched communication links, synchronization is constantly ensured throughout the system. Each network element (NE1, NE2, NE3) has at least one interface unit that is reserved for synchronization and that continuously receives signals at the wavelength (&lgr;1) reserved for synchronization.

Abstract: The synchronous digital communications system according to the invention serves to transmit electric signals optically. The electric signals to be transmitted are converted from electrical to optical form (E/O1, E/O2, E/On) and are transmitted using wavelength division multiplexing (WDM) or dense wavelength division multiplexing (DWDM). At least one optical connection is configured as a nonswitched connection using at least one wavelength per transmission section between optical network elements or optical and electrical network elements, and serves to transmit synchronization and information signals. This has the advantage that independently of the switched communication links, synchronization is constantly ensured throughout the network. Each network element (NE1, NE2, NE3) has at least one interface unit that is reserved for synchronization and that continuously receives signals at the wavelength (&lgr;1) reserved for synchronization.

Abstract: An arrangement for synchronization of nodes in VDSL-systems, or more exactly, synchronization of optical VDSL-nodes which share a common part of a cable in the access network between subscribers and a local station. A time synchronization is provided towards an external system, for instance GPS, which gives a time reference by which the different nodes can be synchronized. The synchronization reduces the near end cross-talk between the VDSL-systems in the different nodes. Preferably, each respective node includes a receiver for a synchronization signal and an internal oscillator with high stability to deliver a stable clock signal.

Abstract: A method and apparatus for synchronizing with communication traffic in a BLUETOOTH network without joining the network. The apparatus transmits an inquiry signal and receives an inquiry response signal having a coarse system clock time. The apparatus uses the coarse system clock time for estimating an initial channel in a channel hopping sequence then advances channels through the sequence in steps of four or more for scan window time periods of four or more time slot periods until a communication traffic signal is recognized. The time-of-arrival of the traffic signal is used for refining the coarse system clock time in order to acquire the exact system clock time. The exact system clock time is used by the analyzer for deriving the channels and timing of the sequence for synchronizing to subsequent communication traffic signals.

Abstract: A method of synchronizing each local clock to a master clock in a data bus system is described. In an embodiment, the data bus system includes a plurality of nodes each having a local clock. Initially, a clock source for each local clock is the respective local clock generator of each node. During formation of a data bus configuration for the data bus system, each node assigns either a first identifier or a second identifier to each port that is coupled to another port. If a node has a first identifier port, the node changes a clock source for its local clock from the local clock generator to a particular clock recovery circuit that is coupled to the first identifier port. In another embodiment, a clock source for each local clock is initially the respective multiple mode clock recovery circuit (MMCRC) operating in the unlocked mode.

Abstract: The invention relates to a wireless network which includes a plurality of network nodes, each of which includes a radio device with a respective radio clock supply and is arranged to exchange data via a wireless medium, and also includes a user interface for the exchange of data between the associated radio device and at least one user. At least one user of a network node receives a user clock, being independent of the radio clock, from a user clock supply of the relevant network node. Each network node is arranged to determine, in response to events specified by a central network node, a time value related to the relevant application clock. The central network node transmits at least the last time value formed by a selected network node.

Abstract: A method of transmitting clock signals (CS) in a synchronous digital communications network and a method of synchronizing clock generators (SSU) or network elements (SEC) wherein signaling of the clock quality is effected by phase-modulating the clock signal (CS). The clock signal (CS) is transmitted and received through simple clock interfaces (T4, CLO; T3, CLI) and contains a phase modulation characteristic of the clock quality. The phase modulation is detected and quality information is derived therefrom. Based on the quality information, the clock generator (SSU) or the network element (SEC) are synchronized to the clock signal. Also disclosed are a clock generator (SSU) and a network element (SEC; NE) for carrying out the two methods.

Abstract: A main-remote radio base station system includes plural remote radio units each having a remote digital interface unit and a main unit having a main digital interface unit. Different length links couple different remote radio units to the main unit. The digital interfaces in the main and remote units include a digital data channel and a digital timing channel. A delay associated with each link is determined without interrupting transmission of data over the digital data channel. The delays, reported continuously, periodically, or upon request, are compensated for and equalized by advancing a time when the timing and data signals are sent over their respective digital channels. In a preferred embodiment, the interface is a digital optical interface. A hybrid base station includes synchronized “near” and “remote” radio units.

Abstract: The present invention relates to a quasi-synchronous multi-stage event synchronization apparatus by a phase lock loop (PLL) control circuit and a quasi-synchronous multi-stage synchronizer to tolerate clock uncertainty and speed up the synchronizing process between the asynchronous digital circuits from producing-end to consuming-end in the computer system. The phase lock loop (PLL) control circuit generates a pair of well-controlled clocks, PDU_CLK, CSM_CLK, assigned to producing-end and consuming-end and a pair of clock phase indicating signals, PDU_SYNC_PULSE, CSM_SYNC_PULSE, associated with the pair of well-controlled clocks. The quasi-synchronous multi-stage synchronizer routes the series of sync events into a synchronization stage with minimal synchronization delay from producing-end to consuming-end.

Abstract: A wireless digital telephone system containing at least one emulated base station plus one or more subscriber stations, the emulated base station comprising a station similar to the subscriber station but having the capability of initiating a synchronization process whereby it is enabled to assign time slots to the subscriber station within the frame pattern of an amplitude signal by means of monitoring for positive edges in the signal.

Abstract: A method and apparatus for providing frame acquisition and synchronization for ATM transmissions in terrestrial wireless and satellite systems. During acquisition (1020), the transmitter (15) fills the entire payload of a frame with a pattern that is used by the receiver (18) to determine the location of the frame boundary. As to synchronization (1020), a procedure is utilized for using frame sequence number field in the header and Reed-Solomon decoding result (1012) for correction and maintaining frame synchronization.

Abstract: A wireless local area network apparatus includes a transmitter and a receiver in which operation of the receiver is accurately synchronized with periodic signals from the transmitter. The periodic signals contain timing data indicating the state of a timer in the transmitter at the time the signal containing that data was transmitted and this timing data is retrieved from the signal when received by the receiver and loaded in a timer for controlling operation of the receiver.

Abstract: A network element is provided for receiving receives message signals and reading the synchronization status messages contained therein. The network element transmits the message signals to a central network management facility which selects one of the message signals as a timing reference based on the synchronization status messages and based on stored information about the structure and configuration of the network. The network management facility then notifies the network element of the selection. The network element derives a clock signal from the selected message signal and uses this clock signal to adjust an internal clock generator. Because the network management facility also has information about parallel transmission paths, the creation of timing loops is effectively prevented.

Abstract: A smart different prime code multiplexing system. Using the characteristic that two different prime codes do not interfere with each other, these two prime codes are combined to replace the conventional asynchronous division multiple access. Without affecting the user and the original data, in the original optical fiber transmission system, other users or data are dynamically added to improve the insufficient capacity of the prime code system. The decoding capacity is thus raised to achieve the objective of multiple access. Furthermore, in the invention, a synchronous parallel prime code is used to increase the original asynchronous decoding capacity. Therefore, a decoding capacity in the asynchronous system similar to that of the synchronous system is obtained. Characteristics such as ultra-high capacity and ultra-high operating speed can also be achieved.

Abstract: A communication system in which normal communications can be ensured even upon a loss of synchronization on a part of transmission paths configuring a network.

Abstract: A system and method for minimizing the frequency error of satellite modem signals at a satellite gateway. The gateway downstream baud (symbol) clock and the elements that control the upstream frequency (i.e., local oscillators in the conversion chain, A/D sample clocks) are locked to a common frequency reference. The gateway sends upstream satellite frequency offset information, such as satellite ephemeris data from which to calculate Doppler offset, to the satellite modem. The satellite modem locks the frequency of the satellite modems master oscillator to the recovered baud rate using a frequency locked loop. The satellite modem uses its master oscillator as the carrier reference for the upstream frequency up conversion. The satellite modem uses or calculates the upstream satellite frequency offset and compensates for this offset by shifting its center frequency.

Abstract: A communication system, source and destination ports of the communication system, and methodology is provided for transporting data in one of possibly three different ways. Data is transported across the network at a frame sample rate that can be the same as or different from the sample rate or master clock within the source port or the destination port. If the sample rate of the source port is known, the sample rate of the destination port can be created using a PLL within the destination port and simply employing a phase comparator in the source port. The phase comparator forwards the phase or frequency difference of the network transfer rate and the source sample rate to the destination port, which then generates a local clock equivalent to the source which then compiles audio data being played at the same rate in which it was sampled at the source. Where economically feasible, sample rate conversion can be used at the source.

Abstract: A method for synchronizing a time architecture of a mobile network that includes a plurality of network components, each having a time subsystem clock that is updated using a network time protocol (NTP) program. The method includes operating the components in a hierarchical fashion and booting up all the network components such that execution of a NTP sub-program for making small incremental changes to the each component time subsystem clock is delayed. Additionally, the method includes iteratively executing a NTP sub-program for making large changes to each component time system clock until each component time sub-system clock establishes an initial synchronization with a parent component time sub-system clock. Furthermore, the method includes iteratively executing the NTP sub-program for making small incremental changes once initial synchronization is established such that each component time sub-system clock maintains synchronization with the parent component time sub-system clock.

Abstract: A phase lock loop (PLL) clock generator with programmable frequency and skew is provided in the present invention, in which frequency of clock signals generated can be dynamically changed and skew of the clock signals generated can be dynamically adjusted by a computer program. Also, the signal skew due to the change of loading can be compensated. Therefore, the PLL clock generator based on a closed-loop configuration can better control the skew of clock signals to provide higher stability and durability to the system.

Abstract: A system and method in a communication device (10) uses timing tracking to correct timing drifting due to the difference in frequency of a transmitter clock and a receiver clock. With the timing tracking, correlation values of three consecutive samples are calculated using the receive signal and the recovered symbols and then summed. A timing signal, (nk, frack) is updated based upon a metric calculated from a previous correlation value, R−1, present correlation value (R0) and a next con-elation value (R+1). Adjustment of timing signal is based on the relative location with respect to the current timing of a peak of a second order polynomial curve formed by the first correlation value R−1, the second correlation value Ro and the third correlation value R+1.

Abstract: Like a conventional one-way pager system, a two-way pager system is provided in which a message is received by paging from a base station and a message responding to the received message is returned to the base station. In this system, direct communication and peer-to-peer communication between terminals are performed. All the terminals included in the service area of the base station are always synchronized with sync signals paged from the base station. No special infrastructure is therefore required for synchronizing the terminals with the sync signals to perform the peer-to-peer communication. Furthermore, since each of the terminals receives a paging signal during the peer-to-peer communication, it can respond to a paging call.

Abstract: A wireless communication apparatus which performs communication control on wireless communication apparatuses in a predetermined cell of a predetermined range. When information on synchronization transmitted from a wireless communication apparatus in the adjacent cell has been received, frame/communication synchronization is established with respect to the adjacent cell, and communication control is performed in the predetermined cell, based on the information. Upon transmitting information for synchronization to the wireless communication apparatuses in the cell, the information is sent in a time slot, different from a time slot used for receiving the synchronizing information from the wireless communication apparatus in the adjacent cell, in the same communication frame.

Abstract: A distributed system with mechanisms for automatic selection of master and slave clocks to be used for clock synchronization. The distributed system includes a set of nodes, including a first node and a second node, each having a local clock and a set of information pertaining to the local clock. The first node transfers a packet on a communication link that carries the information. The second node receives the packet on the communication link and determines whether the local clock of the second node is a master clock that synchronizes a time value in the local clock of the first node or a slave clock that synchronizes to a time value from the local clock in the first node by comparing the information in the packet to the information pertaining to the local clock in the second node. Automatic selection of master and slave clocks in boundary nodes is provided along with mechanisms for determining clock synchronization delays and mechanisms for reporting jitter associated with communication devices.

Abstract: A synchronizer for providing a source-synchronized clock bus reduces the effect of clock skew during the signal capturing process. The synchronizer includes at least one capture latch in the capture clock domain for capturing the signal, at least one storage latch for storing the signal coupled to the at least one capture latch, and a multiplexer coupled to the at least one storage latch. The multiplexer synchronizes data transfer of the at least one storage latch and the at least one capture latch, and an internal latch in the internal clock domain. The signal is controlled and processed by strobe signals and clock signals from the sending chip.

Abstract: A digital circuit includes a plurality of arbiters, each arbiter having first and second input ports and an output port at which is provided an arbiter output signal. Each first input of the plurality of arbiters is connected to a first common line and each second input of the plurality of arbiters is connected to a second common line. The digital circuit further includes a decision circuit, having a plurality of inputs and an output, with each of the inputs of the decision circuit coupled to a corresponding one of the output of the plurality of arbiters. The decision circuit provides an output signal indicative of the time difference between a signal fed to the first common line and a signal fed to the second common line. With such an arrangement, phase jitter or timing jitter in a clock network can be measured with relatively high resolution and the system cam resolve cycle-by-cycle jitter with a predetermined resolution.

Abstract: A distributed system with an architecture based on synchronized clocks that provides accurate coordination of control functions. The distributed system includes a set of nodes coupled to a communication link. Each node has a clock which holds a real-world time. The nodes participate in a synchronization protocol on the communication link for synchronizing the real-world time in each clock. The architecture of the distributed system is such that the synchronization of control functionality in the distributed system is based upon the real-world time in the clocks. A variety of examples of applications for this architecture are set forth.

Abstract: A spread spectrum communication system includes at least one mobile station and a plurality of base stations for communicating with mobile stations in sites thereof by a spread spectrum scheme. Each base station includes an accumulation section and calculation section. The accumulation section accumulates a reception timing difference indicating the difference in reception timing between a transmission signal from a mobile station in a base station in an adjacent site and a transmission signal from the mobile station in a self-station. The calculation section obtains the reception timing of the transmission signal from the mobile station in the self-station by using the reception timing difference between the self-station and a handover source base station in an adjacent site, which is accumulated in the accumulation section, when the self-station become a handover destination base station upon handover of the mobile station between adjacent sites.

Abstract: A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

Abstract: A method employing multisignal encoded start pulses and end pulses for data transmission by use of radio waves, carries out encoding so that a very large number of kinds of patterns (not less than 1014 kinds are possible) can be effected with one frequency. In the binary system, encoding needs a large number of signal pulses and high frequency, and the frequency of the carrier wave becomes very high also. The multisignal method of this invention makes it possible to reduce the encoding bits and the carrier wave frequency by using level sensing and width comparison techniques. This method also removes noise owing to its level sensing and width comparison techniques which have not been used in conventional digital communication systems. Therefore, the reception of erroneous information, the occurrence of unclear audio-visual images, and noise trouble are prevented in the use of radio waves.

Abstract: The invention relates to a method of synchronizing a reference clock of a first ground station and a local clock of a remote system, in particular a satellite. It includes: a) acquisition in a first loop of synchronization between reference bursts received by the remote system and generated bursts synchronized with the local clock, b) detection of the recognition word of the reference bursts received by the first remote system and generation of a time window containing N pulses of the reference clock, c) acquisition of the average phase of said pulses and comparison with the phase of the local clock, and d) in a second loop, synchronization of the phase of the local clock with said average phase. The method can be reiterated to synchronize a second ground station with the first one via the remote system.

Abstract: A switch suitable for use in high-bandwidth environments is disclosed. The switch eliminates the need for inter-stage jitter compensation by determining the timing signals associated with each data input and then re-timing the data based upon the timing signals at the switch output. Bandwidth is conserved by routing timing signals through a multiplexer that preferably determines the difference between the timing signal and a reference signal, combines the difference signal with other difference signals calculated for other data inputs, and then transmits the multiplexed difference signals to a demultiplexer. Suitable multiplexing schemes include time division multiplexing, wavelength division multiplexing, code division multiple access (CDMA) multiplexing, as well as various combinations of suitable multiplexing methods.

Abstract: A communication system such as an OFDM or DMT system has nodes which are allowed to transmit continuously on one or just a few of the sysiem's frequency sub-channels, while the other nodes avoid putting any signal into those sub-channels. Simple low data rate nodes are allowed to use a small number of sub-channels while more complicated nodes use the remainder, and preferably functionality is provided to ensure that adjacent sub-channels are reliably spaced apart in frequency so that they do not bleed over into one another; to ensure that signals from all nodes arrive at the base station with well-aligned symbol transitions; and to ensure that signals from the various nodes arrive at the base station with similar power levels.

Abstract: A method of and apparatus for detecting drift between two clocks is presented. The apparatus comprises a hardware implementation of a clock drift evaluator. The evaluator monitors received packets associated with a data stream, and extracts a time stamp generated by a source clock from each packet. A difference d between the extracted time stamp and the local time is compared against a d_ref value to determine whether the packet was received early or late. On a prescribed schedule, the degree of late and early receipt of packets is compared against a tolerance level to determine whether a relative drift exists between the pacing of the source clock and the pacing of the local clock. The detection of drift between the two clocks provides support for service level guarantees in provisioning data streaming services in packet-switched environments.

Abstract: A method of synchronizing a base station and a remote station is presented. The base station is communicatively coupled with the remote station and a reference network. The base station clock signal is compared with a reference clock signal derived from the reference network and adjusted accordingly. The adjusted base station clock signal is then used to generate timing information in the form of a preamble, which is periodically transmitted from the base station over a wireless communication network to the remote station where a clock signal is generated. The remote station compares the clock signal with the timing information and adjusts the clock signal accordingly. This is done without reference to an external clock.

Abstract: A clock selection controller is shown which allows a user to assign a priority scheme to recovered clock signals obtained from communication facilities. The clock selection controller also receives a plurality of alarm signals corresponding to the communications facilities for each of the recovered clock signals. The clock selection controller then automatically selects, for output as a reference clock signal, the highest priority clock input available for which the corresponding alarm signals are inactive. In the absence of an available clock input in the priority scheme, the processor selects a free running clock input.

Abstract: Apparatus for synchronizing time-of-day events across a plurality of neighboring processing nodes organized in a distributed parallel processing system with each processing node including a time-of-day (TOD) incrementor. The TOD incrementor of each processing node is coupled to a local oscillator in the processing node running at a preselected frequency to increment locally the TOD incrementor. A controller determines one of the processing nodes as the master processing node by transmitting an initialization packet to the selected processing node, and transmits a set TOD service packet to the selected master processing node. The master processing node includes a broadcast generator that broadcasts TOD update packets to neighboring processing nodes. A register in the master processing node counts a multiple of the preselected frequency.

Abstract: In a clock management apparatus for a synchronous network system, when the quality of a clock signal is deteriorated, the clock signal is switched to another clock signal automatically to continue synchronous communication. Clock signals are received and extracted by transmission/receiving units of the synchronous network system. A plurality of clock signals including the extracted clock signals and a clock signal from an external clock are selectively switched by a clock switching unit, and a master clock signal is selected and output based on quality information transferred with each clock signal. The master clock signal is applied to a clock generator generate a clock signal. A quality control table is used to convert quality information into associated quality levels. A quality determination processing unit issues an alarm when the quality level of the master clock signal is deteriorated beyond a threshold provided by a synchronization management table.

Abstract: A synchronous digital communications network incorporating a number of nodes arranged in path protected rings and has two or more timing reference sources. The reference sources each allocated an artificial ranking of unique quality level values and these quality level values are transmitted as a section overhead message to provide a unique identifier for each source. Identification of the source to a node enables that node to be aware of a synchronization signal that has in fact originated from that node so as to prevent the setting up of synchronization loops. In a further embodiment the technique is extended to protection path identification for signals coupled between adjacent rings in a network having ring topology.

Abstract: A method and system of synchronizing two nodes of a network uses a demodulated output signal of a time division multiplex (TDM) demodulator to perform frequency and timing synchronization independently. Frequency synchronization is performed without using a program clock reference, by detecting a symbol timing loop error of the TDM demodulator. The error is filtered by an oscillator control loop filter if the error is within a predetermined range. Thus, an output voltage of a digital to analog converter that receives the filtered output controls an oscillator. In the timing synchronizer, an error between a program clock reference (PCR) and a value of a counter in the terminal is computed if the PCR is a not a first PCR, and the error is filtered with a timing loop control filter. A processor then adjusts a value of the counter in the terminal based on the filtered output.

Abstract: A receiver includes clock termination circuitry that is capable of applying either a terminating impedance or a high impedance to a transmission path that carries a clock signal. When multiple of these receivers are used to service data links that share a clock signal, one of the clock termination circuits applies the terminating impedance to the transmission path that carries the clock signal while the other clock termination circuit(s) applies a high impedance to the transmission path. The receiver also includes a plurality of high rate serial bit stream buffers and a clock signal buffer along with the clock termination circuitry. In other embodiments, the receiver includes a deserializer and may include a controller. The receiver may service a dual link Digital Visual Interface.