Abstract: A frequency detector includes an error measurement unit measuring a time interval between zero-crossing points of an input signal that is modulated. An error conversion unit quantizes the measured time interval using one of modulation time intervals. An error calculation unit calculates a frequency error based upon a difference between the measured time interval and the quantized time interval. An error generation control unit controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.

Abstract: Methods and apparatus are provided for requesting uplink Bandwidth (BW) over a BW Request (REQ) channel in an Orthogonal Frequency Division Multiple Access (OFDMA) communication system. A BW REQ indicator is transmitted with a BW REQ message over the BW REQ channel from a Mobile Station (MS) to a Base Station (BS) to request an uplink resource for uplink traffic of a delay sensitive service. A grant of the requested uplink resource is received from the BS in accordance with the transmitted BW REQ indicator and the BW REQ message. The uplink traffic is transmitted from the MS to the BS using the granted uplink resource.

Abstract: A circuit for performing clock recovery according to a received digital signal (30). The circuit includes at least an edge sampler (105) and a data sampler (145) for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock (25) and data clock (20) signals offset in phase from one another to the respective clock inputs of the edge sampler (105) and the data sampler (145). The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

Abstract: In a method and a device for decoding a signal, the signal is transmitted via at least one connecting line of a data transmission system, in a user of the data transmission system receiving the signal. It is provided to measure the interval of a change—provided compulsorily in a transmission protocol used in the data transmission system—of the signal from rising to falling or from falling to rising edge. A tendency for an asymmetrical delay of the signal can be ascertained from the measured interval. The sampling of the bits of the received signal can be improved as a function of the interval or of the asymmetrical delay, for example, by setting the sampling instant in variable fashion. Alternatively, the interval or the asymmetrical delay can be utilized for diagnostic purposes.

Abstract: A method is described for extracting selected time information from a stream of serialized AES digital audio data. A first transition indicative of a first preamble of said stream of serialized AES digital audio data is detected and, upon detection of the transition, a time count initiated. A second transition indicative of a subsequent preamble of said serialized AES digital audio data is subsequently detected and the time count halted. The time separating the first and second transitions is then determined. The separation time, which preferably is determined in the form of a fast clock pulse count, is then transferred to a decoding logic circuit for use in decoding the stream of serialized AES digital audio data.

Abstract: A clock regeneration circuit according to the present invention that generates a clock signal that is synchronized to an input signal, includes: a detection section which detects points at which the input signal transitions; a histogram generation section which associates a plurality of partial periods with the transition points, and generates a first histogram indicating an incidence of the transition points for each of the partial periods, the partial periods being generated by dividing a reference period of the clock signal; a calculation processing section which generates a second histogram by calculation processing based on the first histogram, and calculates a phase adjustment value of the clock signal based on the second histogram; and a phase adjustment section which adjusts a phase of the clock signal based on the phase adjustment value.

Abstract: A comparison period determiner (110) detects whether or not a change occurs in received data during a comparison period including a timing at which a rising edge of a reference clock occurs. A phase determiner (120) determines whether a rising edge of the received data is located before or after the reference clock and determines whether a falling edge of the received data is located before or after the reference clock, and outputs a first determination signal and a second determination signal indicating results of the respective determinations. A synchronous data generator (130) outputs a signal having a level depending on a result of the detection by the comparison period determiner (110) and an output of the phase determiner (120), as synchronous data, in synchronization with a synchronization clock.

Abstract: A signal reception device is disclosed that is capable of detecting symbol synchronization timing with high precision in accordance with a condition of a propagation path even in an environment involving multi-path interference. The signal reception device adopts an OFCDM transmission scheme or a multi-carrier transmission scheme. The signal reception device includes a received signal information calculation unit to calculate received signal information representing a signal reception condition of a received signal; an output combination unit to combine correlation values in a predetermined section obtained by correlation detection based on the received signal information; and a symbol timing detection unit to detect a symbol synchronization timing based on the combined value.

Abstract: An apparatus for recovering data and a method thereof are provided. The apparatus includes a reference clock generator which generates a reference clock, and a data recovering unit which detects an edge of received data and recovers the data using a time difference between a reference point of the reference clock and the detected edge.

Abstract: A data recovery circuit includes a pulse width indicator circuit, an edge detection circuit and a first storage. The pulse width indicator circuit is configured to receive, at an input, a data stream and provide pulses, at respective outputs, that are indicative of respective data bits in the received data stream. The edge detection circuit is configured to receive, on respective inputs, the pulses from the pulse width indicator circuit and provide respective storage signals, on respective outputs that are indicative of a logic level of the respective data bits, responsive to the pulses. The first storage is configured to receive and store the respective storage signals.

Abstract: A disclosed data processing apparatus includes: a binarization unit binarizing input data based on a threshold voltage; a capture unit capturing data from a binary output binarized by the binarization unit; a duty cycle detection unit detecting a duty cycle of the binary output; and a control unit controlling a level of the input data based on the duty cycle detected by the duty cycle detection unit.

Abstract: The present invention relates to a phase detector circuit (10) having an RF distribution device (20) which is intended to receive two sinusoidal high-frequency signals (RF, LO) with an input phase difference (?RF(t)??LO(t)) and comprises two power splitters (21, 22) in order to split the two high-frequency signals (RF, LO) into two respective parts, a self-calibrating phase detector module (30) which is configured to receive one respective part of the two high-frequency signals which have been split, a low-noise phase detector module (40) which is configured to receive the respective other part of the high-frequency signals which have been split, and a complementary filter device (50) which is configured to receive the output signals from the self-calibrating phase detector module (30) and the low-noise phase detector module (40) and to output a signal which indicates the time-dependent input phase difference between the two high-frequency signals (RF, LO).

Abstract: A beamforming system that can be used for both receive and transmit beamforming is provided. The system receives samples of a number of signals, each sample containing a band of frequencies and routes all sampled signals associated with the same beamformed frequency band to a predetermined processing block. A predetermined number of the routed sampled signals are selected sequentially according to predetermined criteria, weighted and accumulated to form a composite signal. Individual signals are then selected from the composite signal and routed to an appropriate output. The system uses a much smaller number of weighting functions than conventionally required, with processing for a single frequency being performed in the same processing block. This reduces the complexity of beamforming processing substantially and simplifies frequency reuse. In addition a single DSP design that works for both transmit and receive beamforming can be implemented.

Abstract: In one aspect, a wireless communication device includes an antenna configured to receive electromagnetic energy corresponding to a wireless communication signal outputted using an interrogator and to output electrical energy corresponding to the received electromagnetic energy, communication circuitry coupled with the antenna and configured to sample the electrical energy to process the wireless communication signal, synchronization circuitry coupled with the antenna and the communication circuitry and configured to generate a clock signal to control sampling of the electrical energy using the communication circuitry, wherein the synchronization circuitry is configured to generate a plurality of transitions within the clock signal responsive to a plurality of transitions of the electrical energy during a first data period and wherein the synchronization circuitry is configured to generate a plurality of transitions within the clock signal during a second data period including generating at least one of the tr

Abstract: Circuitry for decoding data from a pulsed signal received on a single line, the circuitry comprising receiving means for receiving a first edge and a second edge on the single line, the first and second edges being separated by a time period, the time period representing said data; decode circuitry comprising determining means arranged to determine a value of the time period and decoding means arranged to decode said data based on said determined value of the time period; a memory arranged to store a reference value; and calibration means for calibrating said decode circuitry based on a comparison between said determined value of the time period and said reference value, wherein the determining means comprises a plurality of sampling units for sampling said pulsed signal at different times, and selection means for selecting the output of one of said sampling units to decoded.

Abstract: A differential transmitter and an auto-adjustment method of data strobe thereof are provided. The differential transmitter includes a phase-detecting unit, a switching unit, a rising edge strobe unit, and a falling edge strobe unit. The phase-detecting unit detects a phase relation between a clock signal and a data signal to outputs a detection result. The rising edge strobe unit latches the data signal at a rising edge of the clock signal, and converts a latching result to a first differential output signal. The falling-edge-strobe unit latches the data signal at a falling edge of the clock signal, and converts a latching result to a second differential output signal. The switching unit determines whether to switch the clock signal and data signal to the rising edge strobe unit or to the falling edge strobe unit according to the detection result.

Abstract: An RF receiver comprises a signal processor arranged to perform a method of decoding data contained within a signal that comprises a set of slots, at least one said slot comprising a preamble portion and a payload portion and being transmitted at a predetermined transmission frequency. The signal processor is arranged to perform a first process to derive timing data from the preamble portion and perform a second process to extract information from the payload portion, the second process being triggered from said timing data derived from the first process. The preamble portion comprises at least a first sequence of data and a second sequence of data, and the second sequence is the inverse of the first sequence. In preferred embodiments the first process comprises identifying a transition between said first and second sequences of data and deriving said timing data from the identified transition.

Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.

Abstract: An input bit stream including a clock signal and data bits is oversampled to obtain one or more sets of data samples. One or more sets of non-transitioning phases corresponding to data samples that do not switch between zero and one are then identified. Center phases corresponding to the one or more sets of non-transitioning phases are identified and then a final center phase that accurately represents the bits belonging to the input bit stream is selected. The data samples corresponding to the final center phase are extracted, thereby recovering the clock signal and data bits from the input bit stream.

Abstract: The present invention relates to an apparatus and a method for receiving signal for extent of timing synchronization in MB-OFDM UWB System. The invention divides the digital samples completed of sampling twice as much as minimum sampling clock required to restore the MB-OFDM received signal into ODD data path and EVEN data path, executes the packet detection and timing synchronization for each of divided path and selects the data of path with larger cross correlation value at the timing synchronization point to secure the stable receiving performance in system environment with severe frequency offset and prevent the FTT window shift within preamble section through adding minimum hardware and structural change without increasing the system clock.

Abstract: There is provided a circuit constituted by small-sized and simple logical gates which reduces the bit errors generated in a data sequence received by a receiver. A transmission system, in which a data sequence is transferred, includes a transmitter that transmits a first transfer signal including an edge-present data waveform which has (i) a first timing edge indicating a timing to obtain data included in the data sequence and (ii) a level signal indicating a signal level corresponding to a value of the data, and a receiver that outputs the value of the data in accordance with the signal level which is detected at the timing indicated by the first timing edge of the edge-present data waveform.

Abstract: A time to digital converter is used to determine which edge of the higher frequency clock (oversampling clock) is farther away from the edge of the lower frequency timing signal. At the same time, the oversampling clock performs sampling of the timing signal by two registers: one on the rising edge and the other on the falling edge. Then, the register of “better quality” retiming, as determined by the fractional phase detector decision, is selected to provide the retimed output.

Abstract: A sampler circuit comprises a plurality of series-connected sampler cells and a detector circuit. Each successive stage comprises twice the number of sampler cells, in parallel, as the previous stage, and is clocked at half the sampling frequency of the previous stage. Each sampler cell comprises two parallel branches of series-connected clocked inverters. A clocked inverter is operative to invert an applied signal during one phase of an applied sampling clock, and to render a high impedance output during the other sampling clock phase. Successive clocked inverters are clocked with opposite (i.e., positive/negative) versions of the sampling clock. The detector circuit examines the outputs of the last stage of sampler cells, and may for example comprise an OR function to detect a state transition in an applied input signal. The sampler circuit exhibits immunity to metastability and low power consumption.

Abstract: Systems and methods of operating a serial interconnect interface provide for generating a pulse in response to a state change in a data signal of the serial interface interconnect, and transmitting the pulse from a physical layer of the serial interconnect interface to a link layer of the serial interconnect interface. The duration of the pulse can be selected based on whether the state change corresponds to an end of packet (EOP) condition. In addition, the data signal may include a non return to zero invert (NRZI) encoded signal, wherein the pulse is part of a digital NRZI signal.

Abstract: A high speed transceiver without using an external clock signal and a communication method used by the high speed transceiver which applies a clock recovery circuit including a coarse code generator, a frequency detector, and a linear phase detector to the receiver so as to solve problems such as skew between a reference clock and data that may occur during data transmission and jitter of a recovered clock while an embedded clock method of applying clock information to data is used.

Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.

Abstract: A hybrid high-definition encoder and method are disclosed, for processing signal data as a plurality of block transform coefficients for each of base layer data and enhancement layer data, where the encoder includes a two-layer decomposition unit for decomposing an original high-definition signal data sequence into base layer data and enhancement layer data, a standard-definition encoder coupled to the decomposition unit for encoding the base layer data as a base layer bitstream embodying a standard-definition data sequence, and a high-definition encoder coupled to the decomposition unit and the standard-definition encoder for encoding only the difference between the high-definition data and the standard-definition data as base layer picture user data embodying a high-definition data sequence.

Abstract: A data clock frequency divider circuit includes a training decoder and a frequency divider. The training decoder outputs a clock alignment training signal, which is indicative of the start of a clock alignment training, in response to a command and an address of a mode register set. The frequency divider, which is reset in response to an output of the training decoder, receives an internal data clock to divide a frequency of the internal data clock in half. The data clock frequency divider circuit secures a sufficient operating margin so that a data clock and a system clock are aligned within a pre-set clock training operation time by resetting the data clock to correspond to a timing in which the clock training operation starts, thereby providing a clock training for a high-speed system.

Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

Abstract: A method and apparatus for processing a radio frequency (RF) signal is provided. The method includes generating a periodic square wave local oscillator (LO) signal of a first phase, a periodic square wave LO signal of a second phase, and a chopping signal. The method further includes coding the periodic square wave LO signal of the first phase and the periodic square wave LO signal of the second phase synchronously with the chopping signal to generate a first set of synchronized signals (116, 118) and a second set of synchronized signals (120, 122), respectively. A phase difference between the first phase and the second phase is a predefined value. The RF signal is processed with the first set of synchronized signals (116, 118) and the second set of synchronized signals (120, 122) to obtain an in-phase intermediate frequency (IF) signal (132) and a quadrature-phase IF signal (142), respectively.

Abstract: A guard section length detection method detects whether a preamble signal is received. A short preamble boundary is then detected, then detecting a frame boundary and detecting a guard section length. In the step of detecting the guard section length a second matched filter capable of processing 128 point data sets is detected. Four different 128 point data sets have a distance of 8 points, 16 points, 32 points, and 64 points respectively from the frame boundary to the second matched filter. Four signal correlation values are calculated for determining the guard section length.

Abstract: Methods and apparatus for gathering information about the eye of a high-speed serial data signal include sampling each bit of a repeating, multi-bit data pattern at several eye slice locations. For any given eye slice location, each bit in the data pattern is compared in voltage to a base line reference signal voltage to establish a reference value for that bit. Then the reference signal voltage is gradually increased while the voltage comparisons are repeated until for some bit a result of the comparing is different than the reference value for that bit. This establishes an upper value for the eye at the eye slice location. The reference signal voltage is then gradually decreased to similarly find a lower value for that eye slice.

Abstract: A synchronization method and related apparatus of an OFDM digital communication system are disclosed for determining a position of a synchronization byte in a received signal. The method includes extracting a transmission parameter signal (TPS) from the received signal, determining a symbol number and a frame number corresponding to a symbol according to the TPS, and determining the position of the synchronization byte according to the frame number and the symbol number.

Abstract: A method of operating a communication system comprises sending a frame by an access node to a wireless device where the frame comprises a packet. A counter is initialized and a timer for each frame is initiated. The method continues with the access node determining if a response associated with the packet is received before the expiration of the timer. If the response is received prior to the expiration of the timer, the counter and the timer are reset. If a response is not received prior to the expiration of the timer, the counter is incremented. Upon the counter meeting a criteria of a certain quantity of lost packets, the access node performs a synchronization process.

Abstract: A signal processing circuit detects a pulsative change point of an input signal and sets a phase point which is shifted by a predetermined phase difference from the detected pulsative change point of the input signal as the timing for sampling the input signal.

Abstract: Signal processing circuit including a demodulator that receives a receive signal with signal edges, and outputs a demodulated receive signal with transitions from a first level to a second level or vice versa at signal edges of the receive signal, wherein points of time of the transitions depend on the steepnesses of the signal edges. The circuit also includes an edge evaluator that receives the receive signal, and outputs an evaluation signal which includes information about the steepnesses of the signal edges. The circuit also includes a signal generator that receives the output of the demodulator, receives the output of the edge evaluator, and outputs a corrected demodulated receive signal with transitions whose points of time are set with regard to the points of time of the transitions of the demodulated receive signal based on the evaluation signal in order to reduce influences of different steepnesses of the signal edges.

Abstract: In one embodiment, a frequency correction (FC) burst is detected in a complex signal received by a mobile station of a GSM/EDGE wireless communications network by applying the complex signal to one or more correlation paths of a burst detector within the mobile station. Each correlation path generates a correlation signal by multiplying a copy of the complex signal by the complex conjugate of a delayed version of the complex signal and then applies a correlation filter to the correlation signal. A combined correlation signal is formed by combining the filtered correlation signals from the one or more correlation paths. Peak detection is applied to the combined correlation signal, where a detected peak corresponds to the occurrence of the burst in the complex input signal. The correlation filters are designed such that the peak in the combined correlation signal occurs prior to the end of the burst.

Abstract: This invention discloses a self-timing method for phase adjustment. An analog signal is digitized at a first and second phase with respect to the symbols comprised in an analog signal in order to obtain first and second quantized samples. Then a first counter out of a first plurality of counters is increased if said first quantized sample has a first digital value to which said first counter is associated. Moreover a second counter out of a second plurality of counters is increased if a second quantized sample has a second digital value to which the second counter is associated. Finally the sampling phase is adjusted based on the values of the counters of the first and second plurality of counters. Moreover a digitizing, self-timing circuit is disclosed.

Abstract: The present invention includes: a synchronous-word detecting unit receives a baseband received signal including a synchronous word and data for each frame, and detects whether or not the synchronous word is coincided with an expected value in the baseband received signal by using an N-(N is an integer of 2 or larger) phase sampling clock; a phase information retaining unit retains phase information accumulatively including results detected for a plurality of frames by the synchronous-word detecting unit, and determines a phase to be sampled on the basis of the retained phase information; a phase selecting unit selects and determines a phase of the sampling clock on the basis of determination by the phase information retaining unit; and a FIFO buffer samples the data from the baseband received signal, and outputs the sampled data.

Abstract: A clock/data recovery device 1 comprises a sampler 10, a detector 20, an offset determination part 30, a clock output part 40, and a DA converter 50. The phases of clock signals CK and CKX are adjusted so as to match with the phase of an input digital signal. An offset amount (±Voff) added in the sampler 10 is adjusted so as to match with a peak time of a data transition time distribution of a first signal in a case where a value D(n?1) is HIGH level, and is adjusted so as to match with a peak time of a data transition time distribution of a second signal in a case where the value D(n?1) is LOW level. Either of the clock signals CK and CKX is outputted as the recovered clock signal. Time series data of a digital value D(n) is outputted as the recovered data.

Abstract: A deserializer including a plurality of registers, a sync detector, and a lost bit storage unit. If there is a phase difference between an external input data packet and a recovery clock signal transmitted together with the data packet, the sync detector generates an activated sync detect signal. The lost bit storage unit detects a data bit of the data packet corresponding to an activation point of the sync detect signal. The deserializer recovers the data packet by combining the detected data bit with the data packet.

Abstract: Control systems and methods for independent control of power systems, particularly lighting network branches, and separate control of individual branch components. Multi-branch systems comprise independently controllable branches that inter-communicate via PLC communications. In each branch, components such as ballasts, local control units, sensors, actuators, and repeaters, may exchange commands and queries independently of a branch remote control unit (BRCU). Alternatively, a BRCU may manage or arbitrate communications, or interact with other BRCUs, other control units and external management systems. Ballasts include a multi-channel ballast that enables close-loop control of individual fixtures, or of individual dimmable or non-dimmable lamps within a fixture. The close-loop control is facilitated by sampling circuits/sensors co-located with each controlled fixture or lamp. All controllers are preferably implemented using an integrated digital controller.

Abstract: Systems and methods for synchronizing an input signal with a substantial mitigation of race conditions and a substantial increase in resolving time are provided. One embodiment includes a system comprising a first latching device configured to latch a first output signal from the input signal and a delay element configured to receive the first output signal and output a delay signal that is a delayed version of the first output signal. The system also includes a pass-gate element configured to receive the first output signal and to output a second output signal in response to a logic state of the delay signal. The second output signal has a delayed input edge without a delayed resolving edge. The system can be configured to force the first output signal to a stable logic state in response to the first output signal having a metastable state.

Abstract: With the clock data restoration device 1, as a result of the processing of a loop which comprises the sampler section 10, detection section 20, timing determination section 30, and clock output section 40, the respective phases of the clock signal CKXA, clock signal CKXB, and clock signal CK are adjusted to match the phase of the input digital signal, the digital signal sampling time indicated by the clock signal CKXA is adjusted to match the peak time of the distribution of data transition times in a case where the value D (n?2) and value D(n?1) of the preceding two bits differ from one another, and the digital signal sampling time indicated by the clock signal CKXB is adjusted to match the peak time of the distribution of data transition times in a case where the value D (n?2) and value D(n?1) of the preceding two bits are equal to one another.

Abstract: Serial data communication methods and apparatus using a single line are provided. The data communication methods may include: setting a rising edge of a serial pulse signal so that a cycle of the serial pulse signal begins therefrom; setting a falling edge of the serial pulse signal within the cycle of the serial pulse signal according to a data value recorded within the cycle of the serial pulse signal; and transmitting a packet formed by combining at least one cycle of the serial pulse signal in series via a single line.

Abstract: A receiver in an impulse wireless communication. The receiver (300) includes a pulse-pair correlator (304) that receives a signal (316) and divides it into two signals for paths. One of the signals is input to signal multiplier (312) while another signal is delayed by a delay unit (310). The signal multiplier (312) multiplies the received signal (316) by a delayed signal (318). An integrator (314) integrates an output signal (322) over a designated period of time. An adding module (306) sums an output signal (324) from the integrator (314). An acquiring module (308) compares an summing-up output (326) from the adding module (306) with a predetermined threshold value to detect the existence of a transmitting-standard preamble.

Abstract: A clock embedded differential data receiving system for ternary lines differential signaling. The clock embedded differential data receiving system includes a monitoring portion which monitors voltage levels of first, second and third transfer signals to generate a clock signal, a first pre-data and a second pre-data, a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding of the first pre-data and the second pre-data, and a timing controller to delay the transition time point of the clock signal with a delay phase which generates the sampling control signal.

Abstract: A method for adjusting a serial data signal having multiple sets of bits includes the following steps. First, one set of bits in the serial data signal is over-sampled to generate a first set of over-sampled bits. Next, every adjacent two bits of the first set of over-sampled bits are compared to generate one set of edge bits. Then, a delay operation is determined according to the set of edge bits. Afterwards, a displacement operation is executed on next sets of bits in the serial data signal according to the delay operation.

Abstract: A decoder and related method adaptively generate a clock window. A falling edge of a horizontal synchronization signal is detected, and the time difference between an actual frame code and a predefined frame code is determined. The beginning and the end of the clock window are then adaptively determined based on the falling edge and the time difference, such that symbol timing recovery through received clock run-in signals may be performed within the generated clock window.

Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.