With Transition Detector Patents (Class 375/360)
  • Patent number: 8218703
    Abstract: In one aspect, a wireless communication device includes an antenna configured to receive electromagnetic energy corresponding to a wireless communication signal outputted using an interrogator and to output electrical energy corresponding to the received electromagnetic energy, communication circuitry coupled with the antenna and configured to sample the electrical energy to process the wireless communication signal, synchronization circuitry coupled with the antenna and the communication circuitry and configured to generate a clock signal to control sampling of the electrical energy using the communication circuitry, wherein the synchronization circuitry is configured to generate a plurality of transitions within the clock signal responsive to a plurality of transitions of the electrical energy during a first data period and wherein the synchronization circuitry is configured to generate a plurality of transitions within the clock signal during a second data period including generating at least one of the tr
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: July 10, 2012
    Assignee: Battelle Memorial Institute
    Inventors: Richard M. Pratt, Steven B. Thompson
  • Patent number: 8204159
    Abstract: Circuitry for decoding data from a pulsed signal received on a single line, the circuitry comprising receiving means for receiving a first edge and a second edge on the single line, the first and second edges being separated by a time period, the time period representing said data; decode circuitry comprising determining means arranged to determine a value of the time period and decoding means arranged to decode said data based on said determined value of the time period; a memory arranged to store a reference value; and calibration means for calibrating said decode circuitry based on a comparison between said determined value of the time period and said reference value, wherein the determining means comprises a plurality of sampling units for sampling said pulsed signal at different times, and selection means for selecting the output of one of said sampling units to decoded.
    Type: Grant
    Filed: November 25, 2006
    Date of Patent: June 19, 2012
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: Robert Warren
  • Patent number: 8189727
    Abstract: A differential transmitter and an auto-adjustment method of data strobe thereof are provided. The differential transmitter includes a phase-detecting unit, a switching unit, a rising edge strobe unit, and a falling edge strobe unit. The phase-detecting unit detects a phase relation between a clock signal and a data signal to outputs a detection result. The rising edge strobe unit latches the data signal at a rising edge of the clock signal, and converts a latching result to a first differential output signal. The falling-edge-strobe unit latches the data signal at a falling edge of the clock signal, and converts a latching result to a second differential output signal. The switching unit determines whether to switch the clock signal and data signal to the rising edge strobe unit or to the falling edge strobe unit according to the detection result.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: May 29, 2012
    Assignee: Novatek Microelectronics Corp.
    Inventor: An-Hsu Lee
  • Patent number: 8184748
    Abstract: An RF receiver comprises a signal processor arranged to perform a method of decoding data contained within a signal that comprises a set of slots, at least one said slot comprising a preamble portion and a payload portion and being transmitted at a predetermined transmission frequency. The signal processor is arranged to perform a first process to derive timing data from the preamble portion and perform a second process to extract information from the payload portion, the second process being triggered from said timing data derived from the first process. The preamble portion comprises at least a first sequence of data and a second sequence of data, and the second sequence is the inverse of the first sequence. In preferred embodiments the first process comprises identifying a transition between said first and second sequences of data and deriving said timing data from the identified transition.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: May 22, 2012
    Assignee: Plextek Limited
    Inventors: Peter David Massam, Philip Alan Bowden, Timothy David Howe, Timothy Jackson
  • Publication number: 20120121051
    Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
    Type: Application
    Filed: January 25, 2012
    Publication date: May 17, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Gregory Lee Christison
  • Patent number: 8180007
    Abstract: An input bit stream including a clock signal and data bits is oversampled to obtain one or more sets of data samples. One or more sets of non-transitioning phases corresponding to data samples that do not switch between zero and one are then identified. Center phases corresponding to the one or more sets of non-transitioning phases are identified and then a final center phase that accurately represents the bits belonging to the input bit stream is selected. The data samples corresponding to the final center phase are extracted, thereby recovering the clock signal and data bits from the input bit stream.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: May 15, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Asif Iqbal, Girraj K. Agrawal, Ankit Pal
  • Patent number: 8165254
    Abstract: The present invention relates to an apparatus and a method for receiving signal for extent of timing synchronization in MB-OFDM UWB System. The invention divides the digital samples completed of sampling twice as much as minimum sampling clock required to restore the MB-OFDM received signal into ODD data path and EVEN data path, executes the packet detection and timing synchronization for each of divided path and selects the data of path with larger cross correlation value at the timing synchronization point to secure the stable receiving performance in system environment with severe frequency offset and prevent the FTT window shift within preamble section through adding minimum hardware and structural change without increasing the system clock.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: April 24, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Cheol Ho Shin, Byoung Hak Kim, Sang Sung Choi, Kwang Rho Park
  • Patent number: 8155215
    Abstract: There is provided a circuit constituted by small-sized and simple logical gates which reduces the bit errors generated in a data sequence received by a receiver. A transmission system, in which a data sequence is transferred, includes a transmitter that transmits a first transfer signal including an edge-present data waveform which has (i) a first timing edge indicating a timing to obtain data included in the data sequence and (ii) a level signal indicating a signal level corresponding to a value of the data, and a receiver that outputs the value of the data in accordance with the signal level which is detected at the timing indicated by the first timing edge of the edge-present data waveform.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: April 10, 2012
    Assignee: Advantest Corporation
    Inventors: Kiyotaka Ichiyama, Masahiro Ishida
  • Patent number: 8155256
    Abstract: A time to digital converter is used to determine which edge of the higher frequency clock (oversampling clock) is farther away from the edge of the lower frequency timing signal. At the same time, the oversampling clock performs sampling of the timing signal by two registers: one on the rising edge and the other on the falling edge. Then, the register of “better quality” retiming, as determined by the fractional phase detector decision, is selected to provide the retimed output.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: April 10, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Robert B. Staszewski, Kenneth J. Maggio, Dirk D. Leipold
  • Publication number: 20120082280
    Abstract: A sampler circuit comprises a plurality of series-connected sampler cells and a detector circuit. Each successive stage comprises twice the number of sampler cells, in parallel, as the previous stage, and is clocked at half the sampling frequency of the previous stage. Each sampler cell comprises two parallel branches of series-connected clocked inverters. A clocked inverter is operative to invert an applied signal during one phase of an applied sampling clock, and to render a high impedance output during the other sampling clock phase. Successive clocked inverters are clocked with opposite (i.e., positive/negative) versions of the sampling clock. The detector circuit examines the outputs of the last stage of sampler cells, and may for example comprise an OR function to detect a state transition in an applied input signal. The sampler circuit exhibits immunity to metastability and low power consumption.
    Type: Application
    Filed: August 4, 2011
    Publication date: April 5, 2012
    Inventors: Paul Mateman, Johannes Petrus Antonius Frambach
  • Publication number: 20120076251
    Abstract: Systems and methods of operating a serial interconnect interface provide for generating a pulse in response to a state change in a data signal of the serial interface interconnect, and transmitting the pulse from a physical layer of the serial interconnect interface to a link layer of the serial interconnect interface. The duration of the pulse can be selected based on whether the state change corresponds to an end of packet (EOP) condition. In addition, the data signal may include a non return to zero invert (NRZI) encoded signal, wherein the pulse is part of a digital NRZI signal.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventors: Huimin Chen, Chunyu Zhang, Paul S. Durley
  • Patent number: 8135104
    Abstract: A high speed transceiver without using an external clock signal and a communication method used by the high speed transceiver which applies a clock recovery circuit including a coarse code generator, a frequency detector, and a linear phase detector to the receiver so as to solve problems such as skew between a reference clock and data that may occur during data transmission and jitter of a recovered clock while an embedded clock method of applying clock information to data is used.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: March 13, 2012
    Assignee: Korea University Industrial & Academic Collaboration Foundation
    Inventors: Chulwoo Kim, Inhwa Jung
  • Patent number: 8130889
    Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: March 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Gregory Lee Christison
  • Patent number: 8130890
    Abstract: A data clock frequency divider circuit includes a training decoder and a frequency divider. The training decoder outputs a clock alignment training signal, which is indicative of the start of a clock alignment training, in response to a command and an address of a mode register set. The frequency divider, which is reset in response to an output of the training decoder, receives an internal data clock to divide a frequency of the internal data clock in half. The data clock frequency divider circuit secures a sufficient operating margin so that a data clock and a system clock are aligned within a pre-set clock training operation time by resetting the data clock to correspond to a timing in which the clock training operation starts, thereby providing a clock training for a high-speed system.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: March 6, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyung-Hoon Kim, Yong-Ki Kim, Dae-Han Kwon, Taek-Sang Song
  • Patent number: 8130831
    Abstract: A hybrid high-definition encoder and method are disclosed, for processing signal data as a plurality of block transform coefficients for each of base layer data and enhancement layer data, where the encoder includes a two-layer decomposition unit for decomposing an original high-definition signal data sequence into base layer data and enhancement layer data, a standard-definition encoder coupled to the decomposition unit for encoding the base layer data as a base layer bitstream embodying a standard-definition data sequence, and a high-definition encoder coupled to the decomposition unit and the standard-definition encoder for encoding only the difference between the high-definition data and the standard-definition data as base layer picture user data embodying a high-definition data sequence.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: March 6, 2012
    Assignee: Thomson Licensing
    Inventors: Shu Lin, Mary Lafuze Comer
  • Patent number: 8126041
    Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: February 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: Brandon R. Kam, Stephen D. Wyatt
  • Patent number: 8121229
    Abstract: A guard section length detection method detects whether a preamble signal is received. A short preamble boundary is then detected, then detecting a frame boundary and detecting a guard section length. In the step of detecting the guard section length a second matched filter capable of processing 128 point data sets is detected. Four different 128 point data sets have a distance of 8 points, 16 points, 32 points, and 64 points respectively from the frame boundary to the second matched filter. Four signal correlation values are calculated for determining the guard section length.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: February 21, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Chun Kuo, Jen-Yuan Hsu, Chao-Kai Wen, Pang-An Ting
  • Patent number: 8121241
    Abstract: A method and apparatus for processing a radio frequency (RF) signal is provided. The method includes generating a periodic square wave local oscillator (LO) signal of a first phase, a periodic square wave LO signal of a second phase, and a chopping signal. The method further includes coding the periodic square wave LO signal of the first phase and the periodic square wave LO signal of the second phase synchronously with the chopping signal to generate a first set of synchronized signals (116, 118) and a second set of synchronized signals (120, 122), respectively. A phase difference between the first phase and the second phase is a predefined value. The RF signal is processed with the first set of synchronized signals (116, 118) and the second set of synchronized signals (120, 122) to obtain an in-phase intermediate frequency (IF) signal (132) and a quadrature-phase IF signal (142), respectively.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: February 21, 2012
    Assignee: Motorola Solutions, Inc.
    Inventors: Robert E. Stengel, Charles R. Ruelke, Sumit A. Talwalkar
  • Patent number: 8111784
    Abstract: Methods and apparatus for gathering information about the eye of a high-speed serial data signal include sampling each bit of a repeating, multi-bit data pattern at several eye slice locations. For any given eye slice location, each bit in the data pattern is compared in voltage to a base line reference signal voltage to establish a reference value for that bit. Then the reference signal voltage is gradually increased while the voltage comparisons are repeated until for some bit a result of the comparing is different than the reference value for that bit. This establishes an upper value for the eye at the eye slice location. The reference signal voltage is then gradually decreased to similarly find a lower value for that eye slice.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: February 7, 2012
    Assignee: Altera Corporation
    Inventors: Weiqi Ding, Mingde Pan, Wilson Wong, Sergey Shumarayev, Peng Li
  • Patent number: 8107576
    Abstract: A synchronization method and related apparatus of an OFDM digital communication system are disclosed for determining a position of a synchronization byte in a received signal. The method includes extracting a transmission parameter signal (TPS) from the received signal, determining a symbol number and a frame number corresponding to a symbol according to the TPS, and determining the position of the synchronization byte according to the frame number and the symbol number.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: January 31, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventor: Li-Ping Yang
  • Publication number: 20120014489
    Abstract: A method of operating a communication system comprises sending a frame by an access node to a wireless device where the frame comprises a packet. A counter is initialized and a timer for each frame is initiated. The method continues with the access node determining if a response associated with the packet is received before the expiration of the timer. If the response is received prior to the expiration of the timer, the counter and the timer are reset. If a response is not received prior to the expiration of the timer, the counter is incremented. Upon the counter meeting a criteria of a certain quantity of lost packets, the access node performs a synchronization process.
    Type: Application
    Filed: July 13, 2010
    Publication date: January 19, 2012
    Applicant: CLEAR WIRELESS LLC
    Inventors: Chunmei LIU, Masoud Olfat, Nagi Mansour
  • Patent number: 8098785
    Abstract: A signal processing circuit detects a pulsative change point of an input signal and sets a phase point which is shifted by a predetermined phase difference from the detected pulsative change point of the input signal as the timing for sampling the input signal.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: January 17, 2012
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Satoshi Otowa, Hisashi Zaimoku, Masaaki Wada
  • Patent number: 8081725
    Abstract: Signal processing circuit including a demodulator that receives a receive signal with signal edges, and outputs a demodulated receive signal with transitions from a first level to a second level or vice versa at signal edges of the receive signal, wherein points of time of the transitions depend on the steepnesses of the signal edges. The circuit also includes an edge evaluator that receives the receive signal, and outputs an evaluation signal which includes information about the steepnesses of the signal edges. The circuit also includes a signal generator that receives the output of the demodulator, receives the output of the edge evaluator, and outputs a corrected demodulated receive signal with transitions whose points of time are set with regard to the points of time of the transitions of the demodulated receive signal based on the evaluation signal in order to reduce influences of different steepnesses of the signal edges.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: December 20, 2011
    Assignee: Infineon Technologies AG
    Inventors: Thomas Leutgeb, Helmut Koroschetz, Walter Kargl
  • Patent number: 8077820
    Abstract: In one embodiment, a frequency correction (FC) burst is detected in a complex signal received by a mobile station of a GSM/EDGE wireless communications network by applying the complex signal to one or more correlation paths of a burst detector within the mobile station. Each correlation path generates a correlation signal by multiplying a copy of the complex signal by the complex conjugate of a delayed version of the complex signal and then applies a correlation filter to the correlation signal. A combined correlation signal is formed by combining the filtered correlation signals from the one or more correlation paths. Peak detection is applied to the combined correlation signal, where a detected peak corresponds to the occurrence of the burst in the complex input signal. The correlation filters are designed such that the peak in the combined correlation signal occurs prior to the end of the burst.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: December 13, 2011
    Assignee: Agere Systems Inc.
    Inventors: Krishna Prabhu Telukuntla, Peter Kabell Jensen
  • Patent number: 8068572
    Abstract: This invention discloses a self-timing method for phase adjustment. An analog signal is digitized at a first and second phase with respect to the symbols comprised in an analog signal in order to obtain first and second quantized samples. Then a first counter out of a first plurality of counters is increased if said first quantized sample has a first digital value to which said first counter is associated. Moreover a second counter out of a second plurality of counters is increased if a second quantized sample has a second digital value to which the second counter is associated. Finally the sampling phase is adjusted based on the values of the counters of the first and second plurality of counters. Moreover a digitizing, self-timing circuit is disclosed.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: November 29, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: Stefan Langenbach, Negojsa Stojanovic
  • Patent number: 8054927
    Abstract: The present invention includes: a synchronous-word detecting unit receives a baseband received signal including a synchronous word and data for each frame, and detects whether or not the synchronous word is coincided with an expected value in the baseband received signal by using an N-(N is an integer of 2 or larger) phase sampling clock; a phase information retaining unit retains phase information accumulatively including results detected for a plurality of frames by the synchronous-word detecting unit, and determines a phase to be sampled on the basis of the retained phase information; a phase selecting unit selects and determines a phase of the sampling clock on the basis of determination by the phase information retaining unit; and a FIFO buffer samples the data from the baseband received signal, and outputs the sampled data.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: November 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Shinya Konishi
  • Patent number: 8045667
    Abstract: A deserializer including a plurality of registers, a sync detector, and a lost bit storage unit. If there is a phase difference between an external input data packet and a recovery clock signal transmitted together with the data packet, the sync detector generates an activated sync detect signal. The lost bit storage unit detects a data bit of the data packet corresponding to an activation point of the sync detect signal. The deserializer recovers the data packet by combining the detected data bit with the data packet.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: October 25, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Kyul Lim, Dong-Chul Choi
  • Patent number: 8045664
    Abstract: A clock/data recovery device 1 comprises a sampler 10, a detector 20, an offset determination part 30, a clock output part 40, and a DA converter 50. The phases of clock signals CK and CKX are adjusted so as to match with the phase of an input digital signal. An offset amount (±Voff) added in the sampler 10 is adjusted so as to match with a peak time of a data transition time distribution of a first signal in a case where a value D(n?1) is HIGH level, and is adjusted so as to match with a peak time of a data transition time distribution of a second signal in a case where the value D(n?1) is LOW level. Either of the clock signals CK and CKX is outputted as the recovered clock signal. Time series data of a digital value D(n) is outputted as the recovered data.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: October 25, 2011
    Assignee: Thine Electronics, Inc.
    Inventor: Seiichi Ozawa
  • Patent number: 8036321
    Abstract: Control systems and methods for independent control of power systems, particularly lighting network branches, and separate control of individual branch components. Multi-branch systems comprise independently controllable branches that inter-communicate via PLC communications. In each branch, components such as ballasts, local control units, sensors, actuators, and repeaters, may exchange commands and queries independently of a branch remote control unit (BRCU). Alternatively, a BRCU may manage or arbitrate communications, or interact with other BRCUs, other control units and external management systems. Ballasts include a multi-channel ballast that enables close-loop control of individual fixtures, or of individual dimmable or non-dimmable lamps within a fixture. The close-loop control is facilitated by sampling circuits/sensors co-located with each controlled fixture or lamp. All controllers are preferably implemented using an integrated digital controller.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: October 11, 2011
    Assignee: S.T.L. Energy Solutions and Technologies Ltd.
    Inventors: Rafael Mogilner, Boris Nogtev, Yuri Kuhlik, Daniel Rubin, Arie Lev, Eytan Rabinovitz
  • Patent number: 8031819
    Abstract: Systems and methods for synchronizing an input signal with a substantial mitigation of race conditions and a substantial increase in resolving time are provided. One embodiment includes a system comprising a first latching device configured to latch a first output signal from the input signal and a delay element configured to receive the first output signal and output a delay signal that is a delayed version of the first output signal. The system also includes a pass-gate element configured to receive the first output signal and to output a second output signal in response to a logic state of the delay signal. The second output signal has a delayed input edge without a delayed resolving edge. The system can be configured to force the first output signal to a stable logic state in response to the first output signal having a metastable state.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: October 4, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Zhubiao Zhu, Carson Donahue Henrion, Daniel Alan Berkram
  • Patent number: 8023606
    Abstract: With the clock data restoration device 1, as a result of the processing of a loop which comprises the sampler section 10, detection section 20, timing determination section 30, and clock output section 40, the respective phases of the clock signal CKXA, clock signal CKXB, and clock signal CK are adjusted to match the phase of the input digital signal, the digital signal sampling time indicated by the clock signal CKXA is adjusted to match the peak time of the distribution of data transition times in a case where the value D (n?2) and value D(n?1) of the preceding two bits differ from one another, and the digital signal sampling time indicated by the clock signal CKXB is adjusted to match the peak time of the distribution of data transition times in a case where the value D (n?2) and value D(n?1) of the preceding two bits are equal to one another.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: September 20, 2011
    Assignee: Thine Electronics, Inc.
    Inventor: Seiichi Ozawa
  • Patent number: 8023602
    Abstract: Serial data communication methods and apparatus using a single line are provided. The data communication methods may include: setting a rising edge of a serial pulse signal so that a cycle of the serial pulse signal begins therefrom; setting a falling edge of the serial pulse signal within the cycle of the serial pulse signal according to a data value recorded within the cycle of the serial pulse signal; and transmitting a packet formed by combining at least one cycle of the serial pulse signal in series via a single line.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: September 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-Sang Choi
  • Patent number: 8014483
    Abstract: A receiver in an impulse wireless communication. The receiver (300) includes a pulse-pair correlator (304) that receives a signal (316) and divides it into two signals for paths. One of the signals is input to signal multiplier (312) while another signal is delayed by a delay unit (310). The signal multiplier (312) multiplies the received signal (316) by a delayed signal (318). An integrator (314) integrates an output signal (322) over a designated period of time. An adding module (306) sums an output signal (324) from the integrator (314). An acquiring module (308) compares an summing-up output (326) from the adding module (306) with a predetermined threshold value to detect the existence of a transmitting-standard preamble.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: September 6, 2011
    Assignee: Panasonic Corporation
    Inventors: Yew Soo Eng, Zhan Yu
  • Patent number: 8009784
    Abstract: A clock embedded differential data receiving system for ternary lines differential signaling. The clock embedded differential data receiving system includes a monitoring portion which monitors voltage levels of first, second and third transfer signals to generate a clock signal, a first pre-data and a second pre-data, a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding of the first pre-data and the second pre-data, and a timing controller to delay the transition time point of the clock signal with a delay phase which generates the sampling control signal.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: August 30, 2011
    Assignee: TLI Inc.
    Inventor: Jae Gan Ko
  • Patent number: 7991097
    Abstract: A method for adjusting a serial data signal having multiple sets of bits includes the following steps. First, one set of bits in the serial data signal is over-sampled to generate a first set of over-sampled bits. Next, every adjacent two bits of the first set of over-sampled bits are compared to generate one set of edge bits. Then, a delay operation is determined according to the set of edge bits. Afterwards, a displacement operation is executed on next sets of bits in the serial data signal according to the delay operation.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: August 2, 2011
    Assignee: Himax Technologies Limited
    Inventor: Hui-Min Wang
  • Publication number: 20110164711
    Abstract: A decoder and related method adaptively generate a clock window. A falling edge of a horizontal synchronization signal is detected, and the time difference between an actual frame code and a predefined frame code is determined. The beginning and the end of the clock window are then adaptively determined based on the falling edge and the time difference, such that symbol timing recovery through received clock run-in signals may be performed within the generated clock window.
    Type: Application
    Filed: January 4, 2010
    Publication date: July 7, 2011
    Applicant: HIMAX MEDIA SOLUTIONS, INC.
    Inventor: TIEN-JU TSAI
  • Patent number: 7974375
    Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: July 5, 2011
    Assignees: Samsung Electronics Co., Ltd., Korea University Industrial & Academic Collaboration Foundation
    Inventors: Chul-Woo Kim, Seok-Soo Yoon, Young-Ho Kwak, In-Ho Lee, Ki-Hong Kim
  • Patent number: 7970087
    Abstract: A system and method for bit eye center determination is provided. In general, the system samples an incoming data stream to determine where transitions in the data stream occur, selectively offsets the selected samples based on state criteria and the number of transitions in each set of samples, accumulates the offset samples and averages the result to determine the center of the bit eye. The system and method also provides the ability to locate the eye center even in the case of noise in the system, whether the noise is random or deterministic, including odd/even noise.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: June 28, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Steven D. Millman
  • Patent number: 7970091
    Abstract: A method that uses time-domain processing on a spectrally efficient digital modulation scheme to reduce the bandwidth expansion in envelope elimination and restoration (EER) amplifiers is disclosed. The method identifies and localizes sections of the signal responsible for the out of band emissions, or spectral regrowth, using a filter. The detected sections are flagged and extended to allow for introduction of a lower frequency transition in place of the extended section, thus reducing spectral regrowth from the output of an EER amplifier. The method is particularly useful for improving the quality of digital AM radio transmission.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: June 28, 2011
    Assignee: Nautel Limited
    Inventor: Brian W. Walker
  • Publication number: 20110103511
    Abstract: A transmission apparatus, a signal sending apparatus, and a signal receiving apparatus, and a transmission method, a signal sending method, and a signal receiving method capable of solving a problem of metastability and suppressing a delay of a signal when sending and receiving apparatuses having different operation clock frequencies send/receive the signal representative of control information, for example. Included are a sending part that operates in synchronization with a first clock having a first period to output a transmission signal having a signal level that is inverted in response to an input of a first pulse signal corresponding to the first period and a receiving part that operates in synchronization with a second clock having a second period to output a second pulse signal corresponding to the second period in response to inversion of a signal level of the transmission signal.
    Type: Application
    Filed: October 5, 2010
    Publication date: May 5, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Teruaki UEHARA
  • Patent number: 7936855
    Abstract: An oversampling data recovery circuit for a receiver comprises a plurality of sampling circuits for sampling an input data upon a plurality of clocks to generate a plurality of sample data, respectively, an edge detector for determining an edge of the input data by monitoring the plurality of sample data, and a state machine for selecting one from the plurality of sample data as an output data of the oversampling data recovery circuit according to the edge of the input data, such that the receiver will have an optimum timing margin.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: May 3, 2011
    Assignee: ITE Tech. Inc.
    Inventors: Tzuen-Hwan Lee, Shun-Yuan Hsiao
  • Publication number: 20110096884
    Abstract: A system and method for effectively supporting a data transmission procedure includes a phase-locked loop with a phase detector that compares a clock signal and input data to generate a phase error signal for adjusting the clock signal that is generated from a voltage-controlled oscillator. The phase detector includes a positive-edge detector circuit that generates an edge detection signal P to indicate whether data transitions are present in the input data. The phase detector also includes a lead/lag indicator circuit that generates a lead/lag indicator signal T to indicate whether the clock signal is early or late with respect to the input data.
    Type: Application
    Filed: November 16, 2010
    Publication date: April 28, 2011
    Inventor: Jeremy Chatwin
  • Patent number: 7920640
    Abstract: A transmission bit and transmission power distributing method that can reduce the arithmetic amount in a multiantenna-input/multiantenna-output (MIMO) wireless communication system. This method comprises steps of calculating a signal-to-interference-noise ratio (SINR) gain after MIMO detection of each of transport substreams (S601, S602); optimizing, based on the acquired SINR gain, a transmission bit and transmission power distribution in the space domain for all transport substreams on a particular subcarrier in the frequency domain, thereby deciding a transmission bit and transmission power distribution parameters (S603, S604); and optimizing a transmission bit and transmission power distribution for adjacent subcarriers, by sequentially using the transmission bit and transmission power distribution parameters distributed on the subcarrier for which the transmission bit and transmission power distribution parameters have been decided (S605 to S610).
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: April 5, 2011
    Assignee: Panasonic Corporation
    Inventors: Xiaoming She, Jifeng Li
  • Patent number: 7913101
    Abstract: A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: March 22, 2011
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Jae-sun Seo, Ram K. Krishnamurthy
  • Patent number: 7894328
    Abstract: The present invention is directed to a method, apparatus and system for detecting the mode and the guard interval of a received orthogonal frequency division multiplexing (OFDM) symbol, which includes a guard interval with length Ng, and a useful part with length Nu. Mode is detected by searching for the maximum correlation or statistics value based on one (for example, the shortest one) guard interval length. Further, guard interval is detected by searching for the maximum correlation value based on all guard interval lengths.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: February 22, 2011
    Assignee: Via Technologies, Inc.
    Inventor: Yahong Zhao
  • Patent number: 7881418
    Abstract: A base point of a communication frame is detected by only using a reception signal, and an offset amount from the base point and the like are estimated. A device includes: an extraction unit for extracting self correlation processing signals from a digital communication signal having a signal frame for synchronization by using a pair of correlation processing windows of a variable size; a correlation unit for performing self correlation processing to the self correlation processing signals extracted; a matching unit for performing pattern matching processing between the correlation-processed signal, obtained through the self correlation processing, and a reference signal; and a computation unit for estimating the base point of the signal frame and an offset of the digital communication signal with respect to the base point, based on distance information of the pattern matching processing.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: February 1, 2011
    Assignee: NEC Corporation
    Inventor: Hiroyuki Ishii
  • Publication number: 20110008055
    Abstract: An apparatus comprising an optical receiver configured to receive an optical signal, and a combined level and clock recovery circuit coupled to the optical receiver and configured to update a signal threshold and a clock phase substantially simultaneously. Also included is an apparatus comprising at least one processor configured to implement a method comprising recognizing reception of a signal, and adjusting a threshold and a clock phase associated with the signal using a rising time for the signal and a falling time for the signal. Also included is a method comprising receiving a signal, and adjusting a threshold level of the signal to establish level recovery using a clock recovery scheme.
    Type: Application
    Filed: November 23, 2009
    Publication date: January 13, 2011
    Applicant: FUTUREWEI TECHNOLOGIES, INC.
    Inventor: Frank J. Effenberger
  • Patent number: 7864894
    Abstract: Clock signals are supplied, with a phase shift of 1/n cycles between adjacent clock signals. A data acquisition unit acquires serial data at a timing of each of the clock signals. A phase detection unit detects the phase of the transition edge of the serial data using n bits of data. An effective bit number determination unit determines the effective bit number, which is the number of bits to be acquired, based upon the phase of the transition edge of the serial data in the current data-bit acquisition step and the phase of the transition edge of the serial data in the previous data-bit acquisition step. A data-bit output unit outputs the effective bit number of the bits of data acquired at a timing of each clock signal having a predetermined phase relation with the transition edge of the serial data.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: January 4, 2011
    Assignee: Rohm Co., Ltd.
    Inventor: Makoto Terada
  • Patent number: 7864906
    Abstract: A system (101) for clock signal synchronization includes a data analyzer (104) and a synchronized clock signal generator (105) coupled to an RC oscillator (103). The data analyzer (104) generates a digital control signal representing the number of cycles of a reference signal of the RC oscillator (103) during an eight-bit period of an incoming token packet. The synchronized signal clock generator (105) uses the digital control signal to lock a clock signal to packets that have the same bit rate as the token packet.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: January 4, 2011
    Assignee: Apexone Microelectronics Ltd.
    Inventors: Qingjiang Ma, James Y. Gao, Yongqing Ren
  • Patent number: 7865756
    Abstract: A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller has an output for providing a first clock signal to a first device, and an input for receiving a second clock signal from a second device. The second clock signal corresponds to a version of the first clock signal that has undergone processing by a clock synchronizer in at least one of the devices.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: January 4, 2011
    Assignee: Mosaid Technologies Incorporated
    Inventor: HakJune Oh