Abstract: A symbol clock recovery circuit is provided for a data communication system using coherent demodulation. The symbol clock recovery circuit comprises an analog-to-digital converter comprising a first input for receiving a coherent-detected baseband analog signal derived from a carrier signal, a second input for receiving an adapted symbol clock signal, and an output for outputting a digital signal comprising a frame having a preamble with at least two symbols. The symbol clock recovery circuit comprises further a phase shifting unit comprising a first input for receiving a symbol clock signal derived from the carrier signal, and a timing detector, comprising a first input for receiving the digital signal from the analog-to-digital converter and an output for providing a signal comprising information about an optimum sample phase to the phase shifting unit.

Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

Abstract: A signal transition detection circuit is provided. The signal transition detection circuit comprises a counter module, a DAC, a comparator and a digital sampling module. The counter module generates a digital step signal. The DAC converts the digital step signal into an analog input signal and transmits it to an under-test circuit such that the under-test circuit generates an output signal transiting from a first stable level to a second stable level, wherein a transition section is located between the first and the second stable level. The comparator receives and compares the output signal with a default value to generate a normalized output signal. The digital sampling module samples the normalized output signal to retrieve impulses such that when the number of the impulses is accumulated to be larger than a reference value, a corresponding step of the digital step signal is determined to be a transition point.

Abstract: To realize quick adaptation to a communication link between a transmitter and a receiver by using two different frequency carriers. A receiver detects a preamble from a transmission bit string. When determining that a total sum of the number of modified bits exceeds a certain threshold in a range of a payload following the preamble (when detecting that a reception state of a communication link has been degraded), the receiver issues, to a transmitter, a request for changing a transmission parameter (four parameters may be used for enhancement/lowering) for the transmission bit string by using a communication link, which is a relatively-low-frequency carrier. On the other hand, the transmitter receives the request for change, and executes the request for changing the transmission parameter for the transmission bit string while maintaining transmission of a payload in the transmission bit string.

Abstract: A method for detecting a pattern in a signal according to one embodiment includes determining a time between symbol transitions in a signal derived from a radio frequency signal; determining ratios of relational times between consecutive symbol transitions; and comparing a sequence of the ratios to a target pattern for determining whether the sequence corresponds to the target pattern. Such methodology may also be implemented as a system using logic for performing the various operations. Additional systems and methods are also presented.

Abstract: Aspects of the present disclosure are directed towards a circuit-based apparatus for receiving data communications over power distribution lines that carry power using alternating current (AC). The apparatus has a processing circuit that is configured and arranged to receive an input signal representing the data communications over power distribution lines. For a quadrature encoded signal, the input signal is separated into intermediary signals representing a real portion of and an imaginary portion. The processing circuit can then determine timing information from the real portion of and the imaginary portion. The intermediary signals can then be decimated according to a variable rate of decimation that is responsive to the determined timing information. The decimated intermediary signals are also filtered.

Abstract: In various aspects, the disclosure describes systems and methods for decoding of convolutionally encoded signals representing, for example, telecommunications signals such as command or content signals used in digital telecommunications. In various embodiments such aspects of the disclosure provide systems and methods for improving the efficiency, speed, and power consumption of such processes by providing architectures and methods for processing various parts of the encoded data records in parallel, using multiple and optionally specially-designed, dedicated memory registers and multiplexers.

Abstract: Apparatus, methods, and systems are disclosed, including, for example, a data receiver to receive a calibration voltage and a reference voltage to calibrate the data receiver. The output of the data receiver is provided to a first ripple counter that counts the outputs from the data receiver and provides an output count. The ripple counter may count either ones or zeros. A second ripple counter counts the number of a clock signals over the same period of time. The output count is either multiplied by two or the count of clock signals is divided by two. A ripple comparator may then compare the outputs and adjust the reference voltage based upon the comparison results.

Abstract: Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some embodiments, each counter or clock has a different speed. A faster counter or clock is used to determine intra-transition position offsets relative to a slower counter or clock.

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

Abstract: A pulse signal receiving apparatus may include a reception unit that receives a pulse signal modulated by a double-edge modulation scheme, a measurement unit that measures an edge interval of the pulse signal, which has been received by the reception unit, a detection unit that detects a deviation of the edge interval, which has been measured by the measurement unit, for a pulse-width reference value indicating a reference value of a width of the pulse signal, a correction unit that corrects the edge interval, which is to be measured next by the measurement unit, by using the deviation, which has been detected by the detection unit, and a decoding unit that decodes the pulse signal, of which the edge interval has been corrected by the correction unit, so as to output a digital signal.

Abstract: Provided is an equalization device which receives a signal transmitted from a transmission side of the signal as an input signal, and equalizes the deterioration of a wave shape of the received input signal, wherein a bit value indicated by the input signal is judged in accordance with a clock on the basis of the wave shape of the input signal. From judged signals which result from the judgment and which are composed of a plurality of bits, a two-bit transition signal is detected so that the two-bit transition signal has two adjacent bit values having the same value, and bit values located before and after the two adjacent bit values are different from the bit value of the two adjacent bit values, and the phase of the clock is synchronized with the phase of the detected two-bit transition signal.

Abstract: In one embodiment, receiving an Ethernet signal over a channel, the Ethernet signal comprising a preamble frame, an idle frame, and a data frame, the preamble frame comprising one or more preamble codes; synchronizing to the Ethernet signal based on the preamble frame; replicating the one or more preamble codes; and training a decision feedback equalizer (DFE) based on the one or more replicated codes, the training enabling the DFE to use decision values at the DFE output to track channel variations.

Abstract: An object of the present invention is to provide a data communication technique which can reduce a size of a system by enabling bidirectional data communication, and enables a cheap system configuration.

Abstract: A receiver for receiving an input signal (a clock-embedded data (CED) signal), in which a clock signal is periodically embedded between data signals, includes a clock recovery unit configured to recover and output the clock signal and a serial-to-parallel converter configured to recover and output a data signal. The input signal (the CED signal) comprises a single level signal in which the clock signal is periodically embedded between the data signals at the same level. The clock recovery unit is configured based on a delay locked loop (DLL) without using an internal oscillator for generating a reference clock signal.

Abstract: Biphase mark codes (BMC) are used in digital communications. Most BMC formats use preambles for rate determination and synchronization. A decoder compares the intervals of continuous high or continuous low voltages in a BMC stream to predetermined minimum and maximum values of half cell, full cell and one-and-a-half cell intervals for all supported sampling rates. If a pattern matching a preamble is found, the sampling rate is locked in and the decoder is synchronized to the BMC stream. Once locked, the decoder uses the predetermined minimum and maximum values at the locked rate to generate half cell, full cell and one-and-a-half cell indicators for a decoding state machine which decodes data in the BMC stream or decodes expected preambles.

Abstract: An interface circuit for enabling clock and data recovery (CDR) of N-level pulse amplitude modulation (N-PAM) modulated data streams using a 2-PAM CDR circuit. The circuit comprises a number of N?1 comparators for comparing an input data stream to N?1 configurable thresholds, the input data stream is N-PAM modulated and the N?1 configurable thresholds are N?1 different voltage levels; a number of N?1 of edge detectors respectively connected to the N?1 comparators for detecting transitions from one logic value to another logic value, N is a discrete number greater than two; and a determination unit for determining if the detected transitions is any one of a major transition and a minor transition and asserting a transition signal if only a major transition or a minor transition has occurred, the transition signal is fed into a 2-PAM CDR circuit and utilized for recovering a clock signal of the input data stream.

Abstract: Disclosed is an input module of a programmable logic controller (PLC) capable of counting coefficient values of multiple channels. An input module of a PLC includes a plurality of detection units, a decision unit and a control unit. The plurality of detection units receives a pulse signal corresponding to each channel, applied from a load having a plurality of channels, detects rising and falling edges of the pulse signal, and transmits an output signal that is the detected result. The decision unit receives a plurality of output signals respectively transmitted from the plurality of detection units, detects edges of the plurality of channels, and transmits a detection signal that is the detected result. The control unit identifies the presence of occurrence of an interrupt using the detection signal transmitted from the decision unit and performs a counting process using the applied pulse signal when the interrupt occurs.

Abstract: A transceiver comprises a transmitter that converts a plurality of data components into serial data in response to a first clock signal and transmits the serial data, and a receiver that receives the serial data and converts the serial data into the plurality of data components in response to a second clock signal generated from the serial data. The transmitter adds at least one dummy bit to the serial data at predetermined intervals. The at least one dummy bit includes information regarding a data type of the plurality of data components.

Abstract: A data reception unit 21 of a reception device 20n receives calibration data to detect a data reception state or a clock reception state in the reception device 20n from a data transmission unit 11 of a transmission device 10. A decoder unit 24 causes a transmission unit 26 to send out calibration sample data that a sampler unit 23 obtained by sampling calibration data to the transmission device 10. A control unit 15 of the transmission device 10 detects a data reception state or a clock reception state in the reception device 20n based on calibration sample data received from the reception device 20n and controls the data transmission unit 11 and a clock transmission unit 12 based on the detection result.

Abstract: A clock and data recovery circuit includes a multiphase clock generator circuit which generates a multiphase clock having a plurality of clocks, a sampling circuit which samples a received data signal transferring serial data in synchronism with each of the plurality of clocks, and generates a plurality of data signals, a data recovery unit which generates a selection signal indicating a data signal having an appropriate phase among the plurality of data signals, and a storage unit which stores the selection signal. The data recovery unit selects one of the plurality of data signals, based on the selection signal read from the storage unit, and a clock corresponding to the selected data signal.

Abstract: An embodiment of the present invention provides a method for digital television demodulation, comprising using adjacent-channel power dependent automatic gain control (AGC) for the digital television demodulation, wherein an AGC technique takes into account a total power as well as power of adjacent channels to control gain of a gain control amplifier.

Abstract: Aspects of the disclosure provide a method for detecting marks. The method includes receiving a data signal from a channel. Further, the method includes matching the data signal to a template that corresponds to a predetermined pattern transmitted over the channel to detect marks, prior to decoding the data signal into a decoded bit stream.

Abstract: In one general aspect, an apparatus can include a reference oscillator counter circuit configured to produce a reference oscillator count value based on a reference oscillator signal, and a target oscillator counter circuit configured to produce a target oscillator count value based on a target oscillator signal where the target oscillator signal has a frequency targeted for calibration against a frequency of the reference oscillator signal. The apparatus can include a difference circuit configured to calculate a difference between the reference oscillator counter value and the target oscillator counter value, and a summation circuit configured to define a trim code based on only a portion of bit values from the difference.

Abstract: An apparatus for receiving data in a communication system includes: a detection unit configured to calculate power values of a data packet and a ratio of the power values by using a preamble of the data packet in a received signal, and detect the data packet through the calculated ratio of the power values; a control unit configured to calculate a gain compensation value of the detected data packet, and perform an automatic gain control (AGC) on the detected data packet by using the gain compensation value; a compensation unit configured to calculate a DC offset in the received signal, and remove the DC offset from the received signal; and a demodulator configured to demodulate the AGCed data packet.

Abstract: Disclosed herein is a CDR circuit including delay elements, including: a divider having a delay element and configured to extract a clock by using, as a trigger, a data input with a signal transition regularly inserted; and a latch configured to latch an input data signal in synchronization with the clock extracted by the divider.

Abstract: A sampler circuit comprises a plurality of series-connected sampler cells and a detector circuit. Each successive stage comprises twice the number of sampler cells, in parallel, as the previous stage, and is clocked at half the sampling frequency of the previous stage. Each sampler cell comprises two parallel branches of series-connected clocked inverters. A clocked inverter is operative to invert an applied signal during one phase of an applied sampling clock, and to render a high impedance output during the other sampling clock phase. Successive clocked inverters are clocked with opposite (i.e., positive/negative) versions of the sampling clock. The detector circuit examines the outputs of the last stage of sampler cells, and may for example comprise an OR function to detect a state transition in an applied input signal. The sampler circuit exhibits immunity to metastability and low power consumption.

Abstract: An apparatus comprising an optical receiver configured to receive an optical signal, and a combined level and clock recovery circuit coupled to the optical receiver and configured to update a signal threshold and a clock phase substantially simultaneously. Also included is an apparatus comprising at least one processor configured to implement a method comprising recognizing reception of a signal, and adjusting a threshold and a clock phase associated with the signal using a rising time for the signal and a falling time for the signal. Also included is a method comprising receiving a signal, and adjusting a threshold level of the signal to establish level recovery using a clock recovery scheme.

Abstract: A circuit includes a receiver circuit, a data valid monitor circuit, a clock signal generation circuit, and a phase shift circuit. The receiver circuit is operable to generate a first periodic signal, a sampled data signal based on an input data signal, and a data valid signal based on a predefined number of bits in the sampled data signal. The data valid monitor circuit is operable to generate a count value by counting periods of the first periodic signal. The data valid monitor circuit is operable to generate a phase error signal based on the data valid signal and the count value. The clock signal generation circuit is operable to generate a second periodic signal. The phase shift circuit is operable to generate a third periodic signal based on the second periodic signal and to adjust a phase of the third periodic signal based on the phase error signal.

Abstract: An apparatus provides a digital representation of a time difference between a periodic reference signal having a reference signal period and a periodic input signal having an input signal period. The apparatus includes a free-running finite state machine (FSM) that traverses a multiplicity of states in a predetermined order, the state having corresponding state vectors, each of which is held for a state dwell time. A timing circuit receives the reference signal, the input signal and the FSM state vectors, and determines a state transition count equal to a number of FSM state transitions that occur during a counting interval, which corresponds to the time difference between the reference and input signals. A digital low-pass filter receives the state transition counts and provides an output value including weighted sums of the state transition counts, proportional to the time difference between the reference and input signal. A period of the FSM is independent of the reference signal period.

Abstract: A communication receiver and a receiving method are disclosed. An analog front-end device samples a receiving signal and generates a sampled signal. A signal detector detects presence of the receiving signal according to the sampled signal. A symbol timing recovery (STR) unit determines an optimal symbol sampling point according to a zero-crossing point of the sampled signal when the receiving signal is present, and then generates a recovered symbol based on an optimally chosen sampled value according to the optimal symbol sampling point.

Abstract: A signal generation system maintains a phase relationship between output signals of first and second signal generators even when the sampling clock frequency is changed. The signal generators are coupled via a communication means including a dedicated cable where the delay amount of the communication means is known and fixed. The first signal generator provides sampling clock, sequence clock and trigger/event signals to the second signal generator and CPUs of the generators share information via the cable. When the frequency of the sampling clock is changed, the CPU of the first or second signal generator calculates the clock number of the frequency changed sampling clock equivalent to the delay amount of the communication means. A delay circuit of the first signal generator 100 delays the waveform data by one sampling clock based on the calculated value for adjusting phase relationship between the waveform data in the signal generators 1.

Abstract: Disclosed is a method and apparatus for clock checking, to solve the problem of high resource occupation in existing clock checking methods. The method includes: a programmable device for performing frequency division on the source clock signal to obtain a reference clock signal; treating the source clock signal as a counting work clock to determine the counting value of rising edges and counting value of high levels of a clock signal being checked during each high level period out of N continuous high levels of the reference clock signal; and determining whether the clock signal being checked is valid according to the magnitude relationship between the counting value of the high levels of the clock signal being checked during each high level period and a first expected value, as well as the magnitude relationship between the counting value of the rising edges and a second expected value.

Abstract: Provided is a signal processing apparatus including: an equalizer circuit that amplifies a predetermined frequency band of an input signal and outputs an output signal; a sampler circuit that samples the output signal amplified by the equalizer circuit with the output signal being offset in an amplitude direction using a multiphase clock system; an area information calculation circuit that calculates area information of an eye opening in an eye diagram of the output signal based on the output signal sampled by the sampler circuit; and a control circuit that controls amplification of the equalizer circuit based on the area information of the eye opening calculated by the area information calculation circuit.

Abstract: In various aspects, the disclosure describes systems and methods for decoding of convolutionally encoded signals representing, for example, telecommunications signals such as command or content signals used in digital telecommunications. In various embodiments such aspects of the disclosure provide systems and methods for improving the efficiency, speed, and power consumption of such processes by providing architectures and methods for processing various parts of the encoded data records in parallel, using multiple and optionally specially-designed, dedicated memory registers and multiplexers.

Abstract: A channel equalizer that compensates for signal distortion of a signal in a communication channel includes an equalization filter, which gain-equalizes a received signal received through the communication channel, and an equalization control circuit, which generates a gain control signal for controlling the gain of the equalization filter. The equalization control circuit specifies a phase switch in data obtained by the equalization filter as an isolated bit and generates the gain control signal based on a width of the isolated bit.

Abstract: Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some embodiments, each counter or clock has a different speed. A faster counter or clock is used to determine intra-transition position offsets relative to a slower counter or clock.

Abstract: Systems and methods of operating a serial interconnect interface provide for generating a pulse in response to a state change in a data signal of the serial interface interconnect, and transmitting the pulse from a physical layer of the serial interconnect interface to a link layer of the serial interconnect interface. The duration of the pulse can be selected based on whether the state change corresponds to an end of packet (EOP) condition. In addition, the data signal may include a non return to zero invert (NRZI) encoded signal, wherein the pulse is part of a digital NRZI signal.

Abstract: The embodiment of the present disclosure discloses a method and apparatus for detecting frequency deviation of a clock. The method includes: counting the clock to be detected to acquire current counting information; filtering the current counting information to acquire filtered data; and acquiring the frequency deviation of the clock to be detected from the filtered data. According to the embodiments of the present disclosure, the detection accuracy of frequency deviation is improved by filtering the counting information acquired by counting the clock to be detected, and appropriately increasing an amount of information after the filtering, so as to perceive the occurrence of any abnormal dithering, and avoid neglecting of any abnormal condition in periodic or aperiodic queries.

Abstract: A communication device includes a current information storage unit 130 that stores the bit boundary signal at each of timings at which a sampling clock is updated, a past information storage unit 140 that takes in and stores a signal stored in the current information storage unit 130 when a variation point of a reception signal is detected, and does not update a signal stored therein when no variation point of the reception signal is detected, and a clock selection unit 44 that selects CLKSEL2 used for the sampling of the reception signal from N-phase clocks based on a signal stored in the current information storage unit 130 when a variation point of the reception signal is detected, and selects CLKSEL3 based on a signal stored in the past information storage unit 140 when no variation point of the reception signal is detected.

Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

Abstract: An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.

Abstract: An electronics device is disclosed that reduces latency resulting from communication between a first electronics component operating based on a fast clock and a second electronics component operating based on a slow clock reduces communication latency. When transferring the data from the first component to the second, the data is written into a buffer using the first clock, and then extracted by the second component using the second clock. Alternatively, when transferring the data from the second component to the first component, the first component reads the data from the second component and monitors whether the data was extracted during a relevant edge of the second clock signal, in which case the first component again extracts the data from the second component.

Abstract: Apparatus, methods, and systems are disclosed, including, for example, a data receiver to receive a calibration voltage and a reference voltage to calibrate the data receiver. The output of the data receiver is provided to a first ripple counter that counts the outputs from the data receiver and provides an output count. The ripple counter may count either ones or zeros. A second ripple counter counts the number of a clock signals over the same period of time. The output count is either multiplied by two or the count of clock signals is divided by two. A ripple comparator may then compare the outputs and adjust the reference voltage based upon the comparison results.

Abstract: Systems, methods, and circuits extract data from an oversampled data stream in the presence of noise and/or jitter. Pointers decide which data samples of the oversampled data stream are extracted. Some of the pointers occurring right after a data transition are positioned based on the location of previous pointers, rather than using the data transition points as occurs during an alignment. Settings such as the frequency of how often a pointer is aligned with a data transition and a maximum adjustment amount during an alignment may be programmable.

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

Abstract: An embodiment of a detector includes first and second generators. The first generator is operable to receive a transition of a first signal and to generate in response to the transition a first pulse having a length that is approximately equal to a length of a detection window. And the second generator is operable to receive a second signal and to generate a second pulse having a relationship to the first pulse in response to a transition of the second signal occurring approximately during the detection window.

Abstract: In a receiving device for receiving a time-multiplexed signal on one carrier frequency and for reading out a content datum of a further time-multiplexed signal on a further carrier frequency, a receiving unit and a context changing unit are provided in order to change, for the duration of a data symbol in the frame of the time-multiplexed signal of the carrier frequency, to reception of the further time-multiplexed signal on the further carrier frequency, in order to receive a data symbol of the further time-multiplexed signal.

Abstract: A decoder and related method adaptively generate a clock window. A falling edge of a horizontal synchronization signal is detected, and the time difference between an actual frame code and a predefined frame code is determined. The beginning and the end of the clock window are then adaptively determined based on the falling edge and the time difference, such that symbol timing recovery through received clock run-in signals may be performed within the generated clock window.

Abstract: A method and apparatus of clock recovery is disclosed. The apparatus comprising: a first delay circuit for receiving an input data signal and outputting a delayed data signal; an edge extraction circuit for outputting an edge signal by detecting a transition in the input data signal; an clock generator for generating a first clock signal based on an injection of the edge signal, wherein the first clock signal comprises a plurality of phase signals; a second delay buffer for outputting a second clock signal according to the first clock signal; a sampler for outputting a plurality of samples based on sampling the delayed data signal in accordance with the phase signals; and a decision circuit for generating a decision in accordance with the second clock signal based on the three samples and a previous decision.