Abstract: A system including an estimation module, a processing module, and a control module. The estimation module is configured to generate a first set of channel estimates for a plurality of subcarriers of a received signal. The processing module is configured to generate a second set of channel estimates for the plurality of subcarriers, in which the second set of channel estimates are generated based on the first set of channel estimates. The control module is configured to estimate a preamble sequence in the received signal based on each of (i) the first set of channel estimates and (ii) the second set of channel estimates.

Abstract: In a method and a device for decoding a signal, the signal is transmitted via at least one connecting line of a data transmission system, in a user of the data transmission system receiving the signal. It is provided to measure the interval of a change—provided compulsorily in a transmission protocol used in the data transmission system—of the signal from rising to falling or from falling to rising edge. A tendency for an asymmetrical delay of the signal can be ascertained from the measured interval. The sampling of the bits of the received signal can be improved as a function of the interval or of the asymmetrical delay, for example, by setting the sampling instant in variable fashion. Alternatively, the interval or the asymmetrical delay can be utilized for diagnostic purposes.

Abstract: The present invention relates to the communication field and discloses a method and an apparatus for implementing pulse synchronization, so that the control on a single-chip multi-channel device can be simplified. A method for implementing pulse synchronization includes: when a cycle count value corresponding to a reference symbol port of the multiple ports reaches a length of a predetermined pulse cycle, obtaining, by a microprocessor, cycle count values corresponding to the multiple ports; obtaining lengths of temporary synchronization cycles of the multiple ports according to the length of the predetermined pulse cycle and the cycle count values corresponding to the multiple ports; and sending the lengths of the temporary synchronization cycles to logic circuits corresponding to the multiple ports. Embodiments of the present invention are mainly applied in communication systems to output pulse symbols synchronously.

Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.

Abstract: An apparatus for frequency synchronization is proposed to detect a synchronization signal from the baseband signals. It is featured that three types of detection values are introduced to detect whether the synchronization signal is received or not. More particularly, the claimed frequency synchronization apparatus provides at least one signal power generator for receiving a predetermined number of symbols of the baseband signals, and further calculating an average quality value therefore. Further, the apparatus includes a signal selector for producing a first detection value according to the average quality value. Still further, the apparatus provides a decision unit to produce a second detection value. After that, a signal processor inside the decision unit is used to calculate a third detection value as combining the first detection value and the second detection.

Abstract: An approach is provided for supporting carrier synchronization in a digital broadcast and interactive system. A carrier synchronization module receives one or more signals representing a frame that includes one or more overhead fields (e.g., preamble and optional pilot blocks and one or multiple segments separated by pilot blocks). The module estimates carrier frequency and phase on a segment by segment basis and tracks frequency between segments. Carrier phase of the signal is estimated based upon the overhead field. Estimates carrier phase of random data field are determined based upon the estimated phase values from the overhead fields, and upon both the past and future data signals. Further, the frequency of the signal is estimated based upon the overhead fields and/or the random data field. The above arrangement is particularly suited to a digital satellite broadcast and interactive system.

Abstract: The disclosed embodiments provide methods and systems for synchronizing a transmitter and a receiver. In one embodiment, a method for synchronizing a transmitter and a receiver includes the transmitter performing a reset operation, and the receiver responding by performing a reset operation. In another embodiment, a method for synchronizing a transmitter and a receiver includes the receiver performing a reset operation, and the transmitter responding by performing a reset operation. The reset indicator includes toggling a reset indicator.

Abstract: A method for detecting a specific timing from a synchronization channel is described. A signal with a known sequence is received. Two or more correlation values between the received signal and the known sequence are calculated at two or more positions. The two or more correlation values are compared. A determination is made whether the position of the known sequence has been shifted based on the comparison. A specific timing of a synchronization channel is detected based on the determination.

Abstract: Certain aspects of a method and system for satellite communication are disclosed. Aspects of one method may include a receiver that handles digital video broadcasting. The receiver may be enabled to dynamically vary spacing between one or more pilots within at least one frame based on a determined symbol rate. The size of each of a plurality of received programs may be determined and the spacing between one or more pilots may be dynamically varied based on the determined size of each of the plurality of received programs.

Abstract: A receiving method and apparatus for increasing coherent integration length while receiving a positioning signal from transmitters such as GPS satellites. In order to compensate for frequency drifts that may occur in the positioning signal, a hypothesis is made as to the frequency drift, which is inserted into the receiving algorithm. Advantageously, the length of coherent integration can be increased at the expense of reducing the length of incoherent integration while keeping the total integration length the same, the net effect of which is an increase in signal detection sensitivity. The frequency drift hypothesis has any appropriate waveform; for example, approximately linear or exponential.

Abstract: Systems and methods provide for data transfer and transmission according to a synchronous one-bit interface protocol. A bit stream is generated including first data to be transferred or transmitted and second data from which a clock period used to encode the first data may be extracted. The bit stream is provided to a processor for decoding. In one embodiment, the bit stream includes a start segment or sequence, a data segment and a stop segment or sequence. A clock period is encoded into and is extracted from the start and/or stop sequences. The data segment is decoded on the basis of the clock period.

Abstract: For example, a method of detecting frame marker quality includes: detecting, in a bit-stream sent from a first component to a second component of a common hardware unit, a frame marker having a bit pattern different from an uncorrupted frame marker specified by a communication protocol; and assigning a quality level indicator to the frame marker based on a difference between said bit pattern and a bit pattern of said uncorrupted frame marker.

Abstract: A communication system includes first and second independently clocked devices, comprising, for each device, a transmitter and a receiver connected to each other in a crossed way in correspondence of an inter-chip communication channel. The communication system further comprises a synchronizer in turn including at least a first and a second synchronization block, having respective input terminals connected to the receivers and respective output terminals connected to the transmitters and comprising at least: a test pattern generator that generates a programmable test pattern signal; a pattern detector to check a matching between stored and received test pattern signals and thus lock corresponding clock phases of the synchronization blocks in case of positive result of this check; and a delay block able to change the clock phases until a synchronized condition of the synchronization blocks is verified, this synchronized condition corresponding to a matching between stored and received test pattern signals.

Abstract: A system is provided for use with a frequency band including a transmission frequency and a received frequency. The transmission frequency includes a transmission signal having a transmitted unique word therein. The received frequency includes a received signal having a received unique word therein, wherein the received unique word had been received at a received time and at a received phase. The system includes a first sub-correlator, a second sub-correlator and a discrete Fourier transform device. The first sub-correlator can perform a first correlation of only a first portion of the received unique word with a corresponding first portion of the transmitted unique word over a plurality of instances of time and can output a first plurality of sub-correlation values.

Abstract: A Wireless Regional Area Network (WRAN) receiver comprises a transceiver for communicating with a wireless network over one of a number of channels, and an Advanced Television Systems Committee (ATSC) signal detector for use in forming a supported channel list comprising those ones of the number of channels upon which an ATSC signal was not detected, wherein the ATSC signal detector is a threshold-based detector and detects an ATSC signal as a function of at least one threshold, and wherein the ATSC signal detector is responsive to at least one of a carrier tracking loop lock signal, a symbol timing recovery lock signal and a synchronization (sync) lock signal.

Abstract: A frame synchronization device and a frame synchronization method capable of preventing a malfunction when a frame is synchronized by using a frame synchronization pattern varying sequentially is presented. A bit serial signal at every frame is transmitted sequentially in a shift register composed of flip-flop circuits. When a bit in each of the stages is detected to be coincided with a corresponding bit in a frame synchronization pattern by coincidence circuits, existence of a synchronized frame is determined. Each bit in the synchronization pattern is also inputted into an all-zero detection circuit. If an all-zero state is detected, a first AND circuit does not output a synchronization pattern detecting signal even with a case where coincidence is detected from the coincidence circuits.

Abstract: Described is an apparatus for suppressing spurious spectral lines in a frame based bit-serial data stream, in which frames include payload data and frame markers. The apparatus includes means (16) for randomizing first frame marker elements (START) in a first position within each frame and means (18) for correlating second frame marker elements (STOP) in a second position within each frame with the randomized first frame marker element.

Abstract: A receiving method for a digital stream, the stream including frames having each a body composed of a variable number c of symbols and preceded by a header including d symbols, a field composed of a fixed number e of symbols unknown to the receiver and defining the number c. A locking phase of the receiving method includes receiving a series of e symbols of the stream; performing a correlation computation for pairs of symbols received, the correlation computation being used to verify a predefined relationship if the e symbols form the unknown field; determining a correlation level and determining whether the e symbols form the unknown field on the basis of the correlation level; repeating the steps until it is determined that the e symbols form the unknown field.

Abstract: Apparatus, systems, and methods are provided for transmitting messages over a serial interface. A method comprises receiving a first signal at a first time and receiving a second signal at a second time, the second time being after the first time. If a difference between the second time and the first time is less than a threshold time period, the method comprises generating a first message that is representative of the first signal and the second signal and transmitting the first message over the serial interface. In accordance with one embodiment, the threshold time period is equal to one half of an interface acquisition delay time period associated with the serial interface.

Abstract: A system including a magnitude measuring module, an energy normalization module, and a metric generation module. The magnitude measuring module is configured to measure magnitudes of real portions of differentially demodulated signals, wherein the differentially demodulated signals are generated by differential demodulation of signals received from a base station. The energy normalization module is configured to generate a sum of energies of a plurality of subcarriers included in the signals received from the base station. The metric generation module is configured to generate a plurality of metrics for a plurality of symbols included in the signals received from the base station. The metric generation module is further configured to detect, based on the plurality of metrics, a preamble symbol included in the signals received from the base station.

Abstract: A technique for detecting one or more access bursts (112) in a random access channel (110) is described. Each access burst includes a transmission preamble, the transmission preamble being a member of a preamble set including sequences of preamble symbols that can be obtained by cyclically shifting a basic preamble sequence. A detector (118, 120) in a radio base station (108) determines correlation information indicative of a correlation of a single correlation preamble with each of the one or more received transmission preambles, wherein the correlation preamble is a member of the preamble set. The one or more access bursts are detected based on the correlation information.

Abstract: A system and method utilize a dual correlation, one for the synchronization pattern (sync correlation) and one for the channel equalization pattern (CE correlation), to determine where the channel equalization pattern starts and thus establish frame synchronization. The system and method compare the two correlations and decides on the start of the channel equalization symbols when the CE correlation is larger than the sync correlation.

Abstract: A preamble detector for a plurality of streams of baseband digitized signals has a plurality of preamble processors, each preamble processor coupled to an input and generating an output. Each preamble processor has an input coupled to a first delay, the output of the first delay coupled to a second delay generating an output. The first and second delay are substantially equal to a preamble part. A first multiplier generates an output from a conjugated output of the second delay output and a first delay output. A second multiplier generates an output from a conjugated first delay output and an input stream. The first and second multiplier outputs are accumulated over an interval, and the complex output of the accumulator is formed into a magnitude, thereby generating the output of each preamble processor. The outputs of the preamble processors are summed and compared to a threshold to generate a preamble detect.

Abstract: A method and system of sample recovery is disclosed. In one embodiment, a method includes selecting initially in an arbitrary manner, a current symbol from a sequence of input samples, comparing a symbol timing estimate associated with the current symbol to a predetermined threshold, selecting a future symbol strobe that is ahead at an interval equivalent to a predetermined interval based on the comparison of the symbol timing estimate to the predetermined threshold, selecting a future symbol from the sequence of samples corresponding to the future symbol strobe, assigning the future symbol to the current symbol, which is the recovered symbol, rearranging the recovered symbols to form Pulse Code Modulated (PCM) samples of a bandlimited signal at a sample rate which is derived from the recovered symbol rate, and resampling at the sample rate of the receptor block which receives the recovered PCM samples.

Abstract: A permuted sequences combination uses a frame structure in which two sync words, each comprising M complex symbols, are appended at the frame start. One benefit is the reduction of the large variance of the timing estimation error in the conventional correlation method. In at least one embodiment, the first sync word, {right arrow over (s)}1, is a predetermined constant amplitude zero autocorrelation (CAZAC) sequence. The second sync word, {right arrow over (s)}2, is a permutation of the first such that the combination of the two received sync signal vectors perform sliding window processing where the peak occurs at the correct frame start. The permuted sequences combination can be used in both AWGN channel and multi-path environments.

Abstract: The present invention is an improved system and method for detecting the leading edge of a waveform. More specifically, the invention relates to detecting the leading edge of an ultra wideband waveform. The invention requires locking to the ultra wideband waveform at a lock reference time, and sampling the ultra wideband waveform during one or more time windows relative to the lock reference time to identify one or more leading edge candidate times based on one or more detection criterion. The ultra wideband signal is sampled at a band limited Nyquist rate that avoids aliasing within a band of interest of the ultra wideband waveform, but allows aliasing outside of the band of interest to minimize the number of samples for leading edge detection processing.

Abstract: A digital broadcast transmitting/receiving system and a signal processing method thereof that can improve the receiving performance of the system. A digital broadcast transmitter has a randomizer to randomize an input data stream which has null bytes being inserted at a specified position, a multiplexer to output a data stream formed by inserting specified known data into the position of the null bytes of the randomized data stream, an encoder to encode the data stream outputted from the multiplexer, and a modulator/RF-converter to modulate the encoded data, RF-convert the modulated data and transmit the RF-converted data. The receiving performance of the digital broadcast transmitting/receiving system can be improved even in a multi-path channel by detecting the known data from the received signal and using the known data in synchronization and equalization in a digital broadcast receiver.

Abstract: A method for identifying receipt of a sync word in a stream of signal data is provided. The method includes receiving a signal value representing an incoming bit in the stream of signal data. The method also includes inserting the signal value into a first shift register having the same length as the sync word. The method further includes calculating a bit value from the signal value. The method also includes storing the bit value into a second shift register having the same length as the sync word. The method further includes counting the number of matches between the bit values in the second shift register and the corresponding bits in the sync word. The method also includes computing a correlation of the signal data and the sync word by summing the product of each signal value in the first shift register and the corresponding bit in the sync word. The method further includes producing a normalized correlation by dividing the correlation by the energy.

Abstract: A method for performing carrier frequency offset estimation and frame synchronization is disclosed herein. In one approach, the method includes performing a first level frequency discrimination on at least one estimated channel tap to generate a frequency discriminated value; estimating a phase error from the frequency discriminated value; and, determining a predetermined frame synchronization pattern from the estimated phase error. A computer program product having code and a wireless communications apparatus for performing the method are also described herein.

Abstract: Apparatus and methods for accessing a wireless telecommunications network by transmitting a random access signal. The random access signal includes a random access preamble signal selected from a set of random access preamble signals constructed by cyclically shift selected root CAZAC sequences. The random access signal may be one or more transmission sub-frames in duration, the included random access preamble sequence's length being extended with the signal to provide improved signal detection performance in larger cells and in higher interference environments. The random access signal may include a wide-band pilot signal facilitating base station estimation of up-link frequency response in some situations. Each of the plurality of available random access preamble sequences may be assigned a unique information value. The base station may use the information encoded in the random access preamble to prioritize responses and resource allocations.

Abstract: The present invention provides a method of early starting the operation of a descrambler. The method comprises the steps of receiving a, synchronous byte of a transport packet in a group of m packets, where m is an integer, generating an alignment index to indicate a location of the synchronous byte, delivering the alignment index to the descrambler, and loading an initialization sequence to the descrambler in accordance with the alignment index and starting an operation of the descrambler.

Abstract: The present invention provides methods and systems for allowing a receiver in a (wireless) communication system to synchronize its timing and frequency subsystems in accordance with a received signal. In accordance with one aspect, a method is provided in which a relative time of arrival of sync values provided in a received signal are determined and used to align the receiver's reference signal(s) accordingly. Other aspects of the invention will become apparent from the detailed description of exemplary embodiments that follows.

Abstract: An improved Interrogator for use in a radio frequency identification system wherein at least one tag modulates a radio frequency signal by modulated backscatter operations.

Abstract: A receiving apparatus includes a first receiver, a second receiver, a received signal synthesizer connected to the first and second receivers, a synchronizing signal synthesizer connected to the first and second receivers, and a synchronization detector connected to the synchronizing signal synthesizer. In this structure, synchronization determination is performed using a synchronizing signal of either the first or second receiver, and diversity reception is performed using the received signals of the first and second receivers.

Abstract: The present invention provides a unique manner of identifying the Frame boundaries in multiple identical/non-identical Synchronization Channels (SCHs) in different sub-frames via a new sub frame position difference method. The method implements the differences between the different sub-frames carried by the SCH. The sub frame identity, and hence the frame boundary, can be identified by calculating the difference between the positions, based on time or number of slots/sub-frames or any data packets, of the two subsequent slots/sub-frames or any identical data packets.

Abstract: A system includes a first communication device and a second communication device. The first communication device includes a programmable region. The programmable region of the first communication device is programmed so that an associated signal includes a number of preamble cycles. The second communication device also can include a programmable region. The programmable region of the second communication device can be programmed so that an associated signal includes a number of preamble cycles. The number of preamble cycles can be based on a variety of factors, such as the topology or implementation of the system. In an embodiment, the number of preamble cycles is associated with a data strobe signal, and data is not read or written in response to the data strobe signal until all of the preamble cycles have been transmitted and received.

Abstract: A deserializer including a plurality of registers, a sync detector, and a lost bit storage unit. If there is a phase difference between an external input data packet and a recovery clock signal transmitted together with the data packet, the sync detector generates an activated sync detect signal. The lost bit storage unit detects a data bit of the data packet corresponding to an activation point of the sync detect signal. The deserializer recovers the data packet by combining the detected data bit with the data packet.

Abstract: A method is provided for estimating a frequency offset in a carrier signal caused by the Doppler effect. The method determines a frequency offset estimate by utilizing a multi stage estimation scheme. More specifically, the method determines the frequency offset estimate of a data frame by iteratively estimating the frequency offset by comparing different portions of the preamble. As the length of the sampled patterns varies, the frequency offset estimates vary in accuracy and range. The method may adjust frequency offset estimates that are out of range. Finally, the receiver obtains a frequency offset estimate for the data frame from a weighted combination of frequency offset estimates. This method is applicable in WiFi (IEEE 802.11a/g), WiMax (IEEE 802.16), and WAVE (IEEE 802.11p) systems.

Abstract: Disclosed is a signal processing method and apparatus in MIMO system. In a mobile communication system having a plurality of transmitting antennas, the present invention includes the steps of receiving a feedback signal including status information of at least one channel, segmenting one of the first data blocks to segment into at least one or more of the second data blocks, attaching a CRC to each of the at least one or more of the second data blocks, allocating the at least one or more second data blocks to a plurality of the transmitting antennas, respectively, and transmitting the at least one or more of the second data blocks. In a mobile communication system having a plurality of receiving antennas, the present invention includes the steps of receiving at least one data block including a CRC or dummy bits, acquiring channel status information using the CRC or dummy bits, and transmitting the channel status information.

Abstract: Disclosed is a system and a training sequence setting method for performing frame synchronization in a wireless communication system. A received signal is affected by a frequency offset due to an oscillator mismatch between the transmitter and the receiver, which is one of the main causes of performance degradation of frame synchronization. In a prior Constant Amplitude Zero Auto-Correlation (CAZAC) sequence, the larger the frequency offset becomes, the more conspicuously the performance degradation of the frame synchronization occurs. The proposed training is designed to maintain a prior CAZAC property during a differential detection so as to perform a differential detection-based frame synchronization sequence insensitive to the frequency offset. As a result of performance verification, the proposed training sequence indicates that its performance of the frame synchronization is irrespective of the frequency offset, and has a better performance than the prior CAZAC sequence and random sequence.

Abstract: A demodulation section 13 receives a TDMA-TDD based phase-modulated burst signal of mobile communications and demodulates the burst signal by a synchronous detection system (or a quasi-synchronous detection system). The demodulation section 13 includes a frequency deviation compensation section and a carrier recovery section each having a loop filter 14 with three or more stages of time constants. The time constants are switched by a selector switch 15 based on a control signal from a demodulation control section 16. This achieves quick pull-in and jitter after convergence is minimized, thereby allowing highly efficient performance of frequency deviation compensation, etc. that is required for synchronous detection (or quasi-synchronous detection) without increasing the size of circuit.

Abstract: Clear channel assessment (CCA) is a very important issue in Ultra-Wideband (UWB) systems. An effective CCA mechanism will have a large impact on the overall throughput of the communications system. It is disclosed methods and circuits to carry out CCA determinations exploiting the structure of the pulse signal either by using a moving average or by performing a cross-correlation with a locally generated signal.

Abstract: A system includes an input, a differential demodulation module, a magnitude measuring module, a summing module, and a metric generator module. The input receives input signals that include s sets of modulated sub-carriers carrying symbols, where s is an integer greater than or equal to 1. The differential demodulation module generates differentially demodulated signals based on the input signals. The magnitude measuring module measures magnitudes of real portions of the differentially demodulated signals. The summing module generates s sums, wherein each of the s sums is a sum of the magnitudes generated based on a respective one of the s sets. The metric generator module generates metrics for the symbols based on the s sums.

Abstract: A preamble detector for a plurality of streams of baseband digitized signals has a plurality of preamble processors, each preamble processor coupled to an input and generating an output. Each preamble processor has an input coupled to a first delay, the output of the first delay coupled to a second delay generating an output. The first and second delay are substantially equal to a preamble part. A first multiplier generates an output from a conjugated output of the second delay output and a first delay output. A second multiplier generates an output from a conjugated first delay output and an input stream. The first and second multiplier outputs are accumulated over an interval, and the complex output of the accumulator is formed into a magnitude, thereby generating the output of each preamble processor. The outputs of the preamble processors are summed and compared to a threshold to generate a preamble detect.

Abstract: A method for detecting a specific timing from a synchronization channel is described. A signal with a known sequence is received. Two or more correlation values between the received signal and the known sequence are calculated at two or more positions. The two or more correlation values are compared. A determination is made whether the position of the known sequence has been shifted based on the comparison. A specific timing of a synchronization channel is detected based on the determination.

Abstract: A circuit to synchronize with a data transmission includes a comparator to read a set of data within a serialized data transmission, compare the set of data to a predetermined data pattern and output a comparison result. For a serialized data transmission, the comparator receives the serialized transmission and a shift register serially coupled to the comparator to hold the data pattern. A synchronization detector receives a comparison hit vector based on the comparison result from the comparator and aligns a boundary of a data frame according to the comparison hit vector if the comparison hit vector indicates a match between the data pattern in the set of data and the predetermined data pattern. For a deserialized data transmission, each stage of a multistage shift register read a set of data from the deserialized data transmission and selectively outputs the set of data to a comparator which compares each set to a predetermined data pattern and output a comparison result.

Abstract: A method for performing symbol timing estimation is disclosed herein. In one approach, the method includes defining a search space in a plurality of estimated magnitudes of channel taps; defining a search window in the search space; and locating a symbol timing estimate index in the search space corresponding to a maximum value of an energy of the plurality of estimated magnitudes of channel taps within the search window. A computer program product having code and a wireless communications apparatus for performing the method are also described herein.

Abstract: A circuit and algorithm are disclosed for a step2 search of a three step search of synchronization channels in a W-CDMA system. A mobile terminal of the CDMA system includes an RF downconverter for receiving I and Q signals. A searcher, responsive to the I and Q signals, includes a first correlator for correlating the I and Q signals with a primary synchronization code on a primary synchronization channel, and a second correlator for correlating I and Q signals with a secondary synchronization code on a secondary synchronization channel. The correlated I and Q signals are added for each of the secondary synchronization codes. An energy calculator and a maximum energy detector use the correlated I and Q signals of both the primary and secondary synchronization channels to detect the most likely scrambling code group of secondary synchronization codes.

Abstract: The present invention provides architectures and methods which enables faster and more power efficient detection of channel parameters used by a communication system. Various parallel preamble correlator structures are able to perform searches for multiple preambles in parallel. The received samples are correlated with different delays between the samples corresponding to the different possible channel parameters that may be used by the communication system. Processing elements used in the preamble search may be shared among the parallel preamble search sections of a given architecture to reduce costs and power consumption. Decimation and filtering may also be used to reduce the interference from adjacent channels.

Abstract: Provided is a synchronization error tracking device and method. The method and system estimates and corrects the synchronization error generated by time and frequency offsets during the data transmission interval and uses a module designed for initial synchronization or channel estimation without adding a new correlation operator. Further, a combining mark value and a synchronization position value acquired during the synchronization process are used.