Abstract: A variable code-tracking loop filter in a receiver having the ability to change its parameters multiple times in response to received signals. Parameters for the code-tracking loop filter may be varied based on phase and frequency errors from an error detector. In one implementation, the code-tracking loop filter is able to repeatedly vary a single parameter, such as its received bandwidth, based on the phase and frequency errors, while in another, the code-tracking loop filter may vary two or more parameters, such as the loop bandwidth and the natural frequency.

Abstract: Methods, devices and systems are provided for word synchronizing multiple serial data bitstreams (106) with a serial framing signal (106A). Offset values (420) are determined (512) from the relative locations of predetermined data correlation values (107) stored within the data buffers during a correlation mode to indicate the amount of skew observed between the framing channel and each of serial data channels. Data received during subsequent operation of each data stream is stored a buffer (402), and the framing signal (106A) is monitored to identify a boundary between data words. When a frame boundary occurs, parallel data is extracted from the buffer using the previously-stored offset values to compensate for bit skew between the data and framing channels.

Abstract: A circuit and algorithm are disclosed for a step2 search of a three step search of synchronization channels in a W-CDMA system. A mobile terminal of the CDMA system includes an RF downconverter for receiving I and Q signals. A searcher, responsive to the I and Q signals, includes a first correlator for correlating the I and Q signals with a primary synchronization code on a primary synchronization channel, and a second correlator for correlating I and Q signals with a secondary synchronization code on a secondary synchronization channel. The correlated I and Q signals are added for each of the secondary synchronization codes. An energy calculator and a maximum energy detector use the correlated I and Q signals of both the primary and secondary synchronization channels to detect the most likely scrambling code group of secondary synchronization codes.

Abstract: A clock and data recovery circuit and method are used in a digital data communications system. The circuit and method are effectively employed for high speed, burst-mode transmission and allow rapid recovery of the clock and data signals without the need for an extended header, and notwithstanding the presence of substantial timing jitter. The method adaptively selects from among three delay times for the extraction of data by identifying a frequently recurring incoming pattern in the incoming data. The delay time is selected in a manner that insures that the same pattern is present in the reconstructed, resynchronized output data.

Abstract: A computerized system simulates a non-linear Decision Feedback Equalizer. The computerized system includes a user interface, an output port, and a controller coupled to the user interface and to the output port. The controller is configured to (i) receive electronic design automation commands from a user through the user interface, (ii) generate, as an electronic model of the non-linear Decision Feedback Equalizer, an electronic representation of a linear filter in response to the electronic design automation commands, and (iii) integrate the electronic representation of the linear filter into an electronic circuit design having other electronic representations of other electronic circuits. The electronic circuit design is externally accessible through the output port.

Abstract: Two wireless local area networks exhibiting different characteristics link portable or mobile computer devices. An infrastructure network comprising radio base stations, and at least one portable computer device make up the first wireless network, which communicates using spread spectrum frequency hopping communication. A second local area network supports radio communication between a portable computer and peripheral devices with built-in transceivers. The networks use a reservation access protocol that facilitates frequency hopping synchronization, supports adaptive data rate selection based on communication quality, and prevents interference between the wireless networks. In a premises LAN, an infrastructure network comprises radio base stations and a backbone LAN. A higher-power LAN using frequency hopping comprises the infrastructure network and at least one mobile computing device.

Abstract: A method is disclosed, including identifying a preamble in a frame, where the preamble has a preamble length 1. M data items received in succession are stored. The m data items once divided into n portions, where the data items in each portion have respectively been received at successive times and where m and n are natural numbers and the following applies to m and n: m>n, m>1, n>1. The n portions are respectively correlated to the expected values to form component correlation results. Delaying the component correlation results, with at least two component correlation results being delayed by different lengths. The method also includes combining the delayed component correlation results to form a total correlation value. The total correlation value is used to determine whether the m received data items contain the preamble of a frame.

Abstract: Methods, apparatus, systems and devices are implemented according to a number of embodiments. According to one such embodiment, a method of synchronizing a receiver to a timing and carrier frequency of a communication system is implemented. A set of predetermined possible synchronization patterns is detected in a received signal. Timing and structure information is generated specifying the occurrence of detected ones of said predetermined set of possible synchronization patterns in said received signal. Channel coefficient estimations of different receiving channels are derived from the timing and structure information. A carrier frequency offset is determined for the received signal based on a comparison of predetermined ones of said derived channel coefficient estimates.

Abstract: Detecting a symbol of interest comprises despreading a received signal to obtain despread values corresponding to the symbol of interest and to one or more interfering symbols, combining the despread values to generate combined values for the symbol of interest and the interfering symbols, computing spreading waveform correlations between the spreading waveform for the symbol of interest and the spreading waveforms for the interfering symbols, computing interference rejection terms representing the interference present in the combined value for the symbol of interest attributable to the interfering symbols based on the spreading waveform correlations, and generating an estimate of the symbol of interest by combining the combined values with the interference rejection terms. The interference rejection terms are computed by scaling the spreading waveform correlations by corresponding signal powers and compensating the estimates for noise.

Abstract: The recognition of a frame synchronization pattern or unique word of a received signal may be enhanced using a data-aided estimator of the signal-to-noise ratio (SNR) together with a correlation detector of the unique word to be received. Detecting a frame synchronization pattern or a unique word in a received signal, the SNR is estimated on the received signal with a data-aided SNR estimator using the unique word to be received. If the estimated SNR exceeds a certain threshold, an eventual recognition of the unique word established by a correlation correlator of the receiver is considered reliable. Comparing the SNR with the threshold may be carried out either before or after the correlator has processed the unique word.

Abstract: A coder is fed with pre-coded data such that the absolute value of the RDS of the code words as produced by the coder is limited. This is achieved by ensuring that in a group of 2 code words the RDS of the first code word is compensated by the RDS of the second conde word. The RDS at the end of the second code word is then zero and the excursions of the RDS from the start of the first code word until the end of the second code word are limited because there are only a limited number of bits that can contribute to an increase of the absolute value of the RDS. This principle can easily be applied to the 17PP coder.

Abstract: The present invention relates to a method for measuring radio channel quality in a radio communication system. In the method a modulated signal is received over a communication channel. The modulated signal has been modulated by using modulation parameters. A decoder decodes (305) the modulated signal and forms decoded data. The decoder creates (306) a decoder performance indicator (PS) that depends on the decoded data. Then a radio channel quality indicator (RCQI) is created, the radio channel quality indicator being essentially independent of the modulation parameters.

Abstract: Methods and systems provide approaches to start code emulation prevention at a granularity higher than the bit level. By operating at a level other than the bit level, processing capability requirements on both the encoder and decoder side can be reduced. In accordance with one or more embodiments, a start code emulation prevention method looks for data patterns relative to fixed-size data portions larger than single bits. When a particular pattern is found, start code emulation prevention data is inserted to prevent start code emulation. The inserted data is larger than a single bit and, in some embodiments, comprises a byte. When a decoder decodes data that has had start code emulation prevention data inserted, it can easily identify legitimate start codes and then can remove the start code emulation prevention data to provide the original data that was protected.

Abstract: A method is provided for frequency acquisition, particularly for initial frequency acquisition, pursuant to a known synchronization sequence for synchronizing a mobile communications device having a local oscillator with previously known transmit frequencies of a base station that transmit in a known channel raster with defined frequency points within a band, wherein the method includes the steps of determining the inband power of the known synchronization sequence via a sensor by scanning a frequency band, performing coarse determination of the local power maximum of the inband power and, thus, of the received carrier frequency over the scanned frequency band, producing a presumed channel frequency at which the base station is transmitting on the basis of knowledge of the channel raster of the transmit frequencies of the base station, performing fine determination of the received carrier frequency by comparison with the known synchronization sequence, and correcting the frequency deviation of the local oscil

Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.

Abstract: In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.

Abstract: An approach is provided for supporting carrier synchronization in a digital broadcast and interactive system. A carrier synchronization module receives one or more signals representing a frame that includes one or more overhead fields (e.g., preamble and optional pilot blocks and one or multiple segments separated by pilot blocks). The module estimates carrier frequency and phase on a segment by segment basis and tracks frequency between segments. Carrier phase of the signal is estimated based upon the overhead field. Estimates carrier phase of random data field are determined based upon the estimated phase values from the overhead fields, and upon both the past and future data signals. Further, the frequency of the signal is estimated based upon the overhead fields and/or the random data field. The above arrangement is particularly suited to a digital satellite broadcast and interactive system.

Abstract: Provided are a method for measuring characteristics of a path between nodes by using active testing packets based on priority, i.e., an inter-node path characteristic measuring method, which can measure and provide characteristics of a generated node, when an inter-node data transmission path is generated based on Multi-Protocol Label Switching (MPLS) to provide a path with satisfactory transmission delay, jitter and packet loss that are required by a user, and to provide a computer-readable recording medium for recording a program that implement the method. The method includes the steps of: a) synchronizing system time of the nodes with a global standard time; b) forming each testing packet; c) registering frame sequence and the global standard time during transmission; and d) calculating transmission delay time, jitter and packet loss by using time stamp and packet sequence information of a frame received by the destination node and transmitting the result to the management system.

Abstract: A method for identifying receipt of a sync word in a stream of signal data is provided. The method includes receiving a signal value representing an incoming bit in the stream of signal data. The method also includes inserting the signal value into a first shift register having the same length as the sync word. The method further includes calculating a bit value from the signal value. The method also includes storing the bit value into a second shift register having the same length as the sync word. The method further includes counting the number of matches between the bit values in the second shift register and the corresponding bits in the sync word. The method also includes computing a correlation of the signal data and the sync word by summing the product of each signal value in the first shift register and the corresponding bit in the sync word. The method further includes producing a normalized correlation by dividing the correlation by the energy.

Abstract: A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by synchronizing an initialization training sequence to a reset deassertion. Specifically, the proposal facilitates response determinism from the DUT by synchronizing training sequences and subsequently synchronizing flit transmission to reset assertion as sampled by reference clock.

Abstract: A modular, numerical control having low-jitter synchronization includes a main computer and at least one controller unit which, starting from the main computer, are interconnected by serial data-transmission channels in the form of a series circuit. The at least one controller unit includes a first receiver unit for receiving a serial data stream arriving from the direction of the main computer, and a first transmitter unit for outputting a serial data stream. Also provided in the at least one controller unit is a clock recovery unit which derives a synchronous clock signal from the serial data stream arriving at the first receiver unit, and supplies it to the first transmitter unit which uses it as a transmission clock signal, so that the serial data stream arriving at the first receiver unit and the serial data stream output by the first transmitter unit are coupled to each other in phase-locked manner.

Abstract: A semiconductor integrated circuit includes a sampling unit, a delay unit, a first operating unit and a second operating unit. The sampling unit samples an input signal supplied from an external circuit in synchronization with a clock signal, and outputs the sampled input signal as a first signal. The delay unit delays the first signal in synchronization with the clock signal, and outputs the delayed first signal as a second signal. The first operating unit operates whether a signal level of the input signal is sustained equal to or longer than a predetermined period based on the first and second signals, and outputs an output signal in synchronization with the clock signal when the signal level of the input signal is sustained equal to or longer than the predetermined period. A signal level of the output signal is sustained equal to or longer than the predetermined period. The second operating unit asynchronously controls the sampling unit based on the input signal and the output signal.

Abstract: A communication system for pulse based communication using a sequence acquisition system using the correlation method in UWB communications which generates a pulse detection signal differing in phase by exactly a predetermined period (?) from the transmission information of a pulse signal of a predetermined period at the transmission side and reception side, uses the pulse detection signal to establish synchronization at the reception side, then generates transmission information at the reception side by making its phase different by exactly a predetermined time from the synchronized pulse detection signal so as to establish synchronization between the reception signal and the transmission information, whereby it is possible to enable synchronization acquisition and shorten the synchronization acquisition time without complicating the hardware and even without the presence of information in the transmission signal.

Abstract: A packet preamble search method is disclosed for locating a packet preamble with multiple predetermined patterns of a regular form within a received transmission signal with sequential multiple patterns. The pattern of the received transmission signal and the predetermined pattern of the packet preamble have the same length with even bits. The pattern of the transmission signal is sequentially compared with the predetermined pattern. A hit count is increased and a miss count is reset when the pattern of the transmission signal matches the predetermined pattern. The miss count is increased and the hit count is decreased when the pattern of the transmission signal does not match the predetermined pattern. The hit count and the miss count are reset when the hit count is less than or equal to the miss count. An address matching procedure is activated when the hit count exceeds or is equal to a threshold value.

Abstract: A frame synchronous circuit operable in a dedicated short-range communication system, applicable to several modulation schemes, includes a UW detector for detecting a UW word from received data, an operation setting register group for specifying the operations of an on-board unit, a synchronous manager for controlling synchronization, an unlimited synchronization continuation register for maintaining the unlimited continuation of the synchronization, and an FCMC data analyzer for analyzing FCMC data. The operation setting register group can control synchronization by using not only operational information obtained from the FCMC data but also another operational information retrieved from an input device such as a CPU or terminal connected to the on-board unit. Consequently, debug and test operations can be performed without receiving any FCMC data.

Abstract: The present invention provides a method and apparatus for detecting and decoding data. The method comprises: receiving a set of data signals from an external data source; detecting a size of said received set of data signals; decoding said received set of data signals; extracting a destination address from said set of data signals; comparing said destination address extracted from said data signals to a known data value; determining whether said received data signals should be received by a host circuitry based upon said comparison of said destination address extracted from said data signals to a known data value; generating at least one status signal alerting said host circuitry of said determination that said received data signals should be received by said host circuitry; and waking up said host circuitry upon a determination that said received set of data is addressed to said host circuitry.

Abstract: A receiver includes a baseband processor for selecting a set of demodulation processing delays for received signal demodulation from a larger set of candidate delays. In one embodiment, the baseband processor selects the set of demodulation processing delays by calculating at least one metric for each demodulation processing delay in the set of candidate delays, iteratively reducing the set of candidate delays by eliminating one or more demodulation processing delays from the set as a function of comparing the metrics, and setting the processing delays for received signal demodulation to the candidate delays remaining after reduction. In a Generalized RAKE (G-RAKE) embodiment, the metric corresponds to combining weight magnitudes associated with G-RAKE finger delays. In a chip equalizer embodiment, the metric corresponds to coefficient magnitudes associated with equalization filter tap delays.

Abstract: An Orthogonal Frequency Division Multiplexing (OFDM) synchronization module includes a window generator module, a symbol timing estimator module, and a reliability metric calculator. The window generator module generates a sampling window that bounds a plurality of samples of OFDM symbols. The symbol timing estimator module generates an estimated symbol timing from the plurality of samples before a fast Fourier transform operation is performed on the plurality of samples. The reliability metric calculator calculates a reliability metric for the estimated symbol timing based on the estimated symbol timing. The window generator module changes at least one parameter of the sampling window based on the reliability metric.

Abstract: Methods and apparatuses for dynamically adjusting sync windows are described. A default sync window is set; a data signal is input; detecting if parts of the data signal within the sync window form a sync pattern; accumulating a count of the sync pattern within and without the sync window; and reducing the sync window when the count of sync pattern within the sync window achieves a first threshold value, and increasing the sync window when the count of the sync pattern outside the sync window achieves a second threshold value.

Abstract: A synchronization determination method includes: a synchronization determining step of determining whether or not synchronization has been successfully performed by detecting a synchronous pattern from the demodulated data input as a data stream; a synchronization probability determining step of determining whether or not there is a probability that synchronization is successfully performed using the progress of detecting a synchronous pattern in the synchronization determining step; and a synchronization determination discard step of discarding a determination in the synchronization determining step when it is determined in the synchronization probability determining step that there is no probability that synchronization is successfully performed, and passing control to the process performed when it is determined in the synchronization determining step that synchronization has not been successfully performed.

Abstract: A communications network and method thereof include a base station controller configured to provide a repetition period of a primary synchronization channel to be equal to a predetermined integer value times a scrambling code length of the scrambling code of a common pilot channel. A user equipment in the network is configured to search for a known sequence comprising the primary synchronization channel to select a cell and a corresponding sub-frame/symbol timing from the selected cell.

Abstract: Disclosed is a channel estimator and a method for changing a coefficient of an IIR filter depending on a moving speed of a mobile communication terminal. In the channel estimator, a coefficient changing unit receives I and Q signals from a current base station, and selects a coefficient of the IIR filter optimized depending on the moving speed of the current mobile communication terminal. The coefficient changing unit sets the selected coefficient of the IIR filter to the IIR filter of the channel estimator. Accordingly, it is possible to prevent the performance degradation of the channel estimator caused by the speed of the mobile communication terminal.

Abstract: A receiving device (50) is provided to allow appropriate clock regeneration even for a VBR TS when a stream including video and audio data, such as an MPEG2 TS, is transmitted or received in real time through a network having jitter. When the received packet data is stored in a memory (53) and the packet data is output in accordance with time information added to the received packet data, a clock frequency deviation between a sending device and a receiving device is calculated on the basis of the integration result of the amount of the received packets temporarily stored in the memory (53), the number of the received packets which have been processed, and the measurement result of the integration time used for integrating the amount of the received packets. A read timing offset of the received packet is obtained on the basis of the calculation result of the clock frequency deviation.

Abstract: A special data including communication wire continuous dominant levels of a number of N more than the transceiving bit number of n of communication wire continuous dominant levels, set in a character as one unit of communication data, can be transceived by a widely-used serial communication interface such that a predetermined transmission rate is changed to n/N times the transmission rate only when the special data is transmitted, whereby the special data can be easily transceived at a low cost.

Abstract: Systems and methods are disclosed for detecting framing data in a telecommunications signal. In one embodiment, a frame synchronizer circuit is provided that includes an interface for receiving bits of a telecommunications signal and storage for storing a framing state for the bit positions in the frame, the framing state for a given bit position indicating whether that bit position is a potential holder of the frame synchronization pattern. The frame synchronizer circuit also contains a state update function that determines the current-state for each bit position based on the bit position's previous state, and the value of the most recently received bit in that bit position. The encoding scheme makes use of shorter bit length symbols to represent statistically more frequently occurring states. In one embodiment, a single code word is used to record the state of a sequence of consecutively occurring bit positions that share the same state.

Abstract: The present invention provides an event edge synchronization system and a method of operating the same. In one embodiment, the event edge synchronization system includes: (1) a first clock zone device configured to generate an event signal based upon a first clock rate, (2) a second clock zone device configured to operate at a second clock rate, which is asynchronous with the first clock rate and (3) a synchronous notification subsystem configured to receive the event signal, synchronize the event signal to the second clock rate based upon an edge transition of the event signal and the second clock rate, and generate a synchronous notification signal therefrom.

Abstract: A synchronizing apparatus comprises a normal lock synchronization detecting unit for detecting synchronization by detecting from demodulated data a synchronization pattern in a normal lock state, and a pseudo lock synchronization detecting unit for detecting synchronization by detecting from the demodulated data a synchronization pattern in a pseudo lock state.

Abstract: A frame synchronization method is disclosed. The method comprises correlating a stream with a pattern to generate a correlated result c(t). A first peak and a second peak are selected from the correlated result c(t), wherein the first peak is the peak with highest amplitude, and the second peak is the peak occurring later than the first peak with the second highest amplitude. The peak ratio of the two peaks is computed, and the position of the frame boundary is determined according to the ratio.

Abstract: A synchronization extraction apparatus for a communication system and a method thereof are disclosed. A frame synchronization is obtained in a manner that the sum of an input signal and a delay signal is obtained without obtaining a simple correlation value between the input signal and the delay signal, and then a correlation value between a summed signal and the delay signal is obtained. The synchronization extraction apparatus and method can reduce the implementation complexity and power consumption in obtaining the frame synchronization, and thus increase the battery cycle of a terminal provided with the synchronization extraction apparatus or method.

Abstract: A frequency control device capable of detecting a frame sync pattern and generating a frequency information accurately even if a reproduction signal is not zero-crossed, and an information reproduction apparatus having the same, which includes an oscillation circuit outputting a clock having a frequency corresponding to a control signal; a converter sampling an input analog signal having a predetermined pattern based on the clock and converting the same to a digital signal; and a frequency detection device detecting an object to be a sync pattern from a changing trend of the digital signal, generating a frequency information for controlling a reproduction clock based on the detected object to be the sync pattern, and outputting the same as the control signal to the oscillation circuit.

Abstract: A frame format decoder (22) and training sequence generator (24) for determining the frame format of received data which is compliant with the IEEE 802.1 1b standard for wireless local area networks, and for providing a training sequence for an adaptive equalizer (16). The received signal is first despreaded, demodulated and descrambled, so that the SYNC field is reconstructed, and then a counter 32 counts the number of consecutive bits having the same polarity or logic value until N such bits are counted (where N is an integer greater than 1). The polarity or logic value of the N counted bits enables the decoder (22) to determine whether the frame format is long or short. A training sequence, being a copy of the transmitted SYNC field eventually followed by an SFD field, is also generated for use by an adaptive equalizer (16).

Abstract: A synchronism pattern detecting timing recorder (20) records a synchronism pattern detecting timing at which a synchronism pattern is detected in reception data, a synchronism decider (12) collates the reception data with reference data to decide whether or not the reception data is consistent in phase with the reference data, and a timing generator (22) operates, when the synchronism decider (12) gives a decision for inconsistency in phase, for a match between the synchronism pattern detecting timing recorded in the synchronism pattern detecting timing recorder (20), as a subsequent one, and a timing of a synchronism pattern of the expectation data, and the subsequent synchronism pattern detecting timing in record is used to render the phases consistent, allowing for a rapid synchronization to be obtained, without the need of waiting a detection of synchronism pattern, even with an inconsistency in phase due to a false synchronism pattern.

Abstract: A deterministic finite state machine is operated to detect any one of a plurality of digital signatures each corresponding to a succession of characters and each defined by a sequence of states in the state machine. The machine is organized such that for each state after the first in any sequence there are not more than two allowed exit transitions of which one is to a default state. Input characters are examined to determine a transition from a current state of the machine to a next state. When the machine responds to an input character to perform a transition to the default state, the input character is re-examined to determine the next state of the state machine. The reduction in transitions saves considerable space in memory.

Abstract: A communication apparatus (400) capable of supporting two bidirectional communication protocols is connected to a single bidirectional signal line and a controller (414). Software processes of the controller (414) include only processes of requesting transmission, setting transmission data, and decoding reception data. All communication processes, such as generation of a waveform during transmission, sampling of data during reception, decoding of a reception address, and the like, are hardware processes of the communication apparatus (400). In accordance with a control of a state determining circuit (405), the generation of a waveform during transmission is controlled by a transmission control circuit (409) and a data output circuit (111), while the sampling of data during reception and the decoding of a reception address are controlled by a waveform timing check circuit (407) and a reception control circuit (410).

Abstract: A data transfer control device includes: an encoder circuit which performs encoding data and generation of a special code; a parallel/serial conversion circuit which converts parallel data from the encoder circuit to serial data; and a transmitter circuit which receives the serial data and transmits the special code and the data through the serial signal line. The transmitter circuit outputs an idle signal, logical level of which is continuously fixed at a first logical level in units of a given number of bits or more to the serial signal line as a signal indicating an idle state. The encoder circuit suspends operation after an indication that there is no transmission data by a transmission data valid/invalid signal from an upper layer circuit.

Abstract: Detecting a boundary within a transmitted packet is disclosed. A first symbol of the transmitted packet is received in a band. A second symbol of the transmitted packet is received in the band. The first and second symbols are compared. The boundary within the transmitted packet is detected based at least in part on the comparison of the first symbol and the second symbol and the band.

Abstract: An RF receiver comprises a signal processor arranged to perform a method of decoding data contained within a signal that comprises a set of slots, at least one said slot comprising a preamble portion and a payload portion and being transmitted at a predetermined transmission frequency. The signal processor is arranged to perform a first process to derive timing data from the preamble portion and perform a second process to extract information from the payload portion, the second process being triggered from said timing data derived from the first process. The preamble portion comprises at least a first sequence of data and a second sequence of data, and the second sequence is the inverse of the first sequence. In preferred embodiments the first process comprises identifying a transition between said first and second sequences of data and deriving said timing data from the identified transition.

Abstract: A data processing apparatus receives a message containing a sync break interval with a unique bit pattern and a sync field interval identified by the sync break interval. A timing property of the sync field interval specifies the length of bit periods of the message. A clock source circuit supplies a sampling clock signal to define time points for sampling bits from the message. The clock source circuit adapts a frequency of the sampling clock signal to the timing property of the sync field interval.

Abstract: A transmitter comprises a frequency utilization status detector configured to detect the utilization status of an allocated frequency band based on a received signal, a symbol placement determination unit configured to determine placement of pilot symbols based on the detected status of frequency utilization, and a symbol placement unit configured to place the pilot symbols according to the determined symbol placement.

Abstract: A method (60) and apparatus process video in a multiple encoder system by identifying (61) those frames that were originally encoded as anchor frames in the first encoder and ensuring that a second encoder encodes (65) these identified frames as anchor frames rather than bidirectional frames or non-anchor frames. In addition, the second encoder identifies (62) those frames that were originally encoded as non-anchor frames in the first encoder and encodes (66) the non-anchor frames, such as bidirectional frames, as non-anchor frames during the second encoding process. Once the anchor and non-anchor frames are identified, a frame-type pattern is determined (63) by the first encoder and synchronizes (64) the second encoder to the frame-type pattern.