Abstract: A charge coupled device includes a plurality of first CCD shift-registers transferring charge signals in parallel and a second CCD shift-register receiving the charge signals from the first CCD shift-registers for a parallel-serial coversion, the second CCD shift-register being connected to the first CCD shift-registers through barrier regions covered with electrodes in the second CCD shift-register.

Abstract: In dynamic memories, generally a fluctuation of 10% of the nominal value of the supply voltage is allowed. Since, when reading, the input gate is applied to the supply, this fluctuation in the supply results in 20% of fluctuation in the charge packet formed below the input gate. In order to eliminate this fluctuation and hence to increase the permitted interference margin for other interference sources, a voltage stabilization circuit is arranged between the supply voltage and the input gate so that the fluctuation in the supply also occurs at the source zone, as a result of which the size of the charge packet becomes independent of the supply. For the voltage stabilization circuit, use may advantageously be made of a band gap reference.

Abstract: A transistor (14) having a plurality of sub-transistors (26a-f) includes a voltage controlling device (45). The voltage controlling device induces a current through an elongated gate (24) producing a voltage drop across the elongated gate (24) by providing a path between one end of the gate and ground (32). The voltage drop across the elongated gate (24) sequentially reduces the gate voltage present at each of the sub-transistors (29a-f), thereby reducing the amount of current which the sub-transistors (29a-f) can conduct. The voltage controlling circuit (45) gradually reduces the current through the elongated gate (24), thereby increasing the amount of current through the sub-transistors (29a-f). The time interval over which the conductive device induces a current through the elongated gate (24) can be adjusted by positioning the connection to the gate of a transistor (62) along the elongated gate (24).

Abstract: A step-up circuit is comprised of plurality of charge pumping circuits connected in parallel to an output line. Each charge pumping circuit is activated by a pair of mutually opposite clock signals to produce a higher output voltage than its power source voltage. The clock signals applied to the charge pumping circuits are out of phase with respect to one another such that a stable output of higher voltage can be obtained.

Abstract: A two phase shift register comprises four serial registers each having an input section, a transfer section, and a lead-in section disposed between the input section and the transfer section. The input sections provide respective sequences of charge samples, the four sequences being offset in phase relative to each other by 90.degree. within the cycle of a clock signal. At least one of the serial registers comprises a first lead-in gate pair and a second lead-in gate pair over the lead-in section, the second lead-in gate pair being between the first lead-in gate pair and the transfer section. The first lead-in gate pair and the second lead-in gate pair are each driven at the frequency of the clock signal, the drive signal applied to the second lead-in gate pair being retarded in phase relative to that applied to the first lead-in gate pair by 90.degree. within the cycle of the clock signal.

Abstract: The semiconductor devices include a semiconductor substrate, a first CCD region formed at the surface of said substrate, and a second CCD region having a side connected to said first CCD. A channel region of the first CCD region has a different channel potential at a latter part of the end transfer electrode corresponding to the portion of the first CCD region connected to the second CCD region.

Abstract: A charge transfer device, suitable for use, for example, in a solid state imager device, having a floating gate electrode in a charge detecting section, a protruding portion provided in at least one of the floating gate electrodes or a gate electrode arranged adjacent to the floating gate electrode, wherein the floating gate electrode and the gate electrode arranged adjacent to the floating gate electrode overlap each other at the protruding portion within an insulating layer, and whereby the parasitic capacitance associated with the floating gate electrode is decreased and the charge voltage converting gain is increased, rendering it possible to obtain an image signal with a good signal/noise ratio, when the charge transfer device is used for a solid state imager device.

Abstract: The invention relates to a charge transfer device (CTD) having two or four phases, for which the speed of transferring the stored charges is increased by means of self-induction members connected to each of the clock areas of each memory element so that the capacitive impedance presented initially to the clock signal generator by the CTD becomes a substantially resistive impedance. Such a charge transfer device having an increased transfer speed is used in digital oscilloscopy or in systems for handling pictures.

Abstract: The invention pertains to a charge transfer shift register provided with a device for voltage sensing using a floating-potential diode. Towards that end of the register which is located on the floating-potential diode side, the width of the charge transfer channel diminishes gradually and symmetrically with respect to the longitudinal axis of the register, and the electrodes have a shape which is all the more similar to that of a ring sector as they are close to the floating-potential diode. Thus, the path followed by the charges which leave it up to the floating electrode are made substantially uniform for each of these electrodes, whether the charges leave the electrode near the edges of the channel or near the longitudinal axis of the register.

Abstract: An analog multiplexing device using charge transfer devices has as many charge transfer multiplexing registers R'i as there are input signals, at the frequency F.sub.e, to be multiplexed, all of these registers preferably having the same length, and a single output register, the first stage of which is connected by a connection to the respective stages with levels i of the registers R'i, i=1 to n, enabling the reading by image charges of the input charges. The transfer into the successive stages of the multiplexing registers is done at a frequency nF.sub.e just as the transfer of the image charges read by the read connection in the output register stages.

Abstract: A transistor (14) having a plurality of sub-transistors (29a-f) includes a voltage controlling device (45). The voltage controlling device induces a current through an elongated gate (24) producing a voltage drop across the elongated gate (24) by providing a path between one end of the gate and ground (32). The voltage drop across the elongated gate (24) sequentially reduces the gate voltage present at each of the sub-transistors (29a-f), thereby reducing the amount of current which the sub-transistors (29a-f) can conduct. The voltage controlling circuit (45) gradually reduces the current through the elongated gate (24), thereby increasing the amount of current through the sub-transistors (29a-f). The time interval over which the conductive device induces a current through the elongated gate (24) can be adjusted by positioning the connection to the gate of a transistor (62) along the elongated gate (24).

Abstract: The present invention enables improved response time in a linked cell discharge detection device by providing additional discharge paths when indicated to speed discharge of circuit nodes in a plurality of detection cells. A circuit node is periodically precharged by connection to a voltage source. This node is selectively discharged in accordance with at least one input signal. An output device connected to the circuit node generates an output indicative of the state of the charge on the circuit node. An additional discharge device which is responsive to the output device provides an additional discharge path when the output signal indicates a charge on the circuit node less than a predetermined magnitude. This additional discharge path speeds up the complete discharge of the circuit node.

Abstract: An MOS transistor circuit for precharging parasitic capacitances C.sub.1 -C.sub.8 associated with a plurality of parallel data transfer bus lines 1-8 under the control of a clock signal .phi.. Each bus line is pulled up to an "H" state through associated MOS transistors T.sub.1 -T.sub.8, and only selected bus lines are thereafter pulled down to the "L" state pursuant to a bit transfer operation. The circuit is also provided with a series of MOS transistors T.sub.11 -T.sub.17 coupled across the adjacent bus lines such that the precharging of the discharged bus lines is contributed to by charging paths associated with non-discharged lines, to thereby shorten the overall precharging time and equalize the charge potentials.

Abstract: A charge coupled device (CCD) analog shift register in a two-channel serial-parallel-serial (SPS) structure operating in a fast-in/slow-out (FISO) mode for high speed signal acquisition and temporary storage of a plurality of samples. The two CCD arrays are clocked simultaneously, and the input analog signal is demultiplexed to the two arrays. Additional transfer electrodes are provided at the input of one of the arrays, and the other array is provided with a sampling clock which is 180.degree. out of phase with the sampling clock of the first array; two consecutive samples of the input signal are taken during each transfer clock cycle. All signal samples are clocked through the arrays simultaneously and appear at the output at the same time.

Abstract: Programmable signal processing apparatus for multiplying a sampled analog signal by a multiple bit digital word coefficient. All signal processing operations are accomplished by the splitting, routing and combining of charge packets formed in a charge domain device.

Abstract: A method and apparatus for frequency conversion comprising sampling an input signal having a first frequency with first time delays between samples in an input delay line, and distributing the samples of the input signal in sequence to an output delay line with different time delays between samples than the first time delays, to generate an output signal of different frequency than the input signal.

Abstract: A switched capacitor filter is designed utilizing two switched capacitor charge pumps connected in series. These two charge pumps operate with different clock frequencies thereby allowing charging of a storage capacitor at a higher frequency, thereby decreasing incremental voltage steps during the charging of the storage capacitor, resulting in the generation of a smoother exponential voltage rise.

Abstract: A method and device in which both positive and negative signal charges can be transferred from a first capacitance to a first point via a transistor circuit which exhibits a threshold level. For this purpose the first capacitance contains a reference charge with a positive or a negative polarity. First, the voltage on the first point is switched so that the first capcitance is charged from said first point and subsequently so that the first capcitance discharges towards the first point to its reference charge, which corresponds to said threshold level, in such a way that the net charge transfer from the first capacitance to the first point is equal to the positive or negative signal charge and the charge on the first capacitance is restored to a reference level.

Abstract: A filter utilizing charge transfer devices for providing recursive transfer functions is described. The filter includes a circular charge transfer shift register having an even number N of stages, greater than two, a first charge transfer shift register, and a second charge transfer shift register. A first input stage is unidirectionally coupled to the first stage of the first shift register and is also bidirectionally coupled to the N.sup.th stage of the circular shift register. A second input stage is unidirectionally coupled to the first stage of the second shift register and is also bidirectionally coupled to the (N/2).sup.th stage of the circular shift register. A first input sequence of packets of charge representing positive weight components of a signal is applied to the first input stage and a second input sequence of packets of charge representing negative weight components of the signal is applied to the second input stage. All three shift registers are clocked at the same frequency.