Abstract: The multilayer wiring board is provided with a lower layer wiring (8), and an upper layer wiring (10) formed on the lower layer wiring (8) through an interlayer insulating layer (9). On the interlayer insulating layer (9), a contact hole (11) is provided for interconnecting the upper layer wiring (8) with the lower layer wiring (10). A region surrounded by an inner wall (13) which forms the contact hole (11) is permitted to have a linewidth region wherein a wide line region (13A) and protruding regions (13B, 13C) as regions having different linewidths are connected. Thus, film thickness distribution of an ink baked product (12) formed at the contact hole (11) rises at the protruding regions (13B, 13C), and highly reliable multilayer interconnection can be performed between the lower layer wiring (8) and the upper layer wiring (10).

Abstract: Part or whole of an electroless gold plating film of a plated film laminate including an electroless nickel plating film, an electroless palladium plating film and an electroless gold plating film is formed by an electroless gold plating using an electroless gold plating bath including a water-soluble gold compound, a complexing agent, formaldehyde and/or a formaldehyde-bisulfite adduct, and an amine compound represented by the following general formula R1—NH—C2H4—NH—R2 or R3—(CH2—NH—C2H4—NH—CH2)n—R4. The method of the invention does not need two types of baths, a flash gold plating bath and a thick gold plating bath for thickening. Gold plating films of different thicknesses suited for solder bonding or wire bonding can be formed using only one type of gold plating bath.

Abstract: A display apparatus and a method for manufacturing a parallax barrier touch board are disclosed. The display apparatus comprises a display panel and the parallax barrier touch board. The method for manufacturing the parallax barrier touch board comprises the following steps: forming a barrier layer on a substrate, wherein the barrier layer includes a plurality of parallax barriers; and forming a touch sensing circuit layer on the parallax barrier.

Abstract: To provide a polishing pad which is insusceptible to clogging of groove with abrasive particles and grinding dusts during polishing, and leads to little decrease in polishing rate even after long-term continuous use. A polishing pad of the present invention has a polishing layer formed of polyurethane resin foam having fine-cells, and asperity structure formed in a polishing surface of the polishing layer, and is featured in that the polyurethane resin foam is a reaction cured product between isocyanate-terminated prepolymer containing high-molecular-weight polyol component and isocyanate component, and a chain extender, and contains a silicon-based surfactant having combustion residue of not less than 8 wt %.

Abstract: A lead frame comprises: a base metal layer; a copper plating layer, including one of a copper layer and an alloy layer including a copper, configured to plate the based metal layer to make a surface roughness; and an upper plating layer, including at least one plating layer including at least one selected from the group of a nickel, a palladium, a gold, a silver, a nickel alloy, a palladium alloy, a gold alloy, and a silver alloy, configured to plate the copper plating layer.

Abstract: A method and apparatus for resisting ballistic impact including an outer energy absorbing assembly having a plurality of interconnected fibers, and a barrier positioned behind the outer energy absorbing assembly. A movement restraint is positioned behind the barrier and a dampener is positioned intermediate the barrier and the restraint.

Abstract: A method comprises providing a bottom electrode, depositing, on the bottom electrode, an active material comprising a first structural portion having an absorption peak at a UV wavelength, wherein such first structural portion is photo-activatable at such wavelength and which is constituted by monomers or oligomers that, when irradiated at said wavelength, undergo a photo-polymerization and/or photo-cross-linking reaction, or constituted by a polymer that at a UV wavelength undergoes a photo-degradation reaction, and a second electrically active or activatable structural portion which is substantially transparent to such predetermined UV wavelength; exposing a portion of the active material, through a photomask, to UV radiation having such UV wavelength, with photo-activation of the exposed portion of such film; selectively removing either the exposed photo-activated portion or the non-exposed portion, with exposure of a respective portion of the bottom electrode; depositing a head electrode.

Abstract: A ceramic compact is provided having a patterned conductor is obtained by coating the patterned conductor with a slurry and then hardening the slurry. The slurry is prepared by mixing a thermosetting resin precursor, a ceramic powder, and a medium. In the ceramic compact, an isocyanate- or isothiocyanate-containing gelling agent and a hydroxyl-containing polymer are reacted and hardened to produce a thermosetting resin. The hydroxyl-containing polymer is preferably a butyral resin, an ethylcellulose-based resin, a polyethyleneglycol-based resin, or a polyether-based resin.

Abstract: Contact printing can be used to form electrically active micro-features on a substrate. An ink formulation containing an oxide precursor is used to form the micro-features, which are heat cured to form oxides. Various precursors are illustrated which can be used to form conducting, insulating, and semiconductor micro-features.

Abstract: A method of manufacturing a structure, including forming a composite film composed of a coating film and an organic or inorganic film on top of a substrate by forming the coating film on the surface of a template provided on top of the substrate; forming the organic or inorganic film on the surface of the coating film, and removing a portion of the organic or inorganic film and a portion of the coating film; forming a second coating film on the surface of the composite film; forming an organic coating film on the substrate that covers the second coating film; removing a portion of the second coating film; and forming a structure composed of a metal or metal oxide later on the substrate by removing all residues left on the substrate except for the coating film and the second coating film.

Abstract: A wiring substrate includes a substrate containing a carbon material, a first insulating layer formed over the substrate, an interlayer formed over the first insulating layer, the interlayer including a metal plate having a smaller coefficient of thermal expansion than the first insulating layer while having a greater elastic modulus than the first insulating layer, and a second insulating layer formed over the interlayer.

Abstract: A method of synthesizing doped semiconductor nanocrystals.

Abstract: A touch screen touch screen display includes a bottom conductor layer coupled to a top conductor layer. The bottom conductor layer extends beyond the top conductor layer adjacent the top conductor layer, exposing a region of the bottom conductor layer. One or more manually actuatable components (e.g., buttons) are coupled to the region of the bottom conductor layer. The bottom conductor layer may include a substrate (such as a polycarbonate layer) and a polymer layer (such as polyethylene terephthalate) formed on the substrate.

Abstract: Disclosed herein is an electronic component-embedded printed circuit board, including: a metal substrate including an anodic oxide film formed over the entire surface thereof; two electronic components disposed in a cavity formed in the metal substrate in two stages; an insulation layer formed on both sides of the metal substrate to bury the electronic components disposed in the cavity; and circuit layers including vias connected with connecting terminals of the electronic components and formed on the exposed surfaces of the insulation layer. The electronic component-embedded printed circuit board is advantageous in that its radiation performance of radiating the heat generated from an electronic component can be improved, and its production cost can be reduced, because a metal substrate is used instead of a conventional insulating material.

Abstract: A method for forming a multi-layered structure using a droplet-discharging device; the method comprises: (A) forming a first insulating-material layer covering the material-body surface by discharging a droplet of a first insulating material including a first photosensitive resin to a material-body surface; (B) obtaining a first insulating layer by curing in the first insulating-material layer; (C) forming a pattern of an electric conductive material layer on the first insulating layer by discharging a droplet of an electric conductive material to the first insulating layer; and (D) forming a wiring pattern on the first insulating layer by activating the pattern of the electric conductive material layer.

Abstract: Disclosed herein is a carrier for manufacturing a substrate, including: an insulation layer including a first metal layer formed on one side or both sides thereof; a second metal layer formed on one side of the first metal layer; and a third metal layer formed on one side of the second metal layer, wherein the second metal layer has a lower melting point than the first metal layer or the third metal layer. The carrier is advantageous in that a build up layer can be separated from a carrier by heating, so that a routing process is not required, with the result that the size of a substrate does not change when the build up layer is separated from the carrier, thereby reusing the carrier and maintaining the compatibility between the substrate and manufacturing facilities.

Abstract: A method produces of a ceramic circuit board that has a ceramic substrate on a top side of the circuit board, solderable contact pads for components, and solderable contacts on an underside of the circuit board. The metallization for the solderable contact pads is produced by depositing a metal from a solution directly onto the ceramic substrate.

Abstract: An optical wiring board and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the method includes providing a base substrate having an optical waveguide layer with a mirror groove formed on one surface thereof and a first insulation layer stacked on one surface of the optical waveguide layer and having a through-hole connected with the mirror groove formed thereon, forming a metal mirror layer connected from the mirror groove to an inner wall of the through-hole and forming an electrode pad on a side of the other surface of the optical waveguide layer, in which the electrode pad is disposed in accordance with the position of the metal mirror layer.

Abstract: In one embodiment, a read sensor for a recording head for a magnetic media storage system, has first and second shields, and a magneto-resistive sensor disposed between and shielded by the first and second shields in which the sensing axis of the sensor is tilted with respect to the recording surface of the head. In one embodiment, the sensing axis is oriented at an angle between 10 and 60 degrees with respect to the normal of the recording surface. Other embodiments are described and claimed.

Abstract: An electrical structure and method of forming. The electrical structure includes a first substrate, a first dielectric layer, an underfill layer, a first solder structure, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The first solder structure is formed within the first opening and over a portion of the top surface of said first dielectric layer. The second substrate is formed over and in contact with the underfill layer.

Abstract: A patternable adhesive film is formed in a double-layered structure of an adhesive layer having patternability and an adhesive layer having both adhesion and developability. Thus, the double-layered patternable adhesive film can effectively have both patternability and adhesion.

Abstract: Disclosed herein is a metal wiring structure, including: an electroless nickel plating layer formed on an insulation layer; and a surface treatment layer formed on the electroless nickel plating layer, and a method of fabricating the same. The metal wiring structure has excellent adhesivity without regard to the kind of substrate and can be easily fabricated.

Abstract: A method of integrating a fluorine-based dielectric with a metallization scheme is described. The method includes forming a fluorine-based dielectric layer on a substrate, forming a metal-containing layer on the substrate, and adding a buffer layer or modifying a composition of the fluorine-based dielectric layer proximate an interface between the fluorine-based dielectric layer and the metal-containing layer.

Abstract: A method of integrating a fluorine-based dielectric with a metallization scheme is described. The method includes forming a fluorine-based dielectric layer on a substrate, forming a metal-containing layer on the substrate, and adding a buffer layer or modifying a composition of the fluorine-based dielectric layer proximate an interface between the fluorine-based dielectric layer and the metal-containing layer.

Abstract: A planarization composition is disclosed herein that comprises: a) a structural constituent; and b) a solvent system, wherein the solvent system is compatible with the structural constituent and lowers the lowers at least one of the intermolecular forces or surface forces components of the planarization composition. A film that includes this planarization composition is also disclosed. In addition, another planarization composition is disclosed herein that comprises: a) a cresol-based polymer compound; and b) a solvent system comprising at least one alcohol and at least one ether acetate-based solvent. A film that includes this planarization composition is also disclosed. A layered component is also disclosed herein that comprises: a) a substrate having a surface topography; and b) a planarization composition or a film such as those described herein, wherein the composition is coupled to the substrate.

Abstract: In the present invention, an insulating material is applied onto a substrate in a coating treatment unit to form a coating insulating film. The substrate is heated in the heating processing unit, whereby the coating insulating film is hardened partway. A brush is then pressed against the front surface of the coating insulating film in a planarization unit and moved along the front surface of the coating insulating film, thereby planarizing the coating insulating film. The substrate is then heated to completely harden the coating insulating film. According to the present invention, the coating film can be planarized without using the CMP technology.

Abstract: A method of making a circuitized substrate in which conductors are formed in such a manner that selected ones of the conductors include solder while others do not and are thus adapted for receiving a different form of connection (e.g., wire-bond) than the solder covered conductors. In one embodiment, the solder may be applied in molten form by immersing the substrate within a bath of the solder while in another the solder may be deposited using a screening procedure.

Abstract: Electroless plating is performed to deposit conductive materials on work pieces such as partially fabricated integrated circuits. Components of an electroless plating bath are separately applied to a work piece by spin coating to produce a very thin conductive layer (in the range of a few hundred angstroms). The components are typically a reducing agent and a metal source.

Abstract: The invention provides an electronic component and a manufacturing method thereof that: can allow electronic components to be mounted on an external substrate at a higher density than before; can adjust the height (level) of a terminal electrode as required and desired, thereby solving problems that would occur in the inspection of the conventional electronic components; and can also improve the yield in the mounting of electronic components, thereby achieving increased productivity.

Abstract: The present invention provides a ceramic substrate including: a ceramic stacked layer structure in which multiple ceramic layers are stacked to be interconnected through a via provided within each of the ceramic layers, the ceramic stacked layer structure having a hole provided therein to expose a top portion of the via provided within a ceramic layer of being a surface layer; a conductive material filled within the hole; and an external electrode formed on the surface of the ceramic stacked layer structure so that the external electrode is electrically connected to the conductive material, and a manufacturing method thereof.

Abstract: Multilayer printed wiring boards superior in formation of an ultrafine wiring, which can form a conductive layer superior in peel strength on a flat insulating layer surface, can be prepared by a method including the following steps (A)-(E): (A) a step of laminating a film with a metal film, wherein a metal film layer is formed on a support layer, on an internal-layer circuit substrate via a curable resin composition layer, or laminating an adhesive film with a metal film, wherein a curable resin composition layer is formed on a metal film layer of the film with a metal film, on an internal-layer circuit substrate; (B) a step of curing a curable resin composition layer to form an insulating layer; (C) a step of removing a support layer; (D) a step of removing a metal film layer; and (E) a step of forming a metal film layer on an insulating layer surface by electroless plating.

Abstract: A method is provided which includes forming a metal layer and converting at least a portion of the metal layer to a hydrated metal oxide layer. Another method is provided which includes selectively depositing a dielectric layer upon another dielectric layer and selectively depositing a metal layer adjacent to the dielectric layer. Consequently, a microelectronic topography is formed which includes a metal feature and an adjacent dielectric portion comprising lower and upper layers of hydrophilic and hydrophobic material, respectively. A topography including a metal feature having a single layer with at least four elements lining a lower surface and sidewalls of the metal feature is also provided herein. The fluid/s used to form such a single layer may be analyzed by test equipment configured to measure the concentration of all four elements. In some cases, the composition of the fluid/s may be adjusted based upon the analysis.

Abstract: A process for making a multi-layered circuit board having electrical current traces includes providing a substrate having a 1st layer of conductive material to form a ground plane, plurality of metallic 1st traces on a 2nd side of the substrate having widths of approximately 25 microns or less, developing 1st ribs of photoresist forming 1st walls rising above upper surface of an adjacent seed layer trace, depositing 1st conductive signal traces having a thickness exceeding 25 microns into channels and over seed layer traces and stripping the ribs to leave 1st conductive traces having a height-to-transverse ratio exceeding 1.

Abstract: An electronic component module includes a circuit substrate including surface mount components mounted thereon, a resin layer embedding the surface mount components, and a conductor layer provided on a surface of the resin layer, wherein a conductive post is provided on the surface mount component, and an external electrode having a ground potential provided on the surface mount component is conductively connected to the conductor layer through the conductive post, whereby the conductor layer defines a shielding layer.

Abstract: A touch panel and a fabricating method thereof are provided. The touch panel includes: a substrate; a first conductive layer configured on the substrate and having a first and a second portions; an insulating layer covering the first portion; and a second conductive layer having a third portion configured on the second portion, and a fourth portion configured on the insulating layer and being separate from the third portion. The fabricating method includes the steps of: providing a first conductive layer; forming an insulating layer partially covering the first conductive layer; and forming a second conductive layer having a first pattern coupled to the first conductive layer and a second pattern insulated from the first pattern on the insulating layer.

Abstract: A method and structure for good adhesion of Intermetallic Compounds (IMC) on Cu pillar bumps are provided. The method includes depositing Cu to form a Cu pillar layer, depositing a diffusion barrier layer on top of the Cu pillar layer, and depositing a Cu cap layer on top of the diffusion barrier layer, where an intermetallic compound (IMC) is formed among the diffusion barrier layer, the Cu cap layer, and a solder layer placed on top of the Cu cap layer. The IMC has good adhesion on the Cu pillar structure, the thickness of the IMC is controllable by the thickness of the Cu cap layer, and the diffusion barrier layer limits diffusion of Cu from the Cu pillar layer to the solder layer. The method can further include depositing a thin layer for wettability on top of the diffusion barrier layer prior to depositing the Cu cap layer.

Abstract: The present invention provides an inventive biosensor that includes multiple regions in which the electrical pattern is formed from different electrically conductive materials. The present invention also provides an inventive method for mass producing biosensors as just described. In one embodiment of this method, first and second different electrically conductive materials are deposited side by side on a portion of an electrically insulating base material, and a plurality of electrical patterns is formed on the portion of the base material. Each electrical pattern includes a first region formed from the first electrically conductive material electrically connected to a second region formed from the second electrically conductive material.

Abstract: A method for making printed circuits and printed circuit boards which includes coating a non-metallized substrate and plating an image of a desired circuit design directly onto the coated substrate without the need to image the circuit design on an intermediate silver halide polyester film or diazo and utilizing existing imaging, developing and etching subtractive techniques in conventional printed circuit board processing. One exemplary embodiment of the method for making printed circuit boards includes coating a non-metallized substrate with a palladium based material including a ferric based solution combined with palladium.

Abstract: A method of fabricating an interconnect structure is described. A substrate is provided. A patterned interfacial metallic layer is formed on the substrate. An amorphous carbon insulating layer or a carbon-based insulating layer is formed covering the substrate and the interfacial metallic layer. A conductive carbon line or plug is formed in the amorphous carbon or carbon-based insulating layer electrically connected with the interfacial metallic layer. An interconnect structure is also described, including a substrate, a patterned interfacial metallic layer on the substrate, an amorphous carbon insulating layer or a carbon-based insulating layer on the substrate, and a conductive carbon line or plug disposed in the amorphous carbon or carbon-based insulating layer and electrically connected with the interfacial metallic layer.

Abstract: A method of creating a stack having multiple layers of deposited film onto a substrate is discussed. The method includes depositing a first layer of a first material onto the substrate and depositing a second layer onto the first layer. Depositing the second layer includes depositing a first amount of the second material onto the first layer at a first deposition temperature selected to set the normalized diffusion activation energy of the second material.

Abstract: A via hole is formed in a first cladding layer laminated on a wiring board. A conductive material is filled in the via hole so as to form a first conductor portion (a portion of a conductive via) having a mushroom-like shape projecting from a surface of the first cladding layer. Then, a second cladding layer is formed to cover the first conductor portion, the first cladding layer and a core layer, and a via hole is formed in the second cladding layer. A conductive material is filled in the via hole so as to form a second conductor portion (a remaining portion of the conductive via) connected to the first conductor portion.

Abstract: A wiring board is formed with a substrate designating either the upper surface or the lower surface as a first surface and the other as a second surface; an electronic component arranged inside the substrate; and a first conductive layer formed on the first-surface side of the substrate by means of a first insulation layer made up of a first lower insulation layer and a first upper insulation layer. In such a wiring board, the first lower insulation layer and the first upper insulation layer are made of different materials from each other. Moreover, the first lower insulation layer is positioned on the first surface of the substrate and the electronic component, and the material that forms the first lower insulation layer fills a clearance between the substrate and the electronic component.

Abstract: Disclosed herein is a heat dissipating substrate having a structure in which two two-layered core substrates, each including a metal core functioning to radiate heat, are laminated and connected in parallel to each other, thus accomplishing more improved radiation performance, and a method of manufacturing the same.

Abstract: A method of forming an organosilicon oxide film by plasma CVD includes: (i) adjusting a temperature of a susceptor on which a substrate is placed to lower than 300° C.; (ii) introducing at least tetraethylorthosilicate (TEOS) and oxygen into a reactor in which the susceptor is disposed; (iii) applying high-frequency RF power and low-frequency RF power; and (iv) thereby depositing an organosilicon oxide film on the substrate.

Abstract: Embodiments described herein provide a method for forming two titanium nitride materials by different PVD processes, such that a metallic titanium nitride layer is initially formed by a PVD process in a metallic mode and a titanium nitride retarding layer is formed over a portion of the metallic titanium nitride layer by a PVD process in a poison mode. Subsequently, a first aluminum layer, such as an aluminum seed layer, may be selectively deposited on exposed portions of the metallic titanium nitride layer by a CVD process. Thereafter, a second aluminum layer, such as an aluminum bulk layer, may be deposited on exposed portions of the first aluminum layer and the titanium nitride retarding layer during an aluminum PVD process.

Abstract: The present invention relates to a method to fabricate a flip chip substrate structure, which comprises: providing a carrier; forming a patterned resist layer on the surface of the carrier; forming sequentially a first metal layer, an etching-stop layer, and a second metal layer; removing the resist layer, forming a patterned first solder mask, and then forming at least one first circuit build up structure thereon; forming additionally a patterned second solder mask on the circuit build up structure; respectively removing the carrier, the first metal layer, and the etching-stop layer; and forming solder bumps on both sides of the circuit build up structure. The method increases integration and achieves the purpose of miniaturization. The method solves the problem of circuit layer multiplicity and process complexity.

Abstract: There is a highly reliable semiconductor module having a satisfactory bonding strength in the electrical bonded portion. In the semiconductor module 10, a semiconductor chip 11 is mounted on a circuit board 20. In the circuit board 20, on an insulating ceramic substrate 21 is formed a metal circuit plate 22 on which the semiconductor chip 11 is implemented. The semiconductor chip 11 and metal circuit plate 22 are connected with each other by an aluminum bonding wire 23. In the connected portion between the metal circuit plate 22 and bonding wire 23, a coating layer 24 for excellent conjunction therebetween is mounted. The coating layer 24, as shown in an enlarged diagram, is made up of a nickel (Ni) layer 241, a P-distributed palladium (Pd) layer 242, and an Au layer 243 in increasing order. To the P-distributed Pd layer 242 is added P (phosphorous) and, the P concentration on the Ni layer 241 is higher than that on the Au layer side 243.

Abstract: A manufacturing method of an electronic board includes: placing an electronic component including conductive parts on a first insulation layer with the conductive parts facing up as well as providing projections having conductivities on the conductive parts; applying an insulation material by means of a droplet discharging method providing a second insulation layer on an upper surface of the electronic component while dodging the projections, the second insulation layer having a height the projections project out from the layer; providing conductive wirings to be connected to the projections on the second layer; and applying the insulation material around the electronic component by means of the droplet discharging method to provide a third insulation layer having a height generally equal to the second insulation layer.

Abstract: The invention comprises methods for filling holes in printed wiring boards and printed wiring boards produced by these methods. The methods involve plating metal conductors inside the holes of the printed wiring boards while protecting the conducting surfaces of the printed wiring boards from being plated using photoresist film. The side surfaces of a printed wiring board are covered with photoresist. The photoresist is exposed to developing light, except the photoresist covering the holes on one side of the board is masked to prevent exposure of the holes to the developing light. The undeveloped photoresist covering the holes is removed. The board is subjected to a plating process, which deposits conductive materials in the holes, but the photoresist on the conducting surfaces of the board prevents conductive materials to be plated on the surfaces of the board.

Abstract: A semiconductor device includes a support body, a first substrate provided on a surface at one side of the support body, a second substrate provided on a surface at the other side of the support body, and a semiconductor chip provided on the first substrate exposed to an opening part piercing the support body and the second substrate. The first substrate includes a first dielectric layer and a wiring layer, a plurality of first electrodes connected to the semiconductor chip which first electrodes are provided on a first surface of the first substrate exposed to an inside of the opening part, and the second substrate includes a second dielectric layer made of a material substantially the same as the first dielectric layer.