Multilayer Patents (Class 427/97.1)
-
Patent number: 7470380Abstract: A conductive composition consisting essentially of (a) 50-95 wt % finely divided particles of an electrically-conductive material dispersed in (b) a liquid vehicle, for use in the manufacture of an electrically-conductive pattern on a substrate for the use of reducing cross-sectional area and width while retaining conductivity and resistivity.Type: GrantFiled: March 23, 2004Date of Patent: December 30, 2008Assignee: E.I. Du Pont De Nemours and CompanyInventor: Sarah Jane Mears
-
Patent number: 7459325Abstract: Organic surfactants are employed to passivate the surfaces of MEMS devices, such as digital micromirrors. The binding of these surfactants to the surface is improved by first associating with the surface transition metal atoms or ions from Groups IVB, VB, and IVB of the periodic table.Type: GrantFiled: January 5, 2005Date of Patent: December 2, 2008Assignee: Texas Instruments IncorporatedInventors: Simon Joshua Jacobs, Seth Adrian Miller
-
Patent number: 7455816Abstract: The invention relates to a method for coating a support plate for carrying out functional tests on biological cells, to a support plate for carrying out functional tests on biological cells and to the use of corresponding support plates for carrying out functional tests on biological cells.Type: GrantFiled: February 9, 2007Date of Patent: November 25, 2008Assignee: NMI Naturwissenschaftliches und Medizinisches Institut an der Universitaet TuebingenInventors: Heiko Steuer, Markus Templin, Britta Kanzok, Cornelia Kuschel, Brigitte Angres
-
Publication number: 20080283488Abstract: A ceramic substrate (S) has on its top side weldable connection surfaces (LA) and on its underside weldable contacts (LK). In the disclosed substrate (S), the weldable connection surfaces, which were until now produced using printing pastes, is replaced by weld surface contacts precipitated from a solution and directly applied to the ceramic material. These weld contact surfaces are characterised by a more even surface, improved bondability and structurability.Type: ApplicationFiled: June 3, 2005Publication date: November 20, 2008Inventor: Jurgen Brunner
-
Publication number: 20080283830Abstract: Methods of forming transparent zinc-tin oxide structures are described. Devices that include transparent zinc-tin oxide structures as at least one of a channel layer in a transistor or a transparent film disposed over an electrical device that is at a substrate.Type: ApplicationFiled: May 14, 2007Publication date: November 20, 2008Inventors: Kie Y. Ahn, Leonard Forbes
-
Patent number: 7445952Abstract: A method of forming a laminate and a method of manufacturing a photovoltaic device using the laminate are provided. The laminate forming method includes a first step of forming an intermediate layer on a base member, and a second step of forming a metal layer on the intermediate layer, the adhesion of the metal layer to the base member being lower than that of the intermediate layer, the reflectance of the metal layer being higher than that of the intermediate layer. The rate of formation of the metal layer is increased at an intermediate stage in the second step. The laminate thereby formed has improved characteristics and is capable of maintaining improved reflection characteristics and adhesion even under high-temperature and high-humidity conditions or during long-term use.Type: GrantFiled: August 5, 2005Date of Patent: November 4, 2008Assignee: Canon Kabushiki KaishaInventors: Takaharu Kondo, Hideo Tamura, Atsushi Yasuno, Noboru Toyama, Yuichi Sonoda, Masumitsu Iwata, Akiya Nakayama, Yusuke Miyamoto
-
Patent number: 7438945Abstract: A method of producing a multilayer interconnection board is disclosed that includes the steps of processing a resin member on an interconnection layer by imprinting press, and removing residue of the resin member at the bottom of a via hole after forming the via hole. In the method of producing a multilayer interconnection board, a thermal setting resin, which has a setting temperature higher than that of the resin member, is applied on a via-connecting portion of the interconnection layer, the resin member is formed on the interconnection layer, an interconnection groove and a via hole are formed by imprinting press on the resin member by using a tool, and an un-cured portion of the high temperature setting resin is dissolved and removed by using a resin solvent. Thereby, residue of the resin member on the thermal setting resin is removed.Type: GrantFiled: January 11, 2005Date of Patent: October 21, 2008Assignee: Shinko Electric Industries Co., Ltd.Inventors: Shigetsugu Muramatsu, Katsumi Yamazaki
-
Patent number: 7425346Abstract: A method of forming a hybrid inorganic/organic dielectric layer on a substrate for use in an integrated circuit is provided, wherein the method includes forming a first dielectric layer on the substrate via chemical vapor deposition, and forming a second dielectric layer on the first dielectric layer via chemical vapor deposition, wherein one of the first dielectric layer and the second dielectric layer is formed from an organic dielectric material, and wherein the other of the first dielectric layer and the second dielectric layer is formed from an inorganic dielectric material.Type: GrantFiled: September 7, 2004Date of Patent: September 16, 2008Assignee: Dielectric Systems, Inc.Inventors: Chieh Chen, Atul Kumar, Yuri Pikovsky, Chung J. Lee
-
Patent number: 7418780Abstract: An exemplary method for forming stacked via-holes in a multilayer printed circuit board includes the steps of: providing a base circuit board; attaching a first copper-coated-substrate having a first substrate and a first copper layer thereon and a second copper-coated-substrate having a second substrate and a second copper layer thereon onto the base circuit board in a manner such that; forming at least one first window in the second copper layer, making at least one first hole in the second substrate through the at least one first window, forming at least one second window in the first copper layer through the at least one first hole, and making at least one second hole in the first substrate through the at least one second window, thus forming at least one part-finished stacked via-hole; and plating the at least one part-finished stacked via-hole thereby forming at least one stacked via-hole.Type: GrantFiled: November 16, 2006Date of Patent: September 2, 2008Assignee: Foxconn Advanced Technology Inc.Inventors: Wen-Chin Lee, Cheng-Hsien Lin
-
Patent number: 7416759Abstract: In a method of forming a wiring pattern, a plurality of electrical wirings deposited to be multilayered are conductively connected to one another through a conducting post. The method has forming the electrical wiring by discharging a first droplet including a material for forming the electrical wiring, and forming the conducting post by discharging a second droplet including a material for forming the conducting post, wherein a volume of the second droplet is greater than a volume of the first droplet.Type: GrantFiled: September 13, 2005Date of Patent: August 26, 2008Assignee: Seiko Epson CorporationInventors: Tsuyoshi Shintate, Kazuaki Sakurada, Noboru Uehara
-
Publication number: 20080199597Abstract: The invention relates to a method for producing a three-dimensional circuit having at least two superimposed, flexibly formed substrate layers comprising conductor paths and/or circuit elements composed of electrical functional materials. The method has a combination of the following method steps: a. using a continuous sheet of material for the at least two substrate layers, b. printing the electrical functional materials onto the substrate layers, c. providing at least one folding or bending edge in the sheet of material in order to delimit the at least two substrate layers from each other, the folding operation being carried out inline with the printing operation, d. folding the sheet of material about the folding or bending edge after the conductor paths and/or circuit elements have been printed on, so that the at least two substrate layers are arranged one above the other.Type: ApplicationFiled: July 11, 2006Publication date: August 21, 2008Inventor: Arved Huebler
-
Publication number: 20080171139Abstract: In one embodiment, an inner layer circuit pattern portion and a lead pattern portion are formed, an outer layer base material is prepared, an interlayer adhesive layer to which has been affixed in advance an inner layer separation film is prepared, the interlayer adhesive layer is layered on the outer layer base material, a molded inner layer separation film is formed by molding the inner layer separation film, the molded inner layer separation film is positioned on the lead pattern portion and the outer layer base material is layered on the inner layer base material with interposition of the interlayer adhesive layer, a conductor layer of the outer layer base material is patterned to form an outer layer circuit pattern portion, and the molded inner layer separation film is separated from the inner layer base material to remove the interlayer adhesive layer and the outer layer base material.Type: ApplicationFiled: January 10, 2008Publication date: July 17, 2008Inventors: Yukihiro UENO, Yuhji TAKAMOTO
-
Patent number: 7399399Abstract: A method for manufacturing a semiconductor package is proposed. A circuit board with a circuit layer on at least one surface thereof is provided. The circuit board has at least one free area, and the circuit layer has a plurality of electrically connecting pads distributed on the periphery of the free area. A metal protecting layer is plated on the electrically connecting pads by non-plating line. The free area is removed, to form a cavity penetrating the circuit board. The present invention prevents burrs which may otherwise form on the periphery of a cavity, to increase the yield and throughput.Type: GrantFiled: September 18, 2006Date of Patent: July 15, 2008Assignee: Phoenix Precision Technology CorporationInventors: E-Tung Chou, Che-Wei Hsu, Tzu-Sheng Tseng
-
Publication number: 20080160246Abstract: The invention relates to a circuit board unit and a method for production thereof. The circuit board unit comprises a circuit board topmost laminate with conductive tracks on the upper side for mounting surface-mountable devices. The circuit board topmost laminate features a thickness dimensioned such that the anticipated heat dissipated by the surface-mountable devices is transported from the upper side to the underside of the circuit board laminate to good effect. The circuit board unit further comprises an electrically insulating laminate arranged under the circuit board topmost laminate, inserts made of a material with good heat conductivity and electrical insulation embedded in the electrically insulating laminate at sites below surface-mountable devices with high heat dissipation, and a cooling plate arranged below the electrically insulating laminate and the inserts.Type: ApplicationFiled: October 25, 2007Publication date: July 3, 2008Inventors: Ernst Buhler, Rino D'Amario, Reto Knaak
-
Publication number: 20080160334Abstract: A surface treatment process for a substrate is provided. There are a plurality of first conductive patterns on a top surface of the substrate and a plurality of second conductive patterns on a bottom surface of the substrate and a plurality of inner circuits electrically connected with the first conductive patterns and the second conductive patterns. The process includes the following steps. First, a conductive layer is formed on the second conductive patterns. Next, an insulating layer is formed on the conductive layer. After the insulating layer is formed, an anti-oxidizing layer is electroplated on the first conductive patterns using the conductive layer. Next, the insulating layer and the conductive layer are removed in sequence. The surface treatment process of the present invention has the advantage of low fabrication cost and does not need a plating bar to perform the electroplating process or a photolithographic process.Type: ApplicationFiled: April 11, 2007Publication date: July 3, 2008Applicant: UNIMICRON TECHNOLOGY CORP.Inventor: Chih-Peng Fan
-
Publication number: 20080149375Abstract: A wired circuit board includes a metal supporting board, an insulating base layer formed on the metal supporting board, a conductive pattern formed on the insulating base layer, a first semiconductive layer formed on a surface of the insulating base layer exposed from the conductive pattern, an insulating cover layer formed on the conductive pattern and the first semiconductive layer and a second semiconductive layer formed on a surface of the insulating cover layer. The first semiconductive layer is electrically connected to the conductive pattern and the metal supporting board, and the second semiconductive layer is electrically connected to the metal supporting board.Type: ApplicationFiled: December 20, 2007Publication date: June 26, 2008Applicant: Nitto Denko CorporationInventors: Jun Ishii, Yasunari Ooyabu
-
Single Layer Carbon Nanotube-Based Structures and Methods for Removing Heat from Solid-State Devices
Publication number: 20080131722Abstract: One embodiment includes: a copper substrate; a catalyst on top of a single surface of the copper substrate; and a thermal interface material on top of the single surface of the copper substrate. The thermal interface material comprises: a layer of carbon nanotubes that contacts the catalyst, and a filler material located between the carbon nanotubes. The carbon nanotubes are oriented substantially perpendicular to the single surface of the copper substrate. The thermal interface material has: a bulk thermal resistance, a contact resistance between the thermal interface material and the copper substrate, and a contact resistance between the thermal interface material and a solid-state device. The summation of the bulk thermal resistance, the contact resistance between the thermal interface material and the copper substrate, and the contact resistance between the thermal interface material and the solid-state device has a value of 0.06 cm2K/W or less.Type: ApplicationFiled: May 15, 2007Publication date: June 5, 2008Inventors: Ephraim Suhir, Subrata Dey, Barbara Wacker, Peter Schwartz -
Patent number: 7370412Abstract: An electronic device connecting method according to a first aspect of the present invention includes: mounting an electronic device having at least one electrode portion on a sheet-like porous member having a hole therein so that the electrode portion is close to the porous member; selectively irradiating a predetermined region of the porous member, on which the electronic device is mounted, with energy lines to form a latent image in an irradiated or non-irradiated portion of the porous member, the predetermined region including a portion close to the electrode portion; after irradiating with the energy lines, filling a conductive material in a hole of the latent image of the porous member to form a conductive portion; and bonding and integrating the porous member, in which the conductive portion is formed, to and with the electronic device.Type: GrantFiled: July 3, 2003Date of Patent: May 13, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Toshiro Hiraoka, Mitsuyoshi Endo, Naoko Yamaguchi, Yasuyuki Hotta, Shigeru Matake, Hideo Aoki, Misa Sawanobori
-
Publication number: 20080062688Abstract: The present disclosure is generally directed to illumination devices, and methods for making the same. The device, in particular, includes a first conductor layer, a first insulator layer disposed on the first conductor layer and having at least one first aperture defined therein through the first insulator layer, a second conductor layer disposed on the first insulator layer and having at least one second aperture defined therein through the second conductor layer and positioned to align with the at least one first aperture, and a light manipulation layer disposed on the second conductor layer and having at least one pair of apertures defined therein through the light manipulation layer including a third aperture and a fourth aperture, where the third aperture is positioned to align with the at least one second and first apertures.Type: ApplicationFiled: June 1, 2007Publication date: March 13, 2008Inventors: Ellen O. Aeling, John R. David, Michael A. Meis, Ronald S. Steelman
-
Patent number: 7337537Abstract: A method for forming a back-drilled plated through hole in a printed circuit board and the resulting printed circuit board are described herein. In the preferred embodiment, the printed circuit board includes a via extending through a plurality of stacked layers. The via includes a plated through hole and a back-drilled hole. The plated through hole is located within a predetermined number of the stacked layers and the back-drilled hole is located within the remaining stacked layer(s). The plated through hole without an electrically conductive material located on walls therein has a diameter that is substantially the same size or smaller than the diameter of the back-drilled hole.Type: GrantFiled: February 15, 2006Date of Patent: March 4, 2008Assignee: Alcatel LucentInventor: Joseph Smetana, Jr.
-
Patent number: 7325304Abstract: There is provided a method of manufacturing a probe card that electrically connects a testing device and a device under test to transmit a signal between the testing device and the device under test. The method includes the steps of forming a probe pin on a probe pin substrate, joining the probe pin held on the probe pin substrate to a circuit board, and cutting the probe pin to separate the probe pin substrate from the probe pin.Type: GrantFiled: June 1, 2005Date of Patent: February 5, 2008Assignee: Advantest CorporationInventors: Wataru Narazaki, Tadao Saito
-
Publication number: 20080026593Abstract: A method of manufacturing a patterned electric circuit. The method comprises the steps of providing a cold gas-dynamic spraying (CGDS) device, providing a substrate, and depositing a pattern of electrically conductive material with the CGDS device on the substrate by relative movement between the CGDS device to the substrate.Type: ApplicationFiled: October 1, 2004Publication date: January 31, 2008Inventor: William Ogilvie
-
Patent number: 7320173Abstract: A method for fabricating a multi-layer printed circuit board can include forming an etching resist layer on a first metal layer having plating grooves that selectively expose the first metal layer, forming a plated layer at the surface of the first metal layer exposed by the plating groove through a plating process to form connection protrusion, removing the etching resist layer, forming an insulation layer at the first metal layer and positioning a second metal layer at the surface of the insulation layer coupled to an end portion of the connection protrusion. By forming the connection protrusion through the plating process, a loss of material can be reduced and a strength of the connection protrusion can be increased. Further, a complexity of the fabrication process is reduced to reduce costs and increase productivity.Type: GrantFiled: February 3, 2004Date of Patent: January 22, 2008Assignee: LG Electronics Inc.Inventors: Sung-Gue Lee, Jung-Ho Hwang, Joon-Wook Han, Sang-Min Lee, Tae-Sik Eo, Yu-Seock Yang
-
Patent number: 7290332Abstract: According to one aspect of the present invention, a method of constructing an interposer is provided. A conductive layer is formed on a nonconductive layer. The conductive layer has via portions, non-via portions, and first and second opposing surfaces. The first surface of the conductive layer is adjacent to the nonconductive layer. Portions of the nonconductive layer are removed to expose portions of the first surface of the conductive layer. Conductive pads are formed on the exposed portions of the first surface and the second surface of the conductive layer. The non-via portions of the conductive layer are removed to form a plurality of electrically separated conductors. Each conductor includes at least two conductive pads and a via portion of the conductive layer.Type: GrantFiled: August 31, 2004Date of Patent: November 6, 2007Assignee: Exatron, Inc.Inventor: Robert P. Howell
-
Patent number: 7285305Abstract: A method of producing a multilayered wiring board having at least two wiring layers (wiring patterns 17, 31), polyamide 22 (an interlayer insulation film) between the wiring layers, and an interlayer conducting post (a conductor post) 18 for conducting between the wiring pattern 17 and the wiring pattern 31, wherein the polyimide 22 is disposed around the interlayer conducting post 18 using a liquid drop discharge system.Type: GrantFiled: April 16, 2003Date of Patent: October 23, 2007Assignee: Seiko Epson CorporationInventors: Masahiro Furusawa, Hirofumi Kurosawa, Takashi Hashimoto, Masaya Ishida
-
Patent number: 7281328Abstract: The present invention is related to a method of fabricating a rigid-flexible printed circuit board. Specifically, this invention relates to a method of fabricating a rigid-flexible printed circuit board, in which an internal circuit pattern exposed for use in an external pad and a mounting pad is protected from external environments using a resist cover by window etching the base copper foil of a flexible region upon formation of an external circuit pattern as opposed to using a resist cover. Thus the number of fabrication processes and the fabrication costs are decreased and the increase in defect rates due to contamination is prevented, resulting in maximized reliability.Type: GrantFiled: October 18, 2005Date of Patent: October 16, 2007Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Yang Je Lee, Dek Gin Yang, Jung Wook Hwang, Kyu Hyok Yim, Jung Hun Chai, Young Ho Lee, Kwang Yune Kim, Dong Gi An
-
Publication number: 20070201214Abstract: The present invention provides a core board and a manufacturing method thereof, in which the core board includes a nickel layer as a seed layer to improve the binding strength between an insulation layer and a conductive layer, so that it allows forming fine inner circuits by the semi-additive method.Type: ApplicationFiled: February 21, 2007Publication date: August 30, 2007Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Soon-Oh Jung, Cheol-Ho Choi, Chang-Hyun Nam, Hong-Won Kim, Seung-Chul Kim
-
Patent number: 7240431Abstract: A plating resist film 2 is formed on a wiring board substrate 1 as a core material of a multilayer printed wiring board, then a through-hole 3 is formed, and through-hole conductor 4 is formed along the wall surface of the through-hole 3 and the through-hole surface of the plating resist film 2, so that protrusion portion 4a is formed in the through-hole conductor 4. The plating resist film 2 is then stripped off and a panel plating layer 5 is formed on the surface of the wiring board substrate 1 and the through-hole conductor 4 so that the through-hole 4 and the panel plating layer 5 are connected with the protrusion 4a coated, and thus the connection area can be increased.Type: GrantFiled: October 26, 2005Date of Patent: July 10, 2007Assignee: Sharp Kabushiki KaishaInventor: Yukihiro Ueno
-
Patent number: 7229669Abstract: Described are structures useful in microelectronic or MEMS devices such as atomic clocks, sensors, and RF switches, wherein a first material is deposited onto a substrate to define a first material area of coverage and a second material is deposited over the first material area of coverage to define a second material area of coverage that includes the first material area of coverage and that additionally includes area that surrounds the first material area of coverage, such that the first material is enclosed by the second material over the entire area and past the edges of the first material.Type: GrantFiled: November 13, 2003Date of Patent: June 12, 2007Assignee: Honeywell International Inc.Inventors: Dan W. Youngner, Leonard A. Hilton
-
Patent number: 7225536Abstract: A pre-casting multi-layer PCB process has steel plate mold engraved with circuitry and the epoxy coated on the mold for the epoxy to cover up a fiber glass substrate; conductive material coated on the epoxy to insert molding the former into the latter to form recessed circuitry; then baked and solidified, sandblasted to remove film for the conductive material to become conducted circuitry; the lamination made by layer for achieving even thinner PBC circuitry while maintaining sufficient structural strength.Type: GrantFiled: April 7, 2005Date of Patent: June 5, 2007Inventor: Ho-Ching Yang
-
Patent number: 7223349Abstract: A printed wiring board having a conductor pattern on which a pre-flux film of a stabilized quality is to be formed using a water-soluble pre-flux liquid. To this end, such an apparatus is used which includes an etching unit 12 for etching lands 5b, 6b formed on the printed wiring board 1, a rinsing unit 13 for rinsing the printed wiring board 1, a bubble removing 14 for removing air bubbles 58 attached to the printed wiring board 1 on immersing the printed wiring board 1 in a water-soluble pre-flux liquid 9a in a processing vessel 56, a pre-flux forming unit 15 for forming a pre-flux film 9 on the lands 5b, 6b of the printed wiring board 1 in the pre-flux liquid 9a using an in-liquid spraying unit 61, a liquid removing unit 16 for removing the pre-flux liquid 9a from the printed wiring board 1 transported from the processing vessel 56 and a rinsing unit 17 for rinsing the printed wiring board 1.Type: GrantFiled: March 14, 2005Date of Patent: May 29, 2007Assignee: Sony CorporationInventors: Atsuhiro Uratsuji, Tatsutoshi Narita, Masanobu Yagi, Yoshiyuki Ukeda
-
Patent number: 7213334Abstract: A double-sided flexible printed board is manufactured by: (a) forming a polyimide precursor layer on a metal layer; (b) forming an upper circuit layer on the polyimide precursor layer by a semi-additive technique; and (c) imidating the polyimide precursor layer to form a polyimide insulating layer.Type: GrantFiled: December 16, 2003Date of Patent: May 8, 2007Assignees: Sony Corporation, Sony Chemical & Information Device CorporationInventors: Hideyuki Kurita, Masanao Watanabe
-
Patent number: 7175876Abstract: Patterned articles can be prepared by applying a release polymer to a substrate in a desired pattern, applying a substrate-adherent polymer over the pattern and substrate, and mechanically removing the substrate-adherent polymer from the pattern without requiring solvent. Suitable mechanical removal methods include applying adhesive tape to the substrate-adherent polymer and peeling the tape and substrate-adherent polymer away from the pattern, and abrading the substrate-adherent polymer from the pattern using impact media.Type: GrantFiled: June 27, 2003Date of Patent: February 13, 2007Assignee: 3M Innovative Properties CompanyInventors: M. Benton Free, Mikhail L. Pekurovsky
-
Patent number: 7045198Abstract: The present invention provides a prepreg and a circuit board that can achieve, e.g., low interstitial via connection resistance, excellent connection stability, and high durability, regardless of materials, physical properties, and a combination of the materials of an insulating layer. The present invention also provides a method for manufacturing the prepreg and the circuit board. The prepreg of the present invention includes a laminate including at least one first layer and at least one second layer. The first layer is an insulating layer that includes a resin. The second layer has pores that connect an upper and a lower surface of the second layer, and the upper and the lower surface of the second layer differ from each other in at least one selected from open are ratio and average pore diameter. Using this prepreg makes it possible to provide a circuit board that is characterized, e.g., by low interstitial via connection resistance, excellent connection stability, and high durability.Type: GrantFiled: October 24, 2002Date of Patent: May 16, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasushi Nakagiri, Takeshi Suzuki, Fumio Echigo
-
Patent number: 7036222Abstract: A method of making a multi-layer circuit assembly includes providing a core structure including an inner dielectric element having first and second metal layers on opposite surfaces thereof, forming one or more through vias extending through the metal layers and the inner dielectric element and coating the metal layers and the through vias with a dielectric material to form a coated structure having first and second outer dielectric layers overlying the first and second metal layers respectively and dielectric material lining the through vias. An outer metal layer is then provided over the first and second outer dielectric layers. The coated through vias are then metallized to form metallic via lines which connect the outer metal layers and which are insulated from the first and second metal layers. The outer metal layers are then selectively patterned to form first signal lines overlying the first metal layer and second signal lines overlying the second metal layer.Type: GrantFiled: May 11, 2004Date of Patent: May 2, 2006Assignee: Tessera, Inc.Inventor: Belgacem Haba
-
Patent number: 7028400Abstract: An integrated circuit substrate having laser-exposed terminals provides a high-density and low cost mounting and interconnect structure for integrated circuits. The laser-exposed terminals can further provide a selective plating feature by using a dielectric layer of the substrate to prevent plating terminal conductors and subsequently exposing the terminals via laser ablation. A metal layer may be coated on one or both sides with a dielectric material, conductive material embedded within the dielectric to form conductive interconnects and then coating over the conductive material with a conformal protective coating. The protectant is then laser-ablated to expose the terminals. A dielectric film having a metal layer laminated on one side may be etched and plated. Terminals are then laser-exposed from the back side of the metal layer exposing unplated terminals.Type: GrantFiled: June 24, 2003Date of Patent: April 18, 2006Assignee: Amkor Technology, Inc.Inventors: David Jon Hiner, Ronald Patrick Huemoeller, Sukianto Rusli
-
Patent number: 7011862Abstract: An object of the invention is to prevent the color on a surface of a plated metal layer from changing. The invention is a wiring substrate obtained by forming a wiring conductor made of a metal having a high melting point on an insulator, and coating a surface of the wiring conductor with an electroless plated metal layer, wherein the electroless plated metal layer contains an element of Group 1B and is free from lead.Type: GrantFiled: November 9, 2004Date of Patent: March 14, 2006Assignee: Kyocera CorporationInventors: Yoshihiro Hosoi, Yasuo Fukuda
-
Patent number: 6975453Abstract: The present invention comprises a multilayer inorganic anti-reflective coating with predetermined optical properties, for application on a flexible substrate. The coating comprises a stack consisting of five material layers, whereby the third layer is a dummy layer consisting of an electrically conductive material, preferably indium-tinoxyde, which provides the coating with an adjustable electrical sheet resistance of between 25 and 2000 ?/sq without thereby influencing its optical properties. The anti-reflective coating can be applied onto a flexible substrate (e.g. a polymer film) by means of a single 12 or double pass vacuum magnetron sputtering operation.Type: GrantFiled: October 27, 1998Date of Patent: December 13, 2005Assignee: Innovative Sputtering TechnologyInventors: Paul Lippens, Peter Persoone
-
Patent number: 6966110Abstract: A method of fabricating a liquid emission device includes a chamber having a nozzle orifice. Separately addressable dual electrodes are positioned on opposite sides of a central electrode. The three electrodes are aligned with the nozzle orifice. A rigid electrically insulating coupler connects the two addressable electrodes. To eject a drop, an electrostatic charge is applied to the addressable electrode nearest to the nozzle orifice, which pulls that electrode away from the orifice, drawing liquid into the expanding chamber. The other addressable electrode moves in conjunction, storing potential energy in the system. Subsequently the addressable electrode nearest to the nozzle is de-energized and the other addressable electrode is energized, causing the other electrode to be pulled toward the central electrode in conjunction with the release of the stored elastic potential energy.Type: GrantFiled: September 25, 2002Date of Patent: November 22, 2005Assignee: Eastman Kodak CompanyInventors: Michael J. DeBar, Gilbert A. Hawkins, James M. Chwalek
-
Patent number: 6953600Abstract: There are provided a conductive film forming composition capable of forming wiring or an electrode which can be suitably used in a variety of electronic devices, easily and inexpensively, a method for forming a film using the composition, a conductive film formed by the method, and wiring or an electrode which comprises the film. A conductive film forming composition comprising a complex of an amine compound and aluminum hydride and an organic solvent is applied on a substrate and then subjected to a heat treatment and/or irradiation with light, whereby a conductive film such as an electrode or wiring is produced.Type: GrantFiled: April 10, 2003Date of Patent: October 11, 2005Assignees: JSR Corporation, Sharp Corporation, International Center for Materials ResearchInventors: Yasuaki Yokoyama, Yasuo Matsuki, Ikuo Sakono, Kazuki Kobayashi, Yasumasa Takeuchi
-
Patent number: 6952871Abstract: It consists of making a first engraving over a first face of a panel of electro-conducting material to form some reliefs and depressions corresponding to future tracks and intermediate tracks; subjecting said first face to a black oxide treatment (40); applying a layer of an adhesive material over said first face previously engraved and treated with black oxide; applying by injection moulding a dielectric material (20) over said previously engraved first face, treated and with the adhesive applied, covering said reliefs and filling said depressions; and carrying out a second selective engraving over a second face, opposite to the first one, of the mentioned panel to eliminate the material thereof corresponding to said future intermediate tracks, so that some finished tracks (16) remain insulated from each other, partially embedded on a face of said dielectric material (20) and separated by intermediate tracks (18).Type: GrantFiled: December 31, 1999Date of Patent: October 11, 2005Assignee: Lear Automotive (EEDS) Spain, S.L.Inventors: José Antonio Cubero Pitel, Luis Ara Alonso
-
Patent number: 6889432Abstract: A method for manufacturing a double-sided circuit board from a board material having a first electric conductor layer and a first electrically insulating layer, including the steps of: making conduction holes in the board material so as to penetrate only the first electrically insulating layer or both the first electrically insulating layer and the first electric conductor layer; forming an electrically conductive thin-film layer on a surface of the first electrically insulating layer and wall surfaces of the conduction holes; forming a second electrically insulating layer on the electrically conductive thin-film layer; forming a first electric conductor wiring by electroplating on predetermined portions of the electrically conductive thin-film layer; covering the first electric conductor wiring with a chemical-resistant film; forming a second electric conductor wiring by chemically dissolving a predetermined portion of another surface of the first electric conductor layer; and removing the second electricallType: GrantFiled: February 5, 2003Date of Patent: May 10, 2005Assignee: Nitto Denko CorporationInventors: Toshiki Naito, Yoshifumi Shinogi, Daisuke Uenda
-
Patent number: 6878296Abstract: A printed wiring board having a conductor pattern on which a pre-flux film of a stabilized quality is to be formed using a water-soluble pre-flux liquid. To this end, such an apparatus is used which includes an etching unit 12 for etching lands 5b, 6b formed on the printed wiring board 1, a rinsing unit 13 for rinsing the printed wiring board 1, a bubble removing unit 14 for removing air bubbles 58 attached to the printed wiring board 1 on immersing the printed wiring board 1 in a water-soluble pre-flux liquid 9a in a processing vessel 56, a pre-flux forming unit 15 for forming a pre-flux film 9 on the lands 5b, 6b of the printed wiring board 1 in the pre-flux liquid 9a using an in-liquid spraying unit 61, a liquid removing unit 16 for removing the pre-flux liquid 9a from the printed wiring board 1 transported from the processing vessel 56 and a rinsing unit 17 for rinsing the printed wiring board 1.Type: GrantFiled: October 6, 2003Date of Patent: April 12, 2005Assignee: Sony CorporationInventors: Atsuhiro Uratsuji, Tatsutoshi Narita, Masanobu Yagi, Yoshiyuki Ukeda