Multilayer Patents (Class 427/97.1)
  • Publication number: 20100230148
    Abstract: To provide a substrate for mounting a semiconductor element, in which fine-pitch wiring layers are formed to allow a semiconductor element to be mounted, while heat generated in the semiconductor element will not result in a decrease in reliability. Semiconductor-element mounting substrate sandwiches low-thermal-expansion substrate with upper interlayer resin layer and lower interlayer resin layer, and conductive circuit of organic substrate and first conductive circuit of low-thermal-expansion substrate are connected by via conductor formed in interlayer resin layer. Therefore, low-thermal-expansion substrate for mounting semiconductor element may be connected to organic substrate that is connected to outside substrates, without arranging an organic substrate and resin layers on the lower surface of low-thermal-expansion substrate, where impact from the thermal history of semiconductor element is notable.
    Type: Application
    Filed: November 12, 2009
    Publication date: September 16, 2010
    Applicant: IBIDEN, CO., LTD.
    Inventors: Takashi Kariya, Daiki Komatsu
  • Publication number: 20100218985
    Abstract: An integrated circuit mounted board includes a printed wiring board and an integrated circuit bare chip mounted on the printed wiring board. The printed wiring board includes a metal base, an insulating member made of an insulating material and disposed on the metal base, and a wiring pattern disposed on the insulating member. The wiring pattern includes an electrode part to which the integrated circuit bare chip is electrically coupled. The insulating member includes an under region being opposite to the electrode part. The metal base includes a metal substrate and a metal portion protruding from the metal substrate. The metal portion is buried in the under region of the insulating member.
    Type: Application
    Filed: February 9, 2010
    Publication date: September 2, 2010
    Applicant: DENSO CORPORATION
    Inventor: Takuya KOUYA
  • Patent number: 7776383
    Abstract: Methods for discover of ceramic nanomaterial suitable for an application by preparing an array of first layer of electrodes and printing ceramic nanomaterial films on the electrodes. A second layer of electrodes is printed on the nanomaterial films of ceramics to form an electroded film array. The electroded film array is sintered. Properties of the sintered electroded film array are measured and one of the array elements with properties suited for the particular application is identified.
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: August 17, 2010
    Assignee: PPG Industries Ohio, Inc.
    Inventors: Tapesh Yadav, Clayton Kostelecky
  • Patent number: 7770279
    Abstract: A micro-machined ultrasonic transducer substrate for immersion operation is formed by a particular arrangement of a plurality of micro-machined membranes that are supported on a silicon substrate. The membranes, together with the substrate, form surface microcavities that are vacuum sealed to provide electrostatic cells. The cells can operate at high frequency and can cover a broader bandwidth in comparison with conventional piezoelectric bulk transducers.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: August 10, 2010
    Assignee: VERMON
    Inventors: An Nguyen-Dinh, Nicolas Felix, Aimé Flesch
  • Patent number: 7758913
    Abstract: New protective coating layers for use in wet etch processes during the production of semiconductor and MEMS devices are provided. The layers include a primer layer, a first protective layer, and an optional second protective layer. The primer layer preferably comprises an organo silane compound in a solvent system. The first protective layer includes thermoplastic copolymers prepared from styrene, acrylonitrile, and optionally other addition-polymerizable monomers such as (meth)acrylate monomers, vinylbenzyl chloride, and diesters of maleic acid or fumaric acid. The second protective layer comprises a highly halogenated polymer such as a chlorinated polymer which may or may not be crosslinked upon heating.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: July 20, 2010
    Assignee: Brewer Science Inc.
    Inventors: Chenghong Li, Kimberly A. Ruben, Tony D. Flaim
  • Publication number: 20100178419
    Abstract: The structure comprises at least a device, for example a microelectronic chip, and at least a getter arranged in a cavity under a controlled atmosphere delineated by a substrate and a sealing cover. The getter comprises at least one preferably metallic getter layer, and an adjustment sub-layer made from pure metal, situated between the getter layer and the substrate, on which it is formed. The adjustment sub-layer is designed to modulate the activation temperature of the getter layer. The getter layer comprises two elementary getter layers.
    Type: Application
    Filed: March 23, 2010
    Publication date: July 15, 2010
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventor: Xavier BAILLIN
  • Publication number: 20100176083
    Abstract: A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the microelectronic substrate includes a substrate material (such as borophosphosilicate glass) having an aperture with a conductive material (such as platinum) disposed in the aperture and a fill material (such as phosphosilicate glass) in the aperture adjacent to the conductive material. The fill material can have a hardness of about 0.04 GPa or higher, and a microelectronics structure, such as an electrode, can be disposed in the aperture, for example, after removing the fill material from the aperture. Portions of the conductive and fill material external to the aperture can be removed by chemically-mechanically polishing the fill material, recessing the fill material inwardly from the conductive material, and electrochemically-mechanically polishing the conductive material.
    Type: Application
    Filed: March 24, 2010
    Publication date: July 15, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Whonchee Lee, Scott G. Meikle, Guy Blalock
  • Publication number: 20100170702
    Abstract: An electrically conductive module is provided. The module includes a panel configured to engage with one or more conductive structural elements. The module further includes conductive layers formed on or in the panel. Each conductive layer has a terminal configured to be in electrical communication with at least one of the conductive structural elements. In one embodiment of the present invention, a first terminal is configured to be in electrical communication with a first conductive structural element and a second terminal is configured to be in electrical communication with a second conductive structural element. In another embodiment of the present invention, both a first terminal and a second terminal are configured to be in electrical communication with a first conductive structural element. In this embodiment, the first and second terminals are respectively configured to be in electrical communication with first and second conductive portions of the first conductive structural element.
    Type: Application
    Filed: September 2, 2009
    Publication date: July 8, 2010
    Applicant: USG INTERIORS, INC.
    Inventors: Daniel Boss, Scott Qualls, Terrance Z. Kaiserman, Keith J. Margolin, Michael Wassief, Liang Chai
  • Publication number: 20100163285
    Abstract: An electrical circuit structure employing graphene as a charge carrier transport layer. The structure includes a plurality of graphene layers. Electrical contact is made with one of the layer of the plurality of graphene layers, so that charge carriers travel only through that one layer. By constructing the active graphene layer within or on a plurality of graphene layers, the active graphene layer maintains the necessary planarity and crystalline integrity to ensure that the high charge carrier mobility properties of the active graphene layer remain intact.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Inventor: Ernesto E. Marinero
  • Publication number: 20100139969
    Abstract: Disclosed herein is a printed circuit board, including: metal bumps having constant diameters and protruding over an insulation layer; a circuit layer formed beneath the insulation layer; and vias passing through the insulation layer to connect the metal bumps with the circuit layer.
    Type: Application
    Filed: February 23, 2009
    Publication date: June 10, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Yong An, Ki Hwan Kim
  • Publication number: 20100136223
    Abstract: The present invention comprises methods and compositions of dielectric materials. The dielectric materials of the present invention comprise materials having a dielectric constant of more than 1.0 and less than 1.9 and/or a dissipation factor of less than 0.0009. Other characteristics include the ability to withstand a wide range of temperatures, from both high temperatures of approximately +260° C. to low temperatures of approximately ?200° C., operate in wide range of atmospheric conditions and pressures (e.g., a high atmosphere, low vacuum condition such as that found in the outer-space as well as conditions similar to those found at sea level or below sea level). The dielectric materials of the present invention may be used in the manufacture of composite structures that can be used alone or in combination with other materials, and can be used in electronic components or devices such as RF interconnects.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 3, 2010
    Inventor: Kevin G. NELSON
  • Patent number: 7713592
    Abstract: A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The nanolayer deposition process is a cyclic sequential deposition process, comprising the first step of introducing a first plurality of precursors to deposit a thin film with the deposition process not self limiting, then a second step of purging the first set of precursors and a third step of introducing a second plurality of precursors to modify the deposited thin film. The deposition step in the NLD process using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film such as a modification of film composition, a doping or a removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: May 11, 2010
    Inventors: Tue Nguyen, Tai Dung Nguyen
  • Publication number: 20100098960
    Abstract: A magnetic insulator nanolaminate device comprises a metal magnetic layer formed on a substrate, an insulating layer formed on the metal magnetic layer, wherein the insulating layer is formed by nitriding a portion of the metal magnetic layer, a chelating group layer formed on the insulating layer, and a metal seed layer bonded to the chelating group layer. The magnetic insulator nanolaminate device may be formed by depositing a metal layer on a substrate, converting a portion of the metal layer into an insulating layer using a nitridation process, and depositing a metal seed layer onto the insulating layer using a metal immobilization process, wherein the metal seed layer enables the deposition of a metal layer onto the insulating layer.
    Type: Application
    Filed: June 18, 2007
    Publication date: April 22, 2010
    Inventors: Juan E. Dominguez, Arnel M. Fajardo, Adrien R. Lavoie
  • Patent number: 7700149
    Abstract: An approach is provided for depositing a material onto a printed circuit board layer. The approach includes steps of treating surface of a base film, forming a tie layer on the base film, forming a metal conductive layer on the tie layer, and depositing a metal on the metal conductive layer by radiating electronic beams to form a metal plated layer thereon. The above steps are continuously performed in a vacuum chamber. The approach also includes an unwinding roller, film guide rollers, a surface treating part, tie layer and copper conductive layer, a vacuum depositing part for depositing a metal plated layer on the metal conductive layer by radiating electronic beams, and a winding roller, all of which are provided in a vacuum chamber.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: April 20, 2010
    Assignee: Toray Saehan Inc.
    Inventor: Jeong Cho
  • Publication number: 20100083490
    Abstract: A multilayer circuit board comprises core layers 101 and 102 made of a core material impregnated with resin, resin layers 111 and 112 interposed between the core layers 101 and 102, a wiring pattern 140 embedded in the resin layers 111 and 112. The core layers 101 and 102 have a thickness of 100 ?m or smaller, whereby the entire board can significantly be thinned. Furthermore, the less strong resin layers 111 and 112 are interposed between the hard core layers 101 and 102, whereby the entire board has increased strength.
    Type: Application
    Filed: December 8, 2009
    Publication date: April 8, 2010
    Inventors: KENICHI KAWABATA, Takaaki Morita
  • Publication number: 20100085801
    Abstract: The invention generally encompasses methods of forming thin films molecular based devices, and devices formed therefrom. Some embodiments relate to molecular memory cells, molecular memory arrays, electronic devices including molecular memory, and processing systems and methods for producing molecular memories. More particularly, the present invention encompasses methods and molecular based devices comprising a wetting layer and redox-active molecules.
    Type: Application
    Filed: October 1, 2009
    Publication date: April 8, 2010
    Inventors: Thomas A. Sorenson, Brian Eastep, Lee Gaherty, Timothy L. Snow
  • Patent number: 7693597
    Abstract: A substrate processing method for removing a resist film from a substrate having the resist film formed thereon comprises maintaining the inner region of the chamber at a prescribed temperature by putting a substrate in a chamber, denaturing the resist film by supplying ozone and a water vapor in such a manner that ozone is supplied into the chamber while a water vapor is supplied into the chamber at a prescribed flow rate, the amount of ozone relative to the amount of the water vapor being adjusted such that the dew formation within the chamber is prevented, and processing the substrate with a prescribed liquid material so as to remove the denatured resist film from the substrate.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: April 6, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Mitsunori Nakamori, Tadashi Iino, Noritaka Uchida, Takehiko Orii
  • Publication number: 20100065308
    Abstract: According to one non-limiting embodiment, a low conductive emission substrate includes a plurality of thin high dielectric strength insulating layers separated by a corresponding plurality of conductive layers, wherein one of the plurality of conductive layers is shorted to another one of the plurality of conductive layers.
    Type: Application
    Filed: September 18, 2008
    Publication date: March 18, 2010
    Inventors: Thomas A. Hertel, Erich H. Soendker, Horacio Saldivar
  • Patent number: 7676913
    Abstract: A method of manufacturing a wiring board includes steps of: providing a substrate; forming a first wiring layer on the substrate by photolithography; forming a first insulating layer by ink jetting so as to cover a part of the first wiring layer and expose an exposed section of the first wiring layer; and forming a second wiring layer by ink jetting partly over the first wiring layer, with the first insulating layer being between the part of the first wiring layer and a part of the second wiring layer. A wider variety of conductive material and insulating material can be used for forming the wiring layers and the insulating layers on the substrate by ink jetting, while the wiring board has a first wiring layer having high density.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: March 16, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Hideo Imai, Kazuaki Sakurada
  • Publication number: 20100059257
    Abstract: Disclosed are a method of electroless nickel-gold plating an object and a printed circuit board. The method in accordance with an embodiment of the present invention includes: forming a first nickel plated layer on a surface of the object; forming a second nickel plated layer on the first nickel plated layer; and forming a gold plated layer on the second nickel plated layer.
    Type: Application
    Filed: February 11, 2009
    Publication date: March 11, 2010
    Inventors: Jin-Hak CHOI, Seoung-Jae Lee, Bae-Kyun Kim, Eun-Ju Yang, Jong-Yun Kim, Yeo-Joo Yoon
  • Publication number: 20100058857
    Abstract: A SAW-based humidity sensor apparatus with integrated signal conditioning on the same substrate. A micro-electronic circuit can be processed at a silicon substrate to obtain on-chip signal conditioning internally and the silicon substrate can be covered with a protective layer of, for example, silicon nitride. Surface acoustic wave media (e.g., a ZnO film) can be coated on top of the protective layer. A humidity sensitive film and two sets of interdigital transducers can then be deposited on the surface acoustic wave media. The humidity sensitive film absorbs moisture and changes the receiving frequency at the two sets of interdigital transducers. The output from the two sets of interdigital transducers can be processed by the micro-electronic circuit, which eliminates common mode noise and generates an output signal proportional to the humidity value tested.
    Type: Application
    Filed: September 9, 2008
    Publication date: March 11, 2010
    Inventor: Wenwei Zhang
  • Publication number: 20100052177
    Abstract: Method for manufacturing a crossbar circuit on a substrate (1), the crossbar circuit comprising a first grid of first wires (10) and a second grid of second wires (17), the first wires extending in a first direction, the second wires extending in a second direction, the first direction and the second direction being arranged relative to each other to form a single two-dimensional wire grid, each first wire being separated from each second wire by an intermediate layer (14) located at a location where the first and second wires overlap; the method comprising: depositing an unprintable layer (2) on the substrate, imprinting a two-dimensional grid mask (5) into the unprintable layer by a mould (3); directionally depositing a first material (8) in the first direction on the grid mask; and directionally depositing a second material (15) in the second direction on the grid mask, the grid mask acting as a shadow mask during the directional deposition of the first and second material.
    Type: Application
    Filed: May 24, 2006
    Publication date: March 4, 2010
    Applicant: NXP B.V.
    Inventor: Peter Bartus Leonard Meijer
  • Publication number: 20100044086
    Abstract: A printed wiring board having a conductor circuit comprising a copper layer adjacent to an insulating layer and an electroless gold plating, wherein the insulating layer has ten-point mean surface roughness (Rz) of 2.0 ?m or less is provided. According to the present invention, there is no such a defect that gold plating is deposited on a resin, and fine wiring formation with accuracy is realized.
    Type: Application
    Filed: November 6, 2009
    Publication date: February 25, 2010
    Inventors: Kenji Takai, Norio Moriike, Kenichi Kamiyama, Katsuyuki Masuda, Kiyoshi Hasegawa
  • Publication number: 20100038116
    Abstract: A printed circuit board includes an insulating layer, a copper layer formed on the insulating layer and a reinforcing layer formed on the copper layer at opposite sides of the given portion. The copper layer includes a plurality of electrical traces at a given portion thereof. A thickness of the reinforcing layer increases in a direction away from the given portion. A method for manufacturing the printed circuit board is also provided in this disclosure.
    Type: Application
    Filed: February 20, 2009
    Publication date: February 18, 2010
    Applicant: FOXCONN ADVANCED TECHNOLOGY INC.
    Inventors: CHUNG-JEN TSAI, CHIA-CHENG CHEN, HUNG-YI CHANG, TUNG-YAO KUO, CHENG-HSIEN LIN
  • Publication number: 20100012359
    Abstract: The invention relates to a coated article which has (i) at least one electrically non-conducting base layer, (ii) at least one layer of copper and/or a copper alloy, and (iii) a layer which contains at least one electrically conductive polymer, wherein the copper or copper alloy layer (ii) is positioned between the base layer (i) and the layer containing the conductive polymer (iii), and which is characterized in that the layer (iii) contains at least one precious metal or at least one semiprecious metal or a mixture thereof. The invention also relates to a process for its production and also its use for the prevention of corrosion and to preserve the solderability of printed circuit boards.
    Type: Application
    Filed: August 24, 2007
    Publication date: January 21, 2010
    Applicant: ORMECON GMBH
    Inventor: Bernhard Wessling
  • Publication number: 20100006326
    Abstract: A method of manufacturing ULSI wiring in which wiring layers are separately formed via a diffusion prevention layer with an insulating interlayer portion made of SiO2. The method comprises the steps of treating, with a silane compound, an SiO2 surface on which the insulating interlayer portion is to be formed, performing catalyzation with an aqueous solution containing a palladium compound, forming the diffusion prevention layer by electroless plating, and then forming the wiring layer on this diffusion prevention layer. Furthermore, a capping layer is formed on the wiring layer by electroless plating. Consequently, the diffusion prevention layer having good adhesive properties can all be formed through a simple process by wet processes, and further, the wiring layer can directly be formed on this diffusion prevention layer by the wet process. In addition, the capping layer can directly be formed on this wiring layer by electroless plating.
    Type: Application
    Filed: September 23, 2009
    Publication date: January 14, 2010
    Applicants: NEC ELECTRONICS CORPORATION, WASEDA UNIVERSITY
    Inventors: Kazuyoshi Ueno, Tetsuya Osaka, Nao Takano
  • Patent number: 7641934
    Abstract: There are provided a process for the production of an entry sheet for drilling, comprising preparing a water-soluble resin composition solution by using a mixed solvent containing water and isopropyl alcohol in a specific ratio as a solvent of a water-soluble resin composition, then applying the solution to a sheet-like base material and drying the resultant base material to form a resin layer on the base material, and a method of drilling a printed wiring board material using the above entry sheet. According to the present invention, the problems of remaining bubbles in the resin layer and a decrease in surface flatness and smoothness due to the occurrence of a ridge, which are caused because the melting point of the water-soluble resin is lower than the boiling point of water, are overcome, and an entry sheet for drilling excellent in hole position accuracy is provided.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: January 5, 2010
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Reiki Akita, Shinya Komatsu, Takuya Hasaki
  • Patent number: 7638161
    Abstract: A method and apparatus for controlling dopant concentration during borophosphosilicate glass film deposition on a semiconductor wafer to reduce consumption of nitride on the semiconductor wafer. In one embodiment of the invention, the method starts by placing a substrate having a nitride layer in a reaction chamber and providing a silicon source, an oxygen source and a boron source into the reaction chamber while delaying providing a phosphorous source into the reaction chamber to form a borosilicate glass layer over the nitride layer. The method continues by providing the silicon, oxygen, boron and phosphorous sources into the reaction chamber to form a borophosphosilicate film over the borosilicate glass layer.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: December 29, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Kevin Mukai, Shankar Chandran
  • Patent number: 7632428
    Abstract: A method of synthesizing doped semiconductor nanocrystals.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: December 15, 2009
    Assignee: The Board of Trustees of the University of Arkansas
    Inventors: Xiaogang Peng, Narayan Pradhan
  • Publication number: 20090283302
    Abstract: Disclosed are a printed circuit board and a manufacturing method thereof. The printed circuit board in accordance with the present invention includes: a circuit laminate, a solder resist laminated on the circuit laminate, a metal support layer formed on the solder resist, a stiffener formed on the metal support layer.
    Type: Application
    Filed: January 7, 2009
    Publication date: November 19, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seok-Kyu Lee, Shuhichi Okabe, Seung-Hyun Cho, Jae-Joon Lee
  • Publication number: 20090283305
    Abstract: A tin-silver coating for use with circuit boards, which can include a conductive circuit with an exposed surface disposed on a substrate. The tin-silver coating covers the exposed surface of the conductive circuit. The conductive circuit can include electrical traces, contact pads and vias, each of which may include or be formed of copper. In one embodiment, the tin-silver coating can include a tin weight percentage between 85 and 99.5%, while the silver weight percentage can be between 0.5 and 15%. In one embodiment the tin-silver coating can be between 35 and 60 millionths of an inch. A barrier plate may also be included between the conductive circuit and the tin-silver coating.
    Type: Application
    Filed: May 14, 2009
    Publication date: November 19, 2009
    Applicant: Interplex Industries, Inc.
    Inventors: Joseph J. Lynch, Richard Schneider
  • Patent number: 7611747
    Abstract: This invention provides a material for a multi-layer circuit board, excellent in insulating property and burying properties and free from occurrence of cracks, a production method, and a multi-layer circuit board using the insulating material. The invention provides an insulating material having a curable composition layer wherein the curable composition layer contains 0 to 50 pieces/cm2 of foreign matter having particle sizes falling within a range of 30 to 50 ?m, a production method, and a production method for a multi-layer circuit board using the insulating material.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: November 3, 2009
    Assignee: Zeon Corporation
    Inventors: Kazuyuki Onishi, Toshiyasu Matsui, Hiroshi Kurakata, Masahiko Sugimura
  • Patent number: 7604834
    Abstract: The present invention discloses a method including: providing a substrate; and sequentially stacking layers of two or more diamond-like carbon (DLC) films over the substrate to form a composite dielectric film, the composite dielectric film having a k value of about 1.5 or lower, the composite dielectric film having a Young's modulus of elasticity of about 25 GigaPascals or higher.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: October 20, 2009
    Assignee: Intel Corporation
    Inventor: Kramadhati V. Ravi
  • Publication number: 20090242263
    Abstract: A system and method for providing shielding to an electrical system is disclosed. A conformal shield is formed by applying a conformal insulating coating to an electrical system. A plurality of openings are formed in the insulating coating at desired locations and a first metallic layer is deposited over the insulating coating and in each of the plurality of openings, the first metallic layer being electrically connected with the circuit board at the desired locations. A second metallic layer is then deposited onto the first metallic layer to increase a thickness of the metallic layers.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Inventors: Christopher James Kapusta, Donald Cunningham, Richard Joseph Saia
  • Publication number: 20090229865
    Abstract: A conductor for a flexible substrate, used for a flexible flat cable or disposed inside a flexible printed-circuit board, according to the present invention comprises: a base conductor made of Cu or Cu-alloy; a plating film made of Sn or Sn-alloy formed on a surface of the base conductor; and a surface oxide film formed on a surface of the plating film, in which the surface oxide film includes oxide of an element other than Sn or a mixture of Sn oxide and oxide of an element other than Sn.
    Type: Application
    Filed: March 11, 2008
    Publication date: September 17, 2009
    Inventors: Takayuki Tsuji, Toshiyuki Horikoshi, Masato Ito
  • Publication number: 20090226672
    Abstract: The present invention provides methods of fabricating microelectronics structures and the resulting structures formed thereby using a dual-layer, light-sensitive, wet-developable bottom anti-reflective coating stack to reduce reflectance from the substrate during exposure. The invention provides dye-filled and dye-attached compositions for use in the anti-reflective coatings. The anti-reflective coatings are thermally crosslinkable and photochemically decrosslinkable. The bottom anti-reflective coating stack has gradient optical properties and develops at the same time as the photoresist. The method and structure are particularly suited to high-NA lithography processes.
    Type: Application
    Filed: February 19, 2009
    Publication date: September 10, 2009
    Applicant: Brewer Science, Inc.
    Inventors: Jim D. Meador, Douglas J. Guerrero, Ramil-Marcelo L. Mercado
  • Patent number: 7585541
    Abstract: A printed circuit board is by formed by laminating an interlaminar insulating layer on a conductor circuit of a substrate, in which the conductor circuit is comprised of an electroless plated film and an electrolytic plated film and a roughened layer is formed on at least a part of the surface of the conductor circuit.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: September 8, 2009
    Assignee: IBIDEN Co., Ltd.
    Inventors: Yoshinori Wakihara, Kazuhito Yamada
  • Publication number: 20090205858
    Abstract: Circuit carrier having a metal support layer, at least some portions of which are covered by a dielectric layer, the latter having a plurality of pores, with the pores being sealed by glass at least on the opposite side of the dielectric layer to the support layer.
    Type: Application
    Filed: December 3, 2008
    Publication date: August 20, 2009
    Inventor: Bernd Haegele
  • Patent number: 7575776
    Abstract: A phase changeable memory element is formed by conformally forming a phase changeable material film in a contact hole on a substrate so as to create a void in the phase changeable material film in the contact hole. A capping film is formed on the phase changeable material film, and the void is at least partially closed by a thermal treatment that is sufficient to reflow the phase changeable material film in the void.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: August 18, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hideki Horii
  • Patent number: 7572480
    Abstract: A multilayer ceramic structure is formed by building up a plurality of layers by sequentially coating a substrate with a series of suspensions comprising particles in a fluid medium. A composition of the sequential layers are varied to produce a structure with the desired properties. The thickness of the layers can be controlled by rheological properties of the suspension and/or by the utilization of a gelling or coagulating agent. An advantage of this method is that complete drying between the subsequent coatings is not required.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: August 11, 2009
    Assignee: Federal-Mogul World Wide, Inc.
    Inventors: James L. May, John W. Hoffman, William J. Walker, Jr.
  • Patent number: 7572481
    Abstract: A pattern forming method, for laminating a layer of a pattern on a base by supplying to the base a material for forming the pattern from a supply section for supplying the material based on information of the pattern, comprises the step of adjusting a relative positional relation between a forming surface to which the layer of the pattern is formed and the supply section with respect to a direction in which the pattern is laminated, by using the information.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: August 11, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Michinori Shinkai, Satoshi Suzuki
  • Publication number: 20090186169
    Abstract: An electronic device includes a multilayer circuit board having a non-planar three-dimensional shape defining a battery component receiving recess. The multilayer circuit board may include at least one pair of liquid crystal polymer (LCP) layers, and at least one electrically conductive pattern layer on at least one of the LCP layers and defining at least one battery electrode adjacent to the battery component receiving recess. The electronic device may further include a battery component within the battery component receiving recess and coupled to the at least one battery electrode to define a battery.
    Type: Application
    Filed: January 17, 2008
    Publication date: July 23, 2009
    Applicant: Harris Corporation
    Inventors: Lawrence Wayne Shacklette, Louis Joseph Rendek, JR.
  • Publication number: 20090183911
    Abstract: A wiring board includes an external connection terminal of a cylindrical shape, in which an electrode terminal of the electronic component to be mounted is fitted. In one configuration, a portion of the external connection terminal is electrically connected to a pad portion formed on an electronic component mounting surface side of the wiring board, and the external connection terminal is curvedly formed in such a shape that the outer periphery of the electrode terminal comes into close contact with the inner periphery of the middle portion of the external connection terminal when the electrode terminal is inserted into the external connection terminal.
    Type: Application
    Filed: January 5, 2009
    Publication date: July 23, 2009
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Masahiro SUNOHARA, Kei Murayama, Takaharu Yamano
  • Publication number: 20090151984
    Abstract: A composite resin molded article produced by impregnating cloth made from long fibers of a liquid crystal polymer with a curable resin composition which comprises a polymer (A) and a curing agent (B), the polymer (A) having a weight average molecular weight of 10,000 to 250,000 and containing 5 to 60 mol % of a carboxyl group or a carboxylic anhydride group; a method for manufacturing the composite resin molded article; a cured product produced by curing the composite resin molded article; a laminate made by laminating a substrate having a conductive layer (I) on the surface and an electrical insulating layer made of the cured product; a method for manufacturing the laminate; a multilayer circuit board comprising the laminate and a conductive layer (II) formed on an electrical insulating layer of the laminate; a method for manufacturing the circuit board; and an electronic device having the multilayer circuit board are provided.
    Type: Application
    Filed: August 25, 2006
    Publication date: June 18, 2009
    Applicant: ZEON CORPORATION
    Inventor: Makoto Fujimura
  • Patent number: 7537668
    Abstract: A method of fabricating a high density printed circuit board by applying a strippable adhesive layer on a reinforced substrate (rigid substrate or carrier film) used as a base substrate, forming a metal foil on the adhesive layer by means of plating, lamination or sputtering, and forming a high density circuit on the metal foil serving as a seed layer by means of pattern plating. Specifically, the method of the current invention includes the steps of attaching adhesive means to one surface of a reinforced substrate (rigid substrate or carrier film), forming a seed layer on the adhesive means and forming a circuit pattern on the seed layer, laminating an insulating layer on the circuit pattern and removing the reinforced substrate (rigid substrate or carrier film), and removing the seed layer.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: May 26, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Ryoichi Watanabe
  • Publication number: 20090107692
    Abstract: According to an aspect of the present invention, there is provided a method for manufacturing a MEMS package, the method including: forming a MEMS device on a substrate; forming a sacrificing member on the MEMS device; forming a cavity formation film on the sacrificing member; forming a through hole in the cavity formation film at a portion other than above the MEMS device; removing the sacrificing member through the through hole, thereby forming a cavity around the MEMS device; and forming a seal layer on the cavity formation film to block the through hole and to seal the cavity, by performing a film forming process in which a seal layer material is straightly applied in a direction of perpendicular to a surface of the substrate.
    Type: Application
    Filed: October 16, 2008
    Publication date: April 30, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshiaki SHIMOOKA
  • Patent number: 7507434
    Abstract: An approach is provided for laminating layers for a flexible printed circuit board. The approach includes a method and apparatus for providing a base substrate and the surface of the base substrate is treated by radiating ion beams using a gas mixture including oxygen and argon to improve adhesive strength and heat resistance. A tie layer can be formed on the based film to prevent a metal conductive layer from diffusion and to increase the adhesive strength.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: March 24, 2009
    Assignee: Toray Saehan Inc.
    Inventors: Jeong Cho, Young Kwan Lee, Young Seop Kim
  • Patent number: 7498064
    Abstract: A phase changeable memory element is formed by conformally forming a phase changeable material film in a contact hole on a substrate so as to create a void in the phase changeable material film in the contact hole. The void is at least partially closed by impinging a laser beam on the phase changeable material film sufficiently to reflow the phase changeable material film in the void.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: March 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hideki Horii
  • Patent number: 7479297
    Abstract: There provided a method of manufacturing a multi-layered wiring board having at least two conductor layers, an interlayer insulation layer provided between the conductor layers, and a conductor post that electrically connects the conductor layers, on a substrate. In the method, the conductor post is formed by repeatedly performing: coating a droplet containing a conductive material, applying light energy to the coated droplet, and accumulating and coating a subsequent droplet on the droplet to which the light energy is applied.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: January 20, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Hirotsuna Miura
  • Publication number: 20090004504
    Abstract: A circuit system comprising: forming a lower electrode over a substrate; forming a resistive film over the lower electrode; forming a multi-layered insulating stack over a portion of the resistive film; and forming an upper electrode over a portion of the multi-layered insulating stack.
    Type: Application
    Filed: June 27, 2007
    Publication date: January 1, 2009
    Inventors: Yaojian Lin, Haijing Cao, Qing Zhang