Electron Beam Patents (Class 430/942)
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Patent number: 7476880Abstract: A shaped particle beam writing strategy can be used to write a pattern with a particle beam onto a substrate. The pattern comprises a circuit design that is fractured into a plurality of arbitrary polygons. The writing strategy comprises transforming and fracturing the arbitrary polygons into a plurality of restricted polygons, each restricted polygon being represented by a location coordinate, at least two dimension coordinates, and at least one external edge indicator. Thereafter, the restricted polygons are tiled into a set of tiles comprising interior tiles and external edge tiles. Flash data is assigned for each tile such that the interior tiles are assigned a first flash area and the external edge tiles are assigned a second flash area that is smaller than the first flash area. The flash data is arranged in a selected order to write the pattern with a modulated particle beam, such as an electron beam, on a substrate.Type: GrantFiled: October 3, 2005Date of Patent: January 13, 2009Assignee: Applied Materials, Inc.Inventors: Benyamin Buller, Richard L. Lozes, Robert M. Sills
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Patent number: 7468227Abstract: We are able to reduce the average process bias in a patterned reticle by treating the developed, patterned photoresist which is used to transfer a pattern to the reticle with a silicon-containing reagent prior to the pattern transfer. The process bias is a measure of the difference between a nominal feature critical dimension (CD) produced in a patterned reticle and the nominal isofocal CD for the feature. Improvement of the average process bias is directly related to an improved resolution in the mask features. The reduction in average process bias achievable using the method of the invention typically ranges from about 30% to about 70%. This reduction in average process bias enables the printing of smaller features.Type: GrantFiled: November 16, 2004Date of Patent: December 23, 2008Assignee: Applied Materials, Inc.Inventors: Melvin Warren Montgomery, Alexander Buxbaum
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Patent number: 7462428Abstract: A complementary mask has a plurality of pattern forming regions 34a, 34 having arranged on them complementary patterns 26, 28 obtained by dividing first circuit patterns into complementary patterns 26, 28 complementary with each other and formed by openings. The complementary patterns 26, 28 are arranged in the pattern forming regions 34a, 34b so that pattern densities of the pattern forming regions 34a, 34b become substantially the same.Type: GrantFiled: February 6, 2006Date of Patent: December 9, 2008Assignee: Sony CorporationInventor: Kaoru Koike
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Patent number: 7435517Abstract: A method for reducing the fogging effect in an electron beam lithography system wherein the exposure is controlled in order to obtain resulting pattern after processing which conforms to design data. A model for the fogging effect is fitted by individually changing at least the basic input parameters of the control function, the function type is chosen in accordance to the Kernel type used in the proximity corrector. The proximity effect is considered as well and an optimized set of parameters is obtained in order to gain a common control function for the proximity and fogging effect. The pattern writing with an e-beam lithographic system is controlled by the single combined proximity effect control function and the fogging effect control function in only one data-processing step using the same algorithms as are implemented in a standard proximity corrector.Type: GrantFiled: June 23, 2005Date of Patent: October 14, 2008Assignee: Vistec Electron Beam GmbHInventors: Peter Hudek, Dirk Beyer, Lemke Melchior
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Patent number: 7425396Abstract: A method for reducing an overlay error of structures of a layer to be patterned relative to those of a reference layer includes formation of standard measurement marks assigned to one another in the two layers for determining an overlay error and for setting up further measurement marks for determining an additional optical imaging error of the projection system at least in the current layer. The further measurement marks have a geometry adapted to the geometry of selected structures of the circuit patterns to be transferred by projection from masks onto semiconductor substrates. An imaging error affects circuit structures and further measurement marks in the same way. An alignment correction for a subsequent exposure can be calculated from the measured positional deviations between the two standard measurement marks and between the standard measurement mark and the further measurement mark of the layer currently to be patterned.Type: GrantFiled: September 30, 2004Date of Patent: September 16, 2008Assignee: Infineon Technologies AGInventors: Stefan Gruss, Detlef Hofmann, Rainer Pforr, Mario Hennig, Guido Thielscher, Hans-Georg Froehlich
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Patent number: 7419764Abstract: Provided is a method of fabricating a nanoimprint mold which can form sub-100 nm fine pattern structures. The method includes forming patterns on a first substrate using an E-beam lithography (EBL) process, and transferring the patterns formed on the first substrate to a second substrate using a nanoimprint lithography (NIL) process to complete an NIL mold. Accordingly, the method can easily fabricate the nanoimprint mold at low costs on a quartz or glass substrate, which is not suitable for an EBL process to produce sub-100 nm patterns, by utilizing the advantages of the EBL process with a resolution of tens of nanometers.Type: GrantFiled: August 17, 2006Date of Patent: September 2, 2008Assignee: Electronics and Telecommunications Research InstituteInventors: Jong Hyurk Park, Hyo Young Lee, Nak Jin Choi, Jung Hyun Lee, Gyeong Sook Bang
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Patent number: 7407736Abstract: Methods for improving a single layer resist (SLR) patterning scheme, and in particular, its SLR layer and anti-reflective coating (ARC) etch selectivity, are disclosed. In one method, a patterned SLR layer over an anti-reflective coating (ARC) is provided and at least a portion of the patterned SLR layer and a portion of the ARC are exposed to radiation. The radiation may include, for example, an electron beam or an ion beam. The radiation exposure selectively breaks the polymer chains of the ARC and reduces the thickness of the ARC due to the loss of volatile function groups and free volume. As a result, the etch rate of the ARC is increased due to the conversion from polymer to monomer. Therefore, less resist will be consumed during, for example, an ARC open etch.Type: GrantFiled: January 31, 2006Date of Patent: August 5, 2008Assignee: International Business Machines CorporationInventors: Kuang-Jung J. Chen, Wu-Song S. Huang, Chung-Hsi J. Wu
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Patent number: 7388213Abstract: We have developed a method of registration of a particle beam to internal alignment targets present within photoresist areas which are to be imaged. The method does not affect the photoresist, so the quality of pattern produced in the resist after imaging is not affected. The method used for registration of the particle beam to internal alignment targets also can be used to align a pattern in real time, while the pattern is being created, with the internal alignment targets. The real time alignment during creation of a pattern image in the photoresist can be used to correct for drift, or thermal expansion, or gravitational sag, by way of example.Type: GrantFiled: September 23, 2005Date of Patent: June 17, 2008Assignee: Applied Materials, Inc.Inventor: Jeffrey S. Sullivan
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Patent number: 7388216Abstract: A pattern forming method is proposed for easy correction of a pattern-size variation occurring in an etching process. An energy beam is radiated onto a resist-applied target while the energy beam is adjusted to correct the pattern-size variation occurring in the etching process. The resist on the target is developed to form a resist pattern. The target is etched with the resist pattern as a mask, thus forming patterns thereon.Type: GrantFiled: June 6, 2007Date of Patent: June 17, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Munehiro Ogasawara
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Patent number: 7385209Abstract: Ion beam lithography technique wherein a higher amount of radiation energy is deposited to predetermined regions in the bulk if a suitable substrate. By selecting the radiation nature, its energy and the irradiation parameters a structure can be created in the bulk of the material leaving the surface essentially untouched.Type: GrantFiled: October 24, 2005Date of Patent: June 10, 2008Assignee: Haute Ecole Arc Ne-Be-JuInventors: Samuel Jaccard, Serguei Mikhailov, Frans Munnik
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Patent number: 7384711Abstract: A stencil mask includes a membrane forming thin layer having membrane areas and a border area that limits the membrane areas. The membrane areas have a plurality of pattern areas which include an aperture through which particle beams can permeate and non-pattern areas interposed between the pattern areas. A main strut supports the membrane areas and is formed on the border area of the membrane forming thin layer. An auxiliary strut is formed in the non-pattern areas inside the membrane pattern area such that the auxiliary strut divides the membrane areas into plural divided membrane areas. The auxiliary strut supports the divided membrane areas.Type: GrantFiled: April 19, 2004Date of Patent: June 10, 2008Assignee: Samsung Electronic Co., Ltd.Inventors: In-Sung Kim, Ho-Chul Kim
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Patent number: 7384724Abstract: A method for manufacturing optical components in a three-dimensional photonic crystal lattice. A first resist (9) is coated on a substrate (10) and exposed to an e-beam (11), to produce an imaged area (12). Another resist coating is applied to thicken the resist (13) and an interference exposure (15) is used to image the result. This is developed to form periodic voids (16), which may be filled with a materials having a high refractive index to form a pattern (18 and 12) when the resist (13) is removed.Type: GrantFiled: August 26, 2003Date of Patent: June 10, 2008Assignee: University of DelawareInventors: Janusz Murakowski, Dennis W. Prather
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Patent number: 7371483Abstract: Disclosed is a method for manufacturing a mask for focus monitoring, comprising forming a first opening portion and a second opening portion in a surface region of a transparent substrate, the second opening portion having a pattern shape corresponding to a pattern shape of the first opening portion, and being surrounded by a stack film formed of a halftone film on the transparent substrate and an opaque film on the halftone film, and radiating a charged beam onto a first region which includes an edge of the second opening portion and inside and outside regions which are respectively located inward and outward of the edge of the second opening portion, to etch that part of the transparent substrate which corresponds to the inside region.Type: GrantFiled: April 23, 2004Date of Patent: May 13, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Shingo Kanamitsu, Takashi Hirano, Kyoko Izuha, Soichi Inoue, Shinichi Ito
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Patent number: 7348130Abstract: The present invention describes a method including providing a substrate; forming a photoresist on the substrate; performing a post-apply bake on the photoresist; exposing the photoresist to actinic radiation; performing a post-exposure bake on the photoresist; developing the photoresist; and performing electron exposure on the photoresist to reduce line edge roughness.Type: GrantFiled: March 11, 2005Date of Patent: March 25, 2008Assignee: Intel CorporationInventor: Neil S. Wester
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Patent number: 7348129Abstract: An organic material film formed on a surface of an object to be processed is cured by electron beams irradiated thereon through a hydrocarbon radical generating gas. By employing the electron beams and the hydrocarbon radical generating gas, a deterioration of a k value of the organic material film and a reduction of a chemical resistance thereof are suppressed.Type: GrantFiled: March 29, 2004Date of Patent: March 25, 2008Assignee: Tokyo Electron LimitedInventors: Kazuyuki Mitsuoka, Minoru Honda, Song Yun Kang, Yusuke Saito
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Patent number: 7332252Abstract: A mask layout forming method includes designing an original layout in which a diagonal pattern of a first polygon is repeatedly arranged in a diagonal direction relative to a vertical-axis direction. Opposite edge sides of the diagonal pattern of the first polygon are corrected such that second polygons extending in a horizontal-axis direction are stacked at the opposite edge sides of the diagonal pattern of the first polygon to form a stair-shaped layout. The polygons are fractured in the horizontal-axis direction to provide data associated with the corrected layout to an electron beam exposure system. The diagonal pattern of the first polygon defines an active region and a device isolation layer along a 6F2 cell layout or a 4F2 cell layout.Type: GrantFiled: December 29, 2006Date of Patent: February 19, 2008Assignee: Hynix Semiconductor Inc.Inventors: Chun Soo Kang, Byoung Sub Nam
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Patent number: 7323291Abstract: The present invention relates to preparation of patterned workpieces in the production of semiconductor and other devices. Methods and devices are described utilizing resist and transfer layers over a workpiece substrate. The methods and devices produce small feature dimensions in masks and phase shift masks. The methods described may apply to both masks and direct writing on other workpieces having similarly small features, such as semiconductor, cryogenic, magnetic and optical microdevices.Type: GrantFiled: December 22, 2006Date of Patent: January 29, 2008Assignee: Micronic Laser Systems ABInventor: Torbjörn Sandström
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Patent number: 7316884Abstract: A 5-methylene-1,3-dioxolan-4-one derivative and a monomer and copolymer thereof and a resist composition containing the polymer or copolymer where the 5-methylene-1,3 -dioxolan-4-one derivative is of formula (1): wherein R1 represents a bridged cyclic hydrocarbon group containing 4 to 16 carbon atoms, or a linear or branched alkyl group containing 1 to 6 carbon atoms which has a bridged cyclic hydrocarbon group containing 4 to 16 carbon atoms as a substituent; R2 represents a hydrogen atom, or a linear or branched alkyl group containing 1 to 6 carbon atoms; or R1 and R2 represent a bridged cyclic hydrocarbon group containing 4 to 16 carbon atoms together with the carbon atom to which they are bound, provided that the alkyl group and the bridged cyclic hydrocarbon group may have at least one substituent selected from a group consisting of a linear or branched alkyl group containing 1 to 6 carbon atoms which may be optionally substituted, a hydroxy group, a carboxy group, an acyl group containing 2 to 6 carType: GrantFiled: October 22, 2002Date of Patent: January 8, 2008Assignee: Mitsubishi Rayon Co., Ltd.Inventors: Ryuichi Ansai, Yoshihiro Kamon, Tadayuki Fujiwara, Hideaki Kuwano, Atsushi Ootake, Hikaru Momose
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Patent number: 7306896Abstract: An electron beam duplication lithography apparatus and method for focusing electrons emitted from a mask plate as a result of an application of an electric field between a mask plate and a duplication plate. Irradiation of electrons from the mask plate is assisted through an electric field lens or magnetic field lens, or a combination thereof from an electron field emission material formed into a pattern on a flat surface of a substrate. The result is that a congruent or similar pattern is lithographed by electron beam exposure onto an electron beam resist film from a field emission film having the congruent or similar pattern to be created.Type: GrantFiled: February 14, 2006Date of Patent: December 11, 2007Inventor: Seiichi Iwamatsu
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Publication number: 20070281221Abstract: A stencil mask (10) for use in electron beam projection exposure includes a silicon base plate (12), an insulating film (14) formed on the silicon base plate, and a silicon film (16) formed on the insulating film. In the silicon base plate and the insulating film, an opening (18) penetrating them is provided; in the silicon film, a plurality of holes (20) penetrating it and continuous to the opening are provided. In the silicon base plate and the insulating film, at least one hole (22) penetrating them is provided, and in this hole, an electrically conducting substance (24) contacting the silicon base plate and the silicon film is disposed.Type: ApplicationFiled: May 30, 2007Publication date: December 6, 2007Applicant: HOLON CO., LTD.Inventor: Tokushige Hisatsugu
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Patent number: 7297460Abstract: A radiation curable ink composition comprising at least one initiator and at least one polyhedral oligomeric silsesquioxane (POSS) represented by the following empirical formula [R(SiO1.5)]n wherein n=4, 6, 8, 10, 12, 14, 16 and larger and each R is independently hydrogen, an inorganic group, an alkyl group, an alkylene group, an aryl group, an arylene group, or non-heterocyclic group-containing organo-functional derivatives of alkyl, alkylene, aryl or arylene groups; and a process for obtaining a colourless, monochrome or multicolour ink jet image comprising the steps of jetting one or more streams of ink droplets having the above-mentioned composition onto an ink-jet ink receiver material, and subjecting the obtained image to radiation curing.Type: GrantFiled: February 9, 2004Date of Patent: November 20, 2007Assignee: Agfa-GevaertInventors: Luc Vanmaele, Johan Loccufier, Roland Claes
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Publication number: 20070248893Abstract: A mask layout forming method includes designing an original layout in which a diagonal pattern of a first polygon is repeatedly arranged in a diagonal direction relative to a vertical-axis direction. Opposite edge sides of the diagonal pattern of the first polygon are corrected such that second polygons extending in a horizontal-axis direction are stacked at the opposite edge sides of the diagonal pattern of the first polygon to form a stair-shaped layout. The polygons are fractured in the horizontal-axis direction to provide data associated with the corrected layout to an electron beam exposure system. The diagonal pattern of the first polygon defines an active region and a device isolation layer along a 6F2 cell layout or a 4F2 cell layout.Type: ApplicationFiled: December 29, 2006Publication date: October 25, 2007Applicant: Hynix Semiconductor Inc.Inventors: Chun Soo Kang, Byoung Sub Nam
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Patent number: 7285365Abstract: An aspect of the present invention includes a method for patterning a workpiece covered at least partly with a layer sensitive to electromagnetic radiation by using a plurality of exposure beams having a predetermined separation in at least a first direction for exposing a pattern onto said workpiece, where said predetermined separation is fixed to an initial system pitch in said first direction, comprising the actions of: scaling a pattern pitch in said first direction to be an integer multiple of said system pitch, adjusting the initial system pitch in said first direction to be an adjusted system pitch to maintain a scale of said pattern, adjusting said predetermined separation of exposure beams to said adjusted system pitch. Other aspects of the present invention are reflected in the detailed description, figures and claims.Type: GrantFiled: February 13, 2004Date of Patent: October 23, 2007Assignee: Micronic Laser Systems ABInventor: Peter Ekberg
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Patent number: 7282318Abstract: The present invention relates to photoresist compositions for EUV and methods for forming photoresist patterns. More specifically, fine photoresist patterns: of less than 50 nm without collapse are formed with EUV (Extreme Ultraviolet) as an exposure light source by using a negative photoresist composition comprising a melamine derivative and polyvinylphenol.Type: GrantFiled: June 24, 2004Date of Patent: October 16, 2007Assignee: Hynix Semiconductor Inc.Inventor: Jae Chang Jung
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Patent number: 7270921Abstract: A pattern forming method is proposed for easy correction of a pattern-size variation occurring in an etching process. An energy beam is radiated onto a resist-applied target while the energy beam is adjusted to correct the pattern-size variation occurring in the etching process. The resist on the target is developed to form a resist pattern. The target is etched with the resist pattern as a mask, thus forming patterns thereon.Type: GrantFiled: February 10, 2003Date of Patent: September 18, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Munehiro Ogasawara
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Patent number: 7267927Abstract: A method for fabricating a semiconductor device and an equipment for fabricating the semiconductor device are described. According to the method and the equipment, a semiconductor substrate is irradiated with a particle beam through an opening formed in a thin film portion of a stencil mask having the thin film portion and a supporting portion supporting the thin film portion. The method and the equipment are controlled so that the supporting portion of the stencil mask can be irradiated with the fringe of the particle beam. As a result, the method and the equipment provide suppressing deterioration such as deformation or breakage of the stencil mask.Type: GrantFiled: December 23, 2003Date of Patent: September 11, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Shibata, Kyoichi Suguro
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Patent number: 7264909Abstract: An exposure parameter obtaining method comprising forming a charged reference pattern and a plurality of charged exposure patterns at a surface region of a to-be-exposed insulation substrate by projecting a charged beam with a first incident energy using a reference pattern whose exposure parameter has been known beforehand and all of selected exposure patterns to be corrected, forming electron signal images for the charged reference pattern and the plurality of charged exposure patterns on the basis of charged particles including secondary electrons by scanning the surface of the insulation substrate with a charged beam with a second incident energy lower than the first incident energy, and creating, on the basis of the electron signal images, the exposure parameters including at least one of position, focal point, astigmatism, rotation, and magnification for all of the selected exposure patterns to be corrected.Type: GrantFiled: November 8, 2005Date of Patent: September 4, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Tetsuro Nakasugi
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Patent number: 7261983Abstract: An apparatus and method for manufacturing and using a calibrated registration reference wafer in a semiconductor manufacturing facility where an archive media includes etched alignment attributes. Exposing a pattern of complementary alignment attributes onto the archive media such that the pattern of complementary alignment attributes overlay and interlock with the etched alignment attributes thereby forming completed alignment attributes. Then, measuring offsets in the completed alignment attributes and constructing a calibration file for the archive media based upon the offset measurements and other characteristic data of the exposure tool.Type: GrantFiled: March 8, 2006Date of Patent: August 28, 2007Assignee: Litel InstrumentsInventors: Adlai H. Smith, Robert O. Hunter, Jr.
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Publication number: 20070196769Abstract: Disclosed is a method of forming patterns in semiconductor devices by using photo resist patterns. These methods comprise forming photo resist patterns on a substrate. Inferior patterns are selected among the photo resist patterns. The inferior patterns are eliminated or shrunken by irradiating the selected inferior patterns with an electron beam.Type: ApplicationFiled: October 4, 2006Publication date: August 23, 2007Inventors: Sung-Gun Kang, Jin-Mo Kang, Jae-Ho Lee, Jun-Seop Lee
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Patent number: 7255976Abstract: Laser-engravable flexographic printing elements for the production of flexographic printing plates have relief layers comprising blends of hydrophilic polymers and hydrophobic elastomers. Said flexographic printing elements are used for the production of flexographic printing plates by means of laser engraving.Type: GrantFiled: November 15, 2002Date of Patent: August 14, 2007Assignee: XSYS Print Solutions Deutschland GmbHInventors: Margit Hiller, Jens Schadebrodt, Jürgen Kaczun, Thomas Telser, Wolfgang Wenzl
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Patent number: 7247412Abstract: An embodiment includes a method of correcting deviations of critical dimensions of patterns formed on a wafer in an extreme ultraviolet lithography (EUVL) process. The embodiment includes preparing a reflection photo mask having a reflection layer and absorption patterns that are formed on the reflection layer to define reflection regions therebetween. An exposure process is performed using the reflection photo mask, thereby forming the patterns on the wafer. Critical dimensions of the patterns are measured. A reference critical dimension is set based on the measured critical dimensions of the patterns. Critical dimension deviations are determined by comparing the measured critical dimensions of the patterns with the reference critical dimension. Energy beams having energies corresponding to the critical dimension deviations are locally irradiated onto the reflection layer, thus locally varying the thickness of the reflection layer.Type: GrantFiled: December 27, 2005Date of Patent: July 24, 2007Assignee: Samsung Electronics Co., Ltd.Inventor: Myoung-Soo Lee
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Publication number: 20070166646Abstract: Provided methods for forming a pattern using electron beam and cell masks for electron beam lithography. The methods may include forming a resist layer on a substrate, the resist layer including a first region, a second region surrounding the first region, and a third region surrounding the second region. The second may be irradiated with electron beam at a first dose, and the third region may be irradiated with an electron beam at a second dose less than the first dose. The cell mask may include a mask substrate and a shielding region disposed on the mask substrate. A transmitting region may extend a distance from the shielding region. A gray pattern region may be disposed around the transmitting region. The gray pattern region may include patterns having a pitch smaller than a resolution limit.Type: ApplicationFiled: November 1, 2006Publication date: July 19, 2007Inventors: Hee-Bom Kim, Seong-Woon Choi
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Patent number: 7241542Abstract: A process for controlling the proximity effect correction in an electron beam lithography system. The exposure is controlled in order to obtain resulting pattern after processing which is conform to design data. In a first step an arbitrary set patterns is exposed without applying the process for controlling the proximity correction. The geometry of the resulting test structures is measured and a set of measurement data is obtained. Within a numerical range basic input parameters for the parameters ?, ? and ?, are derived from the set of measurement data. A model is fitted by individually changing at least the basic input parameters ?, ? and ? of a control function to measurement data set and thereby obtaining an optimised set of parameters. The correction function is applied to an exposure control of the electron beam lithography system during the exposure of a pattern according to the design data.Type: GrantFiled: June 23, 2005Date of Patent: July 10, 2007Assignee: Leica Microsystems Lithography GmbHInventors: Peter Hudek, Dirk Beyer
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Patent number: 7232631Abstract: The present invention relates to an SOI substrate as a mask substrate for the charged particle beam exposure of which a silicon oxidized film has a suitable thickness for the fabrication of a mask, a silicon membrane layer has a suitable thickness as a mask membrane and is a low stress membrane having no defects and excellent uniformity and relates to its forming method. The SOI substrate is an SOI wafer which is obtained by forming an oxidized film on a first silicon wafer, forming a separation layer by hydrogen ion implantation into the first silicon wafer via the oxidized film, bonding the first silicon wafer onto a second silicon wafer, and cleaving the first silicon wafer from the second silicon wafer at the separation layer so that a silicon membrane layer is formed on the second silicon layer via the oxidized film.Type: GrantFiled: May 4, 2004Date of Patent: June 19, 2007Assignee: Dai Nippon Prinitng Co., Ltd.Inventors: Kenichi Morimoto, Yoshinori Kinase, Yuki Aritsuka
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Patent number: 7229743Abstract: A fine pattern having first elements within track widths and second elements, which are shifted half a track pitch from the first elements, are drawn across the entire surface of a disk accurately and at high speed. A transfer pattern for a magnetic transfer master carrier is drawn by scanning an electron beam on a disk coated with resist. The first elements and the second elements, which are shifted half a track pitch such that they straddle adjacent tracks, are drawn. While the disk is rotated unidirectionally, the electron beam is deflected in the radial direction within a single track of the disk to draw the first elements. Deflection of the electron beam in the radial direction is shifted half a track, to draw the second elements that straddle adjacent tracks at the same time.Type: GrantFiled: June 30, 2005Date of Patent: June 12, 2007Assignee: Fuji Photo Film Co., Ltd.Inventors: Toshihiro Usa, Kazunori Komatsu
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Patent number: 7229742Abstract: Methods to reduce the write time for forming mask patterns having angled and non-angled features using electron beam lithography are disclosed. In one exemplary embodiment, non-angled features of the mask pattern are formed by exposure to an electron beam. The orientation of the substrate and a path of the generally rectangular-shaped shot from the electron beam may be relatively altered such that the substrate is exposed to the electron beam to form the angled features as if they were non-angled features. In another exemplary embodiment, the electron beam lithography system determines whether it is necessary to relatively alter the orientation of the substrate and a path of the generally rectangular-shaped shot from the electron beam to form the angled features based on the number of angled features and the time required for relatively altering the orientation. Electron beam lithography systems employing a rotatable stage, rotatable apertures, or both, are also disclosed.Type: GrantFiled: April 14, 2004Date of Patent: June 12, 2007Assignee: Micron Technology, Inc.Inventor: Baorui Yang
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Patent number: 7226723Abstract: Methods to reduce the write time for forming mask patterns having angled and non-angled features using electron beam lithography are disclosed. In one exemplary embodiment, non-angled features of the mask pattern are formed by exposure to an electron beam. The orientation of the substrate and a path of the generally rectangular-shaped shot from the electron beam may be relatively altered such that the substrate is exposed to the electron beam to form the angled features as if they were non-angled features. In another exemplary embodiment, the electron beam lithography system determines whether it is necessary to relatively alter the orientation of the substrate and a path of the generally rectangular-shaped shot from the electron beam to form the angled features based on the number of angled features and the time required for relatively altering the orientation. Electron beam lithography systems employing a rotatable stage, rotatable apertures, or both, are disclosed.Type: GrantFiled: September 6, 2006Date of Patent: June 5, 2007Assignee: Micron Technology, Inc.Inventor: Baorui Yang
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Patent number: 7220531Abstract: The invention relates to a resist for electron beam lithography and to a process for producing photomasks for optical lithography. The inventive resist includes repeating units that are derived from maleic anhydride and that can act as an anchor group for the subsequent binding of silicon-containing groups. The etch stability of the resist can thus be subsequently increased so that there is no dimensional loss on transfer of the resist structure to a chromium layer arranged under the resist.Type: GrantFiled: February 28, 2003Date of Patent: May 22, 2007Assignee: Infineon Technologies AGInventors: Klaus Elian, Michael Sebald
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Patent number: 7205078Abstract: A method for generating backscattering intensity with which charged particles are backscattered to a resist layer when charged particle beam is irradiated onto the resist layer which is formed on plural layers, each of which includes a pattern of one substance or a plurality of substances. For the nth layer from the resist layer among the plural layers, there is provided, for each of the substances in the nth layer, a reflection coefficient rn, which corresponds with the number of particles reflected by the nth layer; a transmission coefficient tn, which corresponds with the number of particles transmitted by the nth layer; and a scatter distribution in which the charged particles are scattered within the nth layer. The generation method comprises a first step of generating the backscattering intensity by using the reflection coefficient rn, the transmission coefficient tn, and the scatter distribution.Type: GrantFiled: May 26, 2004Date of Patent: April 17, 2007Assignee: Fujitsu LimitedInventors: Morimi Osawa, Kozo Ogino
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Patent number: 7192686Abstract: Carborane based PAG's are bulky, produce a strong and large superacid, and have polarities that are compatible with the chemically amplified polymers typically used in photoresists. Carborane based PAG's also provide another broad class of bulky PAG's that may be used in photoresist formulations that offer flexibility in acid strength and polarity through changes in chemical structure. These PAG's may be used with EUV wavelengths, 157 nm, or 193 nm. Resolution and critical dimension control may be improved through the use of carborane based PAG's.Type: GrantFiled: March 31, 2004Date of Patent: March 20, 2007Assignee: Intel CorporationInventor: Robert P. Meagley
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Patent number: 7179568Abstract: A dark-field imaging method for detecting defects in reflective lithography masks (e.g., extreme ultraviolet (EUV) masks) used, e.g., in processes for the fabrication of microelectronic devices. A mask blank is coated with a photoresist layer having a fluorescent dye incorporated therein. The photoresist layer is exposed to a source of radiation (e.g., EUV radiation or glancing soft X-rays). In areas of the mask blank having defects the combined direct and reflected radiation will be insufficient fully to expose the photoresist layer. After development, photoresist will remain on the mask blank surface in areas corresponding to defects. Illumination with the excitation wavelength of the fluorescent dye reveals the location of any remaining photoresist, which can be detected using an optical microscope, thereby to detect defects in the mask blank.Type: GrantFiled: July 10, 2003Date of Patent: February 20, 2007Assignee: Wisconsin Alumni Research FoundationInventors: Francesco Cerrina, Adam Pawloski, Lin Wang
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Patent number: 7179571Abstract: An optical apparatus used for the efficient characterization of photoresist material includes at least one grating interferometer having at least two gratings that together define an optical recombination plane. An optical stop blocks any zeroth order beam from propagating through the apparatus. A reticle positioned at the recombination plane has at least one fiducial marking therein. A lithographic imaging optical tool is positioned so that its input optical plane is substantially coincident with the optical recombination plane and its output imaging plane is substantially coincident with photoresist on a wafer. The apparatus writes in the photoresist latent, sinusoidal grating patterns, preferably of different spatial frequencies, as well as at least one fiducial mark whose pattern is determined by the marking in the reticle. After the photoresist is developed, its intrinsic spatial resolution may be determined by automated means.Type: GrantFiled: February 9, 2006Date of Patent: February 20, 2007Assignee: International Business Machines CorporationInventors: William Dinan Hinsberg, III, John Allen Hoffnagle, Frances Anne Houle, Martha Inez Sanchez
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Patent number: 7175970Abstract: In an embodiment, a trench is formed above a via from a photo resist (PR) trench pattern in a dielectric layer. The trench is defined by two sidewall portions and base portions. The base portions of the sidewalls are locally treated by a post treatment using the PR trench pattern as mask to enhance mechanical strength of portions of the dielectric layer underneath the base portions. Seed and barrier layers are deposited on the trench and the via. The trench and via are filled with a metal layer. In another embodiment, a trench is formed from a PR trench pattern in a dielectric layer. A pillar PR is deposited and etched to define a pillar opening having a pillar surface. The pillar opening is locally treated on the pillar surface by a post treatment to enhance mechanical strength of portion of the dielectric layer underneath the pillar surface.Type: GrantFiled: November 22, 2005Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Jun He, Jihperng Leu
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Patent number: 7175952Abstract: A method of generating mask distortion data capable of improving accuracy of distortion measurement, an exposure method using the same and a method of producing a semiconductor device, wherein a production mask is produced by a first thin film formed with a predetermined pattern, and a positional accuracy measurement mask is produced by forming second positional accuracy measurement marks at substantially same positions as those of the first positional accuracy measurement marks on a mask blanks having a second thin film, positions of the second positional accuracy measurement marks and third positional accuracy measurement marks of the positional accuracy measurement mask are measured, a correlation function of the both are calculated, positions of the first positional accuracy measurement marks of the production mask are measured, and mask distortion data on the first thin film of the production mask is generated by using the correlation function.Type: GrantFiled: May 19, 2004Date of Patent: February 13, 2007Assignee: Sony CorporationInventor: Shinji Omori
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Patent number: 7160670Abstract: A scintillating structure for aligning an electron or ion beam using a detector while exposing a wafer, which may be a wafer or mask, is described. The structure is formed by a resist including a polymer with carboxylic acid groups, anhydride groups, and an acid-sensitive group, for instance tert.-butylester; a photoreactive compound which releases an acid upon irradiation with UV light, electrons, or ions; a solvent; and at least one scintillating substance such as anthracene, naphthaline and/or 1,4-bis-(5-phenyl-2-oxazolyl)-benzol. After a developing and silylating step, the cross-linked structure is inert with respect to solvents of additional resists that are applied over the structure. The scintillating structure is thus not dissolved, which improves the quality of online controlled electron or ion beam writing.Type: GrantFiled: January 13, 2003Date of Patent: January 9, 2007Assignee: Infineon Technologies AGInventor: Klaus Elian
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Patent number: 7160655Abstract: To provide an exposure method and an exposure apparatus, using a complementary divided mask, designed to enable alignment of a complementary divided mask at a high precision over the entire region of a semiconductor wafer. Further, to provide a semiconductor device fabricated by the exposure method and a method of producing a semiconductor device using the exposure method.Type: GrantFiled: May 16, 2005Date of Patent: January 9, 2007Assignee: Sony CorporationInventors: Shinichiro Noudo, Kumiko Oguni, Hiroyuki Nakano, Hiroki Hane
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Patent number: 7160657Abstract: An apparatus and method for manufacturing and using a calibrated registration reference wafer in a semiconductor manufacturing facility. A reference reticle consisting of a 2-dimensional array of standard alignment attributes is exposed several times onto a photoresist coated semiconductor wafer using a photolithographic exposure tool. After the final steps of the lithographic development process the resist patterned wafer is physically etched using standard techniques to create a permanent record of the alignment attribute exposure pattern. The permanently recorded alignment attributes are measured for placement error using a conventional overlay metrology tool. The resulting overlay error data is used to generate a calibration file that contains the positions of the alignment attributes on the reference wafer. The reference wafer and calibration file can be used to determine the wafer stage registration performance for any photolithographic exposure tool.Type: GrantFiled: January 26, 2004Date of Patent: January 9, 2007Assignee: Litel InstrumentsInventors: Adlai Smith, Bruce McArthur, Robert Hunter, Jr.
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Patent number: 7154105Abstract: Provided is a method of exposing using an electron beam. The provided method of exposing using the electron beam includes defining main fields on an exposure area of an electron beam exposure target and defining a plurality of sub-fields on the main fields, selecting a main field to be exposed, selecting at least one sub-field of the selected main field, exposing the selected sub-field by using the electron beam, and selecting at least one of the other sub-field, which is not adjacent to the previously selected sub-field and not exposed yet, and exposing the sub-field by using the electron beam.Type: GrantFiled: February 25, 2005Date of Patent: December 26, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Hae-sung Kim, Myung-bok Lee, Jin-seung Sohn, Mee-suk Jung, Eun-hyoung Cho
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Patent number: 7144680Abstract: An electron beam (EB) lithography method using a new material is provided. The method includes forming a thin layer using a Pb-based material; and patterning the thin layer by partially volatilizing the thin layer by irradiating electron beams. In this method, the thin layer formed of the Pb-based material is patterned using e-beams so that the linewidth of patterns formed on the thin layer can be greatly reduced.Type: GrantFiled: September 8, 2005Date of Patent: December 5, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-bong Park, Chel-jong Choi
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Patent number: 7141356Abstract: Deflecting means, for deflecting an electron beam in a radial direction and the circumferential direction, and blanking means, for shielding irradiation of the electron beam at portions other than drawing portions, are provided. While the disk is rotated unidirectionally, the electron beam is repeatedly deflected in a figure 8 pattern, in which the electron beam is deflected toward the next deflection initiation point in the radial direction at track edge portions, such that the deflected directions toward the inner periphery of the disk and toward the outer periphery of the disk intersect each other. Parallel scanning is performed alternately toward the outer periphery and the inner periphery of the disk. Elements of a transfer pattern, having lengths which are integer multiples of a reference value, are drawn by performing scanning a number of times equal to the integer that the reference value is multiplied by.Type: GrantFiled: June 30, 2005Date of Patent: November 28, 2006Assignee: Fuji Photo Film Co., Ltd.Inventors: Toshihiro Usa, Kazunori Komatsu