Having Metal Oxide Or Copper Sulfide Compound Semiconductor Component Patents (Class 438/104)
  • Publication number: 20150041802
    Abstract: To provide a transistor in which a channel is formed in an oxide semiconductor and which has stable electrical characteristics. To suppress shift in threshold voltage of a transistor in which a channel is formed in an oxide semiconductor. To provide a normally-off switching element having a positive threshold voltage as an n-channel transistor in which a channel is formed in an oxide semiconductor. A base insulating layer is formed over a substrate, an oxide semiconductor layer is formed over the base insulating layer, a first gate insulating layer is formed over the oxide semiconductor layer, a second gate insulating layer is formed over the first gate insulating layer by a sputtering method or an atomic layer deposition method at a substrate temperature of higher than or equal to 100° C., and a gate electrode layer is formed over the second gate insulating layer.
    Type: Application
    Filed: July 31, 2014
    Publication date: February 12, 2015
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20150041748
    Abstract: A variable resistance layer between a first electrode and a second electrode includes: a first variable resistance layer contacting the first electrode; and a second variable resistance layer contacting the second electrode and having a lower degree of oxygen deficiency than the first variable resistance layer. A principal face of the first variable resistance layer which is close to the second variable resistance layer is flat. The second variable resistance layer is in contact with both the first variable resistance layer and the second electrode in a polygonal region including a vertex inward of an outline of the variable resistance layer and vertices along the outline when seen from a direction perpendicular to the principal face of the variable resistance layer, and is not in contact with at least one of the first variable resistance layer and the second electrode in a region outside the region inside the polygon.
    Type: Application
    Filed: October 4, 2013
    Publication date: February 12, 2015
    Inventors: Yukio Hayakawa, Takumi Mikawa
  • Publication number: 20150044818
    Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.
    Type: Application
    Filed: October 23, 2014
    Publication date: February 12, 2015
    Inventors: Masashi TSUBUKU, Shuhei YOSHITOMI, Takahiro TSUJI, Miyuki HOSOBA, Junichiro SAKATA, Hiroyuki TOMATSU, Masahiko HAYAKAWA
  • Publication number: 20150041803
    Abstract: A transistor that is formed using an oxide semiconductor film is provided. A transistor that is formed using an oxide semiconductor film with reduced oxygen vacancies is provided. A transistor having excellent electrical characteristics is provided. A semiconductor device includes a first insulating film, a first oxide semiconductor film, a gate insulating film, and a gate electrode. The first insulating film includes a first region and a second region. The first region is a region that transmits less oxygen than the second region does. The first oxide semiconductor film is provided at least over the second region.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 12, 2015
    Inventors: Yuta Endo, Kosei Noda, Yuichi Sato
  • Publication number: 20150044817
    Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.
    Type: Application
    Filed: October 22, 2014
    Publication date: February 12, 2015
    Inventors: Doo Hyoung Lee, Bo Sung Kim, Chan Wood Yang, Seung-Ho Jung, Yeon Taek Jeong, June Whan Choi, Tae-Young Choi
  • Publication number: 20150041800
    Abstract: This semiconductor device (100A) includes: a substrate (1); a gate electrode (3) and a first transparent electrode (2) which are formed on the substrate (1); a first insulating layer (4) formed over the gate electrode (3) and the first transparent electrode (2); an oxide semiconductor layer (5) formed on the first insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); and a second transparent electrode (7) electrically connected to the drain electrode (6d). At least a portion of the first transparent electrode (2) overlaps with the second transparent electrode (7) with the first insulating layer (4) interposed between them, and the oxide semiconductor layer (5) and the second transparent electrode (7) are formed out of the same oxide film.
    Type: Application
    Filed: January 24, 2013
    Publication date: February 12, 2015
    Inventors: Tadayoshi Miyamoto, Kazuatsu Ito, Shigeyasu Mori, Mitsunobu Miyamoto, Yasuyuki Ogawa, Makoto Nakazawa, Seiichi Uchida, Takuya Matsuo
  • Patent number: 8951897
    Abstract: A method for controlling the concentration of a donor in a Ga2O3-based single crystal includes: a step in which a Group IV element is implanted as a donor impurity in a Ga2O3-based single crystal by ion implantation process to form, in the Ga2O3-based single crystal, a donor impurity implantation region that has a higher concentration of the Group IV element than the region in which the Group IV element has not been implanted; and a step in which annealing at 800 C or higher is conducted to activate the Group IV element present in the donor impurity implantation region and thereby form a high-donor-concentration region. Thus, the donor concentration in the Ga2O3-based single crystal is controlled.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: February 10, 2015
    Assignee: Tamura Corporation
    Inventor: Kohei Sasaki
  • Patent number: 8952381
    Abstract: High field-effect mobility is provided for a semiconductor device including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a transistor in which a stack of oxide semiconductor layers is provided over a gate electrode layer with a gate insulating layer provided therebetween, an oxide semiconductor layer functioning as a current path (channel) of the transistor and containing an n-type impurity is sandwiched between oxide semiconductor layers having lower conductivity than the oxide semiconductor layer. In the oxide semiconductor layer functioning as the channel, a region on the gate insulating layer side contains the n-type impurity at a higher concentration than a region on the back channel side. With such a structure, the channel can be separated from the interface between the oxide semiconductor stack and the insulating layer in contact with the oxide semiconductor stack, so that a buried channel can be formed.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20150034942
    Abstract: According to example embodiments, a thin film transistor (TFT) includes a channel layer including zinc, nitrogen, and oxygen; an etch stop layer on the channel layer; source and drain electrodes respectively contacting both ends of the channel layer; a gate electrode corresponding to the channel layer; and a gate insulating layer between the channel layer and the gate electrode. The etch stop layer includes fluorine. The channel layer may be on the gate electrode.
    Type: Application
    Filed: January 24, 2014
    Publication date: February 5, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-suk KIM, Sun-jae KIM, Tae-sang KIM, Myung-kwan RYU, Joon-seok PARK, Kyoung-seok SON
  • Publication number: 20150037931
    Abstract: A method of manufacturing a semiconductor device includes forming a stack of films including a conductive film layer above a semiconductor substrate; patterning the stack of films by dry etching; and cleaning including generation of plasma in an ambient including BCl3 and controlling a bias power to a nonbiased state.
    Type: Application
    Filed: February 14, 2014
    Publication date: February 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takuji KUNIYA
  • Publication number: 20150034949
    Abstract: Provided is a semiconductor device having a structure which can prevent deterioration of the electrical characteristics, which becomes more significant with miniaturization. The semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film over the second oxide semiconductor film; a source electrode and a drain electrode each in contact with side surfaces of the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film and a top surface of the third oxide semiconductor film; a gate insulating film over the third oxide semiconductor film, the source electrode, and the drain electrode; and a gate electrode which is on and in contact with the gate insulating film and faces a top surface and a side surface of the second oxide semiconductor film.
    Type: Application
    Filed: August 4, 2014
    Publication date: February 5, 2015
    Inventor: Shunpei Yamazaki
  • Publication number: 20150037932
    Abstract: A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.
    Type: Application
    Filed: August 14, 2014
    Publication date: February 5, 2015
    Inventors: Shunpei YAMAZAKI, Atsuo ISOBE, Toshihiko SAITO, Takehisa HATANO, Hideomi SUZAWA, Shinya SASAGAWA, Junichi KOEZUKA, Yuichi SATO, Shinji OHNO
  • Publication number: 20150037930
    Abstract: A method of manufacturing a semiconductor structure includes the steps of depositing a layer of semiconductor oxide on a base semiconductor layer, scavenging oxygen from the layer of semiconductor oxide and recrystallizing the oxygen scavenged layer of semiconductor oxide as a semiconductor heteroepitaxy layer.
    Type: Application
    Filed: August 2, 2013
    Publication date: February 5, 2015
    Applicant: The University of Kentucky Research Foundation
    Inventor: Zhi David Chen
  • Publication number: 20150037935
    Abstract: An array substrate for a liquid crystal display includes a substrate and first and second subpixels which are positioned on the substrate and are defined by a crossing structure of one gate line, a first data line, a second data line, a first common line, and a second common line. The first subpixel includes a first semiconductor layer, a first source electrode, a first drain electrode, and a first pixel electrode connected to the first drain electrode. The second subpixel includes a second semiconductor layer, a second source electrode, a second drain electrode, and a second pixel electrode connected to the second drain electrode. The first and second subpixels share the one gate line with each other, and the first drain electrode and the second drain electrode are exposed through one contact hole.
    Type: Application
    Filed: October 22, 2014
    Publication date: February 5, 2015
    Inventors: Kangil Kim, Sungyong Jang, Cheolhwan Lee
  • Publication number: 20150037933
    Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor whose electric characteristics are stable. In addition, it is another object to manufacture a highly reliable semiconductor device at low cost with high productivity. In a semiconductor device including a thin film transistor, a semiconductor layer of the thin film transistor is formed with an oxide semiconductor layer to which a metal element is added. As the metal element, at least one of metal elements of iron, nickel, cobalt, copper, gold, manganese, molybdenum, tungsten, niobium, and tantalum is used. In addition, the oxide semiconductor layer contains indium, gallium, and zinc.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 5, 2015
    Inventors: Shunpei YAMAZAKI, Junichiro SAKATA
  • Publication number: 20150037934
    Abstract: The semiconductor device includes a gate electrode over a substrate, a gate insulating layer over the gate electrode, an oxide semiconductor layer over the gate insulating layer, and a source electrode and a drain electrode over the oxide semiconductor layer. A length of part of an outer edge of the oxide semiconductor layer from an outer edge of the source electrode to an outer edge of the drain electrode is more than three times, preferably more than five times as long as a channel length of the semiconductor device. Further, oxygen is supplied from the gate insulating layer to the oxide semiconductor layer by heat treatment. In addition, an insulating layer is formed after the oxide semiconductor layer is selectively etched.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 5, 2015
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20150034941
    Abstract: Integrated circuits that have a FinFET and methods of fabricating the integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit having a FinFET includes providing a substrate comprising fins. The fins include semiconductor material. A first metal oxide layer is formed over sidewall surfaces of the fins. The first metal oxide layer includes a first metal oxide. The first metal oxide layer is recessed to a depth below a top surface of the fins to form a recessed first metal oxide layer. The top surface and sidewall surfaces of the fins at a top portion of the fins are free from the first metal oxide layer. A gate electrode structure is formed over the top surface and sidewall surfaces of the fins at the top portion of the fins. The recessed first metal oxide layer is recessed beneath the gate electrode structure.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 5, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Michael HARGROVE, Yanxiang LIU, Christian GRUENSFELDER
  • Patent number: 8945982
    Abstract: Disclosed is a semiconductor device using an oxide semiconductor, with stable electric characteristics and high reliability. In a process for manufacturing a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation is performed by heat treatment and oxygen doping treatment is performed. The transistor including a gate insulating film subjected to the oxygen doping treatment and the oxide semiconductor film subjected to the dehydration or dehydrogenation by the heat treatment is a transistor having high reliability in which the amount of change in threshold voltage of the transistor by the bias-temperature stress (BT) test can be reduced.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8946669
    Abstract: A method for forming a resistive memory device includes providing a substrate comprising a first metal material, forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein the lower region is adjacent to the first metal material, forming an amorphous layer from the upper region of the conductive silicon-bearing layer, and disposing an active metal material above the amorphous layer.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: February 3, 2015
    Assignee: Crossbar, Inc.
    Inventors: Sung Hyun Jo, Kuk-Hwan Kim, Tanmay Kumar
  • Patent number: 8945981
    Abstract: To provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability and a manufacturing method of the semiconductor device with high mass productivity. The summary is that an inverted-staggered (bottom-gate) thin film transistor is included in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, a channel protective layer is provided in a region that overlaps a channel formation region of the semiconductor layer, and a buffer layer is provided between the semiconductor layer and source and drain electrodes. An ohmic contact is formed by intentionally providing the buffer layer having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrodes.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Publication number: 20150028331
    Abstract: Provided are a thin-film transistor (TFT), a method of manufacturing the same, and a method of manufacturing a backplane for a flat panel display (FPD). The method of manufacturing the TFT according to an embodiment of the present invention includes forming a gate electrode on a substrate; forming an insulating layer on the substrate to cover the gate electrode; performing a plasma treatment on an upper surface of the insulating layer using a halogen gas; forming an oxide semiconductor layer on the insulating layer and positioned to correspond to the gate electrode; and forming source and drain electrodes on the insulating layer to contact and over portions of the oxide semiconductor layer.
    Type: Application
    Filed: July 23, 2014
    Publication date: January 29, 2015
    Inventors: Young-Gug Seol, Tae-Woong KIM, Jin Jang, Christophe Avis
  • Publication number: 20150028332
    Abstract: This semiconductor device (100) includes a substrate (1), a gate electrode (11), a gate insulating film (12), an oxide semiconductor layer (13), a source electrode (14), a drain electrode (15), and a protective film (16). The upper and side surfaces of the oxide semiconductor layer are covered with the source and drain electrodes and the protective film. When viewed along a normal to the substrate, the narrowest gap between the respective outer peripheries of a first contact region (13s) and the source electrode and the narrowest gap between the respective outer peripheries of a second contact region (13d) and the drain electrode both have a length of 1.5 ?m to 4.5 ?m.
    Type: Application
    Filed: December 28, 2012
    Publication date: January 29, 2015
    Inventor: Akihiro Oda
  • Publication number: 20150028327
    Abstract: A thin film transistor includes a substrate, a gate electrode, a buffer layer, a gate insulating layer, an active layer, an etching stop layer, a source electrode and a drain electrode. The gate electrode is formed on the substrate. The buffer layer partially covers both side portions of the gate electrode. The gate insulating layer covers the gate electrode and the buffer layer. The active layer is formed on the gate insulating layer. The etching stop layer is formed on the active layer, and has a first opening and a second opening on the active layer. The source electrode is formed on the etching stop layer, and contacts with the active layer through the first opening. The drain electrode is formed on the etching stop layer, and is contacted with the active layer through the second opening.
    Type: Application
    Filed: July 14, 2014
    Publication date: January 29, 2015
    Inventors: Jung-Bae KIM, Bo-Yong CHUNG, Hae-Yeon LEE, Yong-Jae KIM
  • Publication number: 20150031169
    Abstract: An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (for dehydration or dehydrogenation) is performed to improve the purity of the oxide semiconductor film and reduce impurities including moisture or the like. After that, slow cooling is performed under an oxygen atmosphere. Besides impurities including moisture or the like exiting in the oxide semiconductor film, heat treatment causes reduction of impurities including moisture or the like exiting in a gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor and in contact therewith.
    Type: Application
    Filed: September 23, 2014
    Publication date: January 29, 2015
    Inventors: Toshinari SASAKI, Junichiro SAKATA, Hiroki OHARA, Shunpei YAMAZAKI
  • Publication number: 20150031168
    Abstract: A display panel manufacturing method includes forming a gate electrode on a substrate and a gate insulator, a semiconductor layer, and an etch stop layer covering the gate electrode. A photoresist layer covering on the etch stop layer is pattern from two opposite side of the substrate by two photolithography processes to form a photoresist pattern. The etch stop layer is dry etched to form an etch stop pattern via the photoresist pattern. The photoresist pattern is formed again by two photolithography processes. The semiconductor layer is wet etched to form a semiconductor pattern via the photoresist pattern. A source electrode and a drain electrode is formed corresponding to two opposite sides of the gate electrode to orderly cover the etch pattern, the semiconductor pattern, and the gate insulator.
    Type: Application
    Filed: July 25, 2014
    Publication date: January 29, 2015
    Inventor: PO-LI SHIH
  • Publication number: 20150028364
    Abstract: A pixel structure includes an active switching device, a patterned common electrode layer, an insulation layer, a patterned oxide electrode layer and a patterned passivation layer. The insulation layer covers the patterned common electrode layer. The patterned oxide electrode layer is disposed on the insulation layer and electrically connected to the active switching device. The patterned oxide electrode layer includes a semiconductor part and a conductive part. The semiconductor part and the patterned common electrode layer substantially overlap to each other in a vertical projection direction. The conductive part and the semiconductor part are connected to each other, the conductive part and the patterned common electrode layer do not overlap to each other in the vertical projective direction, and the conductive part is a pixel electrode. The patterned passivation layer covers the semiconductor part, and the patterned passivation layer has an opening exposing the conductive part.
    Type: Application
    Filed: February 12, 2014
    Publication date: January 29, 2015
    Applicant: AU Optronics Corp.
    Inventor: Seok-Lyul Lee
  • Publication number: 20150028330
    Abstract: Provided is a semiconductor device in which a deterioration in electrical characteristics which becomes more noticeable as miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with each side surface of the first oxide semiconductor film and the second oxide semiconductor film; a first insulating film and a second insulating film over the source electrode and the drain electrode; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with an upper surface of the gate insulating film and facing an upper surface and the side surface of the second oxide semiconductor film.
    Type: Application
    Filed: July 22, 2014
    Publication date: January 29, 2015
    Inventors: Shunpei Yamazaki, Shinya Sasagawa, Suguru Hondo, Hideomi Suzawa
  • Publication number: 20150028326
    Abstract: A thin film transistor includes a gate electrode, a channel layer, a source electrode, and a drain electrode. The channel layer is made of an amorphous oxide semiconductor. The channel layer includes one high oxygen ion concentration region, or two high oxygen ion concentration regions one above the other. An oxygen ion density of each high oxygen ion concentration region is in a range of from about 1×1018 to about 1×1021 per cubic centimeter. A thin film transistor substrate and a method of manufacturing the thin film transistor substrate are also provided.
    Type: Application
    Filed: December 31, 2013
    Publication date: January 29, 2015
    Applicant: Ye Xin Technology Consulting Co., Ltd.
    Inventor: ANJO KENJI
  • Publication number: 20150028300
    Abstract: A thin film transistor includes a gate electrode provided on a substrate, a semiconductor layer insulated from the gate electrode and including indium, tin, zinc and gallium oxide, and source/drain electrodes formed on the semiconductor layer.
    Type: Application
    Filed: April 17, 2014
    Publication date: January 29, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventors: Kwang-Suk KIM, Jong-Han Jeong, Yeon-Gon Mo
  • Patent number: 8941107
    Abstract: With a non-linear element (e.g., a diode) with small reverse saturation current, a power diode or rectifier is provided. A non-linear element includes a first electrode provided over a substrate, an oxide semiconductor film provided on and in contact with the first electrode and having a concentration of hydrogen of 5×1019 atoms/cm3 or less, a second electrode provided on and in contact with the oxide semiconductor film, a gate insulating film covering the first electrode, the oxide semiconductor film, and the second electrode, and third electrodes provided in contact with the gate insulating film and facing each other with the first electrode, the oxide semiconductor film, and the second electrode interposed therebetween or a third electrode provided in contact with the gate insulating film and surrounding the second electrode. The third electrodes are connected to the first electrode or the second electrode. With the non-linear element, a power diode or a rectifier is formed.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: January 27, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8940579
    Abstract: Disclosed are new methods of fabricating metal oxide thin films and nanomaterial-derived metal composite thin films via solution processes at low temperatures (<400° C.). The present thin films are useful as thin film semiconductors, thin film dielectrics, or thin film conductors, and can be implemented into semiconductor devices such as thin film transistors and thin film photovoltaic devices.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 27, 2015
    Assignees: Northwestern University, Polyera Corporation
    Inventors: Antonio Facchetti, Tobin J. Marks, Mercouri G. Kanatzidis, Myung-Gil Kim, William Christopher Sheets, He Yan, Yu Xia
  • Patent number: 8940578
    Abstract: Disclosed are new methods of fabricating metal oxide thin films and nanomaterial-derived metal composite thin films via solution processes at low temperatures (<400° C.). The present thin films are useful as thin film semiconductors, thin film dielectrics, or thin film conductors, and can be implemented into semiconductor devices such as thin film transistors and thin film photovoltaic devices.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 27, 2015
    Assignees: Northwestern University, Polyera Corporation
    Inventors: Antonio Facchetti, Tobin J. Marks, Mercouri G. Kanatzidis, Myung-Gil Kim, William Christopher Sheets, He Yan, Yu Xia
  • Publication number: 20150021599
    Abstract: Described herein are apparatus comprising one or more silicon-containing layers and a metal oxide layer. Also described herein are methods for forming one or more silicon-containing layers to be used, for example, as passivation layers in a display device. In one particular aspect, the apparatus comprises a transparent metal oxide layer, a silicon oxide layer and a silicon nitride layer. In this or other aspects, the apparatus is deposited at a temperature of 350° C. or below. The silicon-containing layers described herein comprise one or more of the following properties: a density of about 1.9 g/cm3 or greater; a hydrogen content of about 4×1022 cm?3 or less, and a transparency of about 90% or greater at 400-700 nm as measured by a UV-visible light spectrometer.
    Type: Application
    Filed: March 8, 2013
    Publication date: January 22, 2015
    Applicant: AIR PRODUCTS AND CHEMICALS, INC.
    Inventors: Robert Gordon Ridgeway, Andrew David Johnson, Anupama Mallikarjunan, Raymond Nicholas Vrtis, Xinjian Lei, Mark Leonard O'Neill, Manchao Xiao, Jianheng Li, Michael T. Savo
  • Publication number: 20150024530
    Abstract: Disclosed is a method of manufacturing an oxide semiconductor device, including: forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming an active pattern on the gate insulating layer; forming a first mask pattern on the gate insulating layer and the active pattern; forming an insulating interlayer on the gate insulating layer, the active pattern, and the first mask pattern; forming a second mask pattern on the insulating interlayer, the second mask pattern comprising an opening that exposes a region where the first mask pattern is formed; forming contact holes exposing portions of the active pattern by patterning the insulating interlayer using the first mask pattern and the second mask pattern; and forming a source electrode and a drain electrode on the gate insulating layer by filling the contact holes, the drain electrode spaced apart from the source electrode.
    Type: Application
    Filed: December 26, 2013
    Publication date: January 22, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventor: Bong-Won LEE
  • Publication number: 20150021597
    Abstract: The present polymeric materials can be patterned with relatively low photo-exposure energies and are thermally stable, mechanically robust, resist water penetration, and show good adhesion to metal oxides, metals, metal alloys, as well as organic materials. In addition, these polymeric materials can be solution-processed (e.g., by spin-coating), and can exhibit good chemical (e.g., solvent and etchant) resistance in the cured form.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 22, 2015
    Inventors: Shaofeng Lu, Daniel Batzel, Chun Huang, Ming Huei Wang, Meko McCray, Yu Xia, Antonio Facchetti
  • Publication number: 20150024544
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor film, which has stable electric characteristics and high reliability. A crystalline oxide semiconductor film is formed, without performing a plurality of steps, as follows: by utilizing a difference in atomic weight of plural kinds of atoms included in an oxide semiconductor target, zinc with low atomic weight is preferentially deposited on an oxide insulating film to form a seed crystal including zinc; and tin, indium, or the like with high atomic weight is deposited on the seed crystal while causing crystal growth. Further, a crystalline oxide semiconductor film is formed by causing crystal growth using a seed crystal with a hexagonal crystal structure including zinc as a nucleus, whereby a single crystal oxide semiconductor film or a substantially single crystal oxide semiconductor film is formed.
    Type: Application
    Filed: October 7, 2014
    Publication date: January 22, 2015
    Inventors: Shunpei YAMAZAKI, Yusuke NONAKA, Takayuki INOUE, Masashi TSUBUKU, Kengo AKIMOTO, Akiharu MIYANAGA
  • Publication number: 20150021593
    Abstract: A crystalline oxide semiconductor film and a semiconductor device including the oxide semiconductor film are provided. One embodiment of the present invention is an oxide semiconductor film including a plurality of flat-plate particles each having a structure in which layers including a gallium atom, a zinc atom, and an oxygen atom are provided over and under a layer including an indium atom and an oxygen atom. In the semiconductor film, the plurality of flat-plate particles face in random directions, and a crystal boundary is not observed using a transmission electron microscope.
    Type: Application
    Filed: May 15, 2014
    Publication date: January 22, 2015
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20150021592
    Abstract: A method of manufacturing a display substrate includes forming a gate electrode on a base substrate, forming an active pattern which includes an oxide semiconductor and overlaps with the gate electrode, forming an etch stopper which partially covers the active pattern, and performing a plasma treatment process to promote a reduction reaction to portions of the active pattern exposed by the etch stopper, thereby forming a source electrode and a drain electrode.
    Type: Application
    Filed: April 10, 2014
    Publication date: January 22, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventors: Ki-Seong SEO, Sung-Hoon YANG, Tae-Young AHN, Sang-Wook LEE, Jung-Yun JO, Heon-Sik HA, Jin-Ho HWANG, Kyung-Tea PARK, Jun-Mo IM
  • Patent number: 8936973
    Abstract: A method of forming a gate dielectric in each MOTFT of an active matrix includes depositing a layer of gate metal on a substrate and patterning the gate metal to define a matrix of MOTFTs each including a gate electrode with all gate electrodes in each column connected together by a gate metal line and the line in each column connected at one end to the line in the next adjacent column by a gate metal bridging portion. The gate metal is anodized to form a layer of gate dielectric material. A layer of semiconductor metal oxide is deposited over the anodized gate metal and patterned to define an active layer for each MOTFT. Source/drain electrodes are formed on the layer of metal oxide for each MOTFT, and a laser is used to cut the bridging portion electrically connecting each gate metal line to the next adjacent gate metal line.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: January 20, 2015
    Assignee: Cbrite Inc.
    Inventors: Gang Yu, Chan-Long Shieh, Kaixia Yang
  • Patent number: 8937305
    Abstract: To provide a highly reliable semiconductor device which includes a transistor including an oxide semiconductor, in a semiconductor device including a staggered transistor having a bottom-gate structure provided over a glass substrate, a gate insulating film in which a first gate insulating film and a second gate insulating film, whose compositions are different from each other, are stacked in this order is provided over a gate electrode layer. Alternatively, in a staggered transistor having a bottom-gate structure, a protective insulating film is provided between a glass substrate and a gate electrode layer. A metal element contained in the glass substrate has a concentration lower than or equal to 5×1018 atoms/cm3 at the interface between the first gate insulating film and the second gate insulating film or the interface between the gate electrode layer and a gate insulating film.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: January 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Cho, Shunsuke Koshioka, Masatoshi Yokoyama, Shunpei Yamazaki
  • Patent number: 8937308
    Abstract: An oxide semiconductor thin film transistor includes a substrate, a gate electrode, an oxide semiconductor layer, a gate insulation layer, an oxide source electrode, an oxide drain electrode and a metal connection component. The gate insulation layer is at least partially disposed between the gate electrode and the oxide semiconductor layer. The oxide source electrode and the oxide drain electrode are respectively disposed at least partially between the oxide semiconductor layer and the substrate. The metal connection component is disposed on the substrate, and the metal connection component overlaps the oxide source electrode in a vertical projective direction perpendicular to the substrate. The metal connection component does not overlap the oxide semiconductor layer in the vertical projective direction.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: January 20, 2015
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Chin-Hai Huang, Bo-Jhang Sun, Szu-Chi Huang
  • Publication number: 20150014677
    Abstract: A thin film transistor substrate includes an active pattern which is disposed on a base substrate and includes a channel, a source electrode and a drain electrode, the channel which includes an oxide semiconductor, the source electrode and the drain electrode connected the channel, a gate electrode overlapped with the channel, a passivation layer which covers the source electrode, the drain electrode and the gate electrode and a fluorine deposition layer disposed between the active pattern and the passivation layer.
    Type: Application
    Filed: November 15, 2013
    Publication date: January 15, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventors: Jung-Yun JO, Sung-Hoon YANG, Ki-Seong SEO, Jin-Ho HWANG
  • Publication number: 20150017761
    Abstract: A method for fabricating a thin-film transistor is described. A structure is provided, including a substrate transmitting an excimer laser light, a diffusion prevention film on the substrate, a gate electrode and a gate insulating film on the diffusion prevention film, and an oxide semiconductor layer on the gate insulating film. The structure is irradiated with an excimer laser light from the side of the substrate, so that two outer regions of the oxide semiconductor layer beside the region corresponding to the gate electrode are irradiated by the excimer laser light, with the gate electrode as a mask, to be reduced in resistance and thereby one of the two outer regions forms a source region and the other one forms a drain region. The diffusion prevention film includes a SiN:F film containing fluorine in a SiN film.
    Type: Application
    Filed: July 3, 2014
    Publication date: January 15, 2015
    Inventor: YASUNORI ANDO
  • Publication number: 20150017762
    Abstract: An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured.
    Type: Application
    Filed: September 30, 2014
    Publication date: January 15, 2015
    Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Masashi TSUBUKU, Kengo AKIMOTO, Miyuki HOSOBA, Masayuki SAKAKURA, Yoshiaki OIKAWA
  • Publication number: 20150014678
    Abstract: A method of manufacturing a semiconductor device, the method includes: providing a gate electrode on a substrate; providing a first interlayer insulating layer to cover the gate electrode on the substrate; providing an oxide semiconductor layer corresponding to the gate electrode on the first interlayer insulating layer; providing a source electrode and a drain electrode, which are in contact with the oxide semiconductor layer, on the first interlayer insulating layer; and heat-treating the oxide semiconductor layer using Joule heat generated therein from a flow of a drain current by applying a voltage to the source electrode or the drain electrode.
    Type: Application
    Filed: December 16, 2013
    Publication date: January 15, 2015
    Applicants: Industry-Academic Cooperation Foundation, Yonsei University, Samsung Display Co., Ltd.
    Inventors: Ji-Won Han, Tae-Woong Kim, Seong-Il Im, Young-Tack Lee, Pyo-Jin Jeon
  • Patent number: 8932902
    Abstract: The present disclosure relates to a thin film transistor substrate with a metal oxide semiconductor layer that has enhanced characteristics and stability. The present disclosure also relates to a method for manufacturing a thin film transistor substrate in which a thermal treatment is conducted for the metal oxide semiconductor layer and the damages to the substrate by the thermal treatment are minimized.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: January 13, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: Kisul Cho, Seongmoh Seo
  • Patent number: 8933429
    Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: January 13, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Venkat Ananthan, Prashant B Phatak
  • Patent number: 8932903
    Abstract: A wiring which is formed using a conductive film containing copper and whose shape is controlled is provided. A transistor including an electrode which is formed in the same layer as the wiring is provided. Further, a semiconductor device including the transistor and the wiring is provided. A resist mask is formed over a second conductive film stacked over a first conductive film; part of the second conductive film and part of the first conductive film are removed with use of the resist mask as a mask so that the first conductive film has a taper angle greater than or equal to 15° and less than or equal to 45°; and the resist mask is removed. The first conductive film contains copper.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: January 13, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiro Sato, Takayuki Cho, Shunsuke Koshioka, Tetsuya Ohshima, Naoya Sakamoto
  • Publication number: 20150011044
    Abstract: Provided is a composition for forming tin oxide semiconductor including a tin precursor compound, an antimony precursor compound, and a solvent, according to an aspect of the present disclosure. Also provided is a method of forming a tin oxide semiconductor thin film. The method includes preparing a composition including a tin precursor compound and an antimony precursor compound dissolved in a solvent; disposing the composition on a substrate; and performing a heat treatment on the substrate coated with the composition.
    Type: Application
    Filed: December 5, 2013
    Publication date: January 8, 2015
    Applicants: Industry-Academic Cooperation Foundation, Yonsei University, Samsung Display Co., Ltd.
    Inventors: Chaun-Gi CHOI, Yeon-Gon MO, Hyun-Jae KIM, Hyun-Soo LIM, Si-Joon KIM, Tae-Soo JUNG, You-Seung RIM
  • Publication number: 20150008429
    Abstract: The present invention includes at least a step forming a source electrode (32) and a drain electrode (33), each of which is a multilayer film of a first conductive film (32a), (33a) made of titanium or molybdenum, a second conductive film (32b), (33b) made of copper, and a third conductive film (32c), (33c) made of titanium oxide, a step of forming passivation film (18), which is an inorganic insulating film, on an oxide semiconductor layer (13), the source electrode (32) and drain electrode (33), and an annealing step of annealing the oxide semiconductor layer (13).
    Type: Application
    Filed: January 16, 2013
    Publication date: January 8, 2015
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Kazuatsu Ito, Hidehito Kitakado