Having Metal Oxide Or Copper Sulfide Compound Semiconductor Component Patents (Class 438/104)
  • Publication number: 20150069377
    Abstract: Disclosed herein are 3D stacked memory devices having WL select gates that comprises TFTs having bodies formed from a wide band gap semiconductor. The wide energy band gap semiconductor may be an oxide semiconductor, such as a metal oxide semiconductor. As examples, this could be an InGaZnO, InZnO, HfInZnO, or ZnInSnO body. The word lines may be formed from metal, such as tungsten. The 3D stacked memory device could have NAND strings. The TFTs may be formed in the word line layer. The TFT has a high drive current, a high breakdown voltage and low leakage current.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 12, 2015
    Applicant: SanDisk Technologies Inc.
    Inventors: Peter Rabkin, Masaaki Higashitani
  • Publication number: 20150072472
    Abstract: An embodiment of the disclosed invention is a method for manufacturing a semiconductor device, which includes the steps of: forming a first insulating film; performing oxygen doping treatment on the first insulating film to supply oxygen to the first insulating film; forming a source electrode, a drain electrode, and an oxide semiconductor film electrically connected to the source electrode and the drain electrode, over the first insulating film; performing heat treatment on the oxide semiconductor film to remove a hydrogen atom in the oxide semiconductor film; forming a second insulating film over the oxide semiconductor film; and forming a gate electrode in a region overlapping with the oxide semiconductor film, over the second insulating film. The manufacturing method allows the formation of a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability.
    Type: Application
    Filed: November 17, 2014
    Publication date: March 12, 2015
    Inventor: Shunpei Yamazaki
  • Patent number: 8975174
    Abstract: A gate stack for a transistor is formed by a process including forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Kisik Choi, Matthew W. Copel, Richard A. Haight
  • Patent number: 8975115
    Abstract: An insulating layer which releases a large amount of oxygen is used as an insulating layer in contact with a channel region of an oxide semiconductor layer, and an insulating layer which releases a small amount of oxygen is used as an insulating layer in contact with a source region and a drain region of the oxide semiconductor layer. By releasing oxygen from the insulating layer which releases a large amount of oxygen, oxygen deficiency in the channel region and an interface state density between the insulating layer and the channel region can be reduced, so that a highly reliable semiconductor device having small variation in electrical characteristics can be manufactured. The source region and the drain region are provided in contact with the insulating layer which releases a small amount of oxygen, thereby suppressing the increase of the resistance of the source region and the drain region.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: March 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Kosei Noda, Toshinari Sasaki
  • Patent number: 8975610
    Abstract: Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on multilayer dielectric stacks. The control element can include a titanium oxide-silicon-titanium oxide multilayer stack. Electrode materials may include one of ruthenium, titanium nitride, or carbon. The control element can include a silicon nitride-silicon-silicon nitride multilayer stack. Electrode materials may include titanium nitride.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: March 10, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Monica Sawkar Mathur, Prashant B. Phatak
  • Patent number: 8975613
    Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode, the switching layer comprising a first metal oxide having a first bandgap greater than 4 electron volts (eV), the switching layer having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a second metal oxide having a second bandgap greater the first bandgap, the coupling layer having a second thickness that is less than 25 percent of the first thickness.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: March 10, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Ronald John Kuse, Tony Chiang, Michael Miller, Prashant Phatak, Jinhong Tong
  • Patent number: 8975114
    Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 10, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Dipankar Pramanik, Tony P. Chiang, Tim Minvielle, Takeshi Yamaguchi
  • Patent number: 8975147
    Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: March 10, 2015
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Xiangxin Rui, Hanhong Chen, Pragati Kumar, Sandra G. Malhotra
  • Publication number: 20150064842
    Abstract: An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes.
    Type: Application
    Filed: November 11, 2014
    Publication date: March 5, 2015
    Inventor: Joon-Young Yang
  • Publication number: 20150060846
    Abstract: A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P?45?0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Inventors: Yoshitaka YAMAMOTO, Tetsuhiro TANAKA, Takayuki INOUE, Hideomi SUZAWA
  • Publication number: 20150060843
    Abstract: A display substrate and a method for manufacturing a display substrate are disclosed. In the method, a gate electrode is formed on a base substrate. An active pattern is formed using an oxide semiconductor. The active pattern partially overlaps the gate electrode. A first insulation layer pattern and a second insulation layer pattern are sequentially formed on the active pattern. The first insulation layer pattern and the second insulation layer pattern overlap the gate electrode. A third insulation layer is formed to cover the active pattern, the first insulation layer pattern and the second insulation layer pattern. Either the first insulation layer pattern or the second insulation layer pattern includes aluminum oxide. Forming the first insulation layer pattern and the second insulation layer pattern includes performing a backside exposure process using the gate electrode as an exposure mask.
    Type: Application
    Filed: February 18, 2014
    Publication date: March 5, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventors: Jong-Chan LEE, Yoon-Ho Khang, Su-Hyoung Kang, Dong-Jo Kim, Ji-Seon Lee, Myoung-Geun Cha, Deuk-Myung Ji
  • Publication number: 20150060848
    Abstract: To provide a highly reliable semiconductor device using an oxide semiconductor. The semiconductor device includes a first electrode layer; a second electrode layer positioned over the first electrode layer and including a stacked-layer structure of a first conductive layer and a second conductive layer; and an oxide semiconductor film and an insulating film positioned between the first electrode layer and the second electrode layer in a thickness direction. The first conductive layer and the insulating film have a first opening portion in a region overlapping with the first electrode layer. The oxide semiconductor film has a second opening portion in a region overlapping with the first opening portion. The second conductive layer is in contact with the first electrode layer exposed in the first opening portion and the second opening portion.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 5, 2015
    Inventors: Shinya SASAGAWA, Motomu KURATA, Katsuaki TOCHIBAYASHI
  • Publication number: 20150060844
    Abstract: A semiconductor device that operates at high speed. A semiconductor device with favorable switching characteristics. A highly integrated semiconductor device. A miniaturized semiconductor device. The semiconductor device is formed by: forming a semiconductor film including an opening, on an insulating surface; forming a conductive film over the semiconductor film and in the opening, and removing the conductive film over the semiconductor film to form a conductive pillar in the opening; forming an island-shaped mask over the conductive pillar and the semiconductor film; etching the conductive pillar and the semiconductor film using the mask to form a first electrode and a first semiconductor; forming a gate insulating film on a top surface and a side surface of the first semiconductor; and forming a gate electrode that is in contact with a top surface of the gate insulating film and faces the top surface and the side surface of the first semiconductor.
    Type: Application
    Filed: August 19, 2014
    Publication date: March 5, 2015
    Inventors: Hidekazu Miyairi, Kazuya Hanaoka, Suguru Hondo, Shunpei Yamazaki
  • Publication number: 20150064841
    Abstract: The number of manufacturing steps is reduced to provide a semiconductor device with high productivity and low cost. A semiconductor device with low power consumption and high reliability is provided. A photolithography process for forming an island-shaped semiconductor layer is omitted, and a semiconductor device is manufactured through at least four photolithography processes: a step for forming a gate electrode (including a wiring or the like formed from the same layer), a step for forming a source electrode and a drain electrode (including a wiring or the like formed from the same layer), a step for forming a contact hole, and a step for forming a pixel electrode. In the step for forming the contact hole, a groove portion is formed, whereby formation of a parasitic transistor is prevented. The groove portion overlaps with the wiring with an insulating layer provided therebetween.
    Type: Application
    Filed: November 7, 2014
    Publication date: March 5, 2015
    Inventor: Jun KOYAMA
  • Publication number: 20150064839
    Abstract: A method of forming a tin oxide semiconductor thin film includes preparing a precursor solution including a tin oxide semiconductor, coating the precursor solution on a substrate; and performing a heat treatment on the substrate coated with the precursor solution. A tin compound having a different tin valence according to a semiconductor type of the tin oxide semiconductor may be used in the precursor solution.
    Type: Application
    Filed: July 17, 2014
    Publication date: March 5, 2015
    Inventors: Chaun-Gi CHOI, Yeon-Gon MO, Hyun-Jae KIM, Hyun-Soo LIM, Si-Joon KIM, Tae-Soo JUNG, You-Seung RIM
  • Publication number: 20150064840
    Abstract: A method for forming a single crystal oxide film with high productivity is provided. Further, a method for forming a single crystal oxide film at a lower temperature is provided. In addition, a method for forming a single crystal oxide film by a simpler method is provided. An oxide film having crystal parts is formed over a formation surface, and the oxide film is single crystallized by performing heat treatment. Further, an oxide film having crystal parts in which the c-axis are aligned in a direction parallel to a normal direction of the formation surface or a normal direction of a surface of the oxide film and having no crystal grain boundary between the crystal parts is used as the oxide film formed over the formation surface.
    Type: Application
    Filed: August 21, 2014
    Publication date: March 5, 2015
    Inventors: Akihisa SHIMOMURA, Masashi OOTA, Yoshinori YAMADA
  • Patent number: 8969201
    Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Ding-Kang Shih, Chin-Hsiang Lin, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 8969129
    Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and a resistive switching layer connected in series with this resistor. The resistor is configured to prevent over-programming of the cell by limiting electrical currents through the resistive switching layer. Unlike the resistive switching layer, which changes its resistance in order to store data, the embedded resistor maintains a substantially constant resistance during operation of the cell. The embedded resistor is formed from tantalum nitride and silicon nitride. The atomic ratio of tantalum and silicon may be specifically selected to yield resistors with desired densities and resistivities as well as ability to remain amorphous when subjected to various annealing conditions. The embedded resistor may also function as a diffusion barrier layer and prevent migration of components between one of the electrodes and the resistive switching layer.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: March 3, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Chien-Lan Hsueh, Randall J. Higuchi, Mihir Tendulkar
  • Patent number: 8969130
    Abstract: An amorphous region with low density is formed in an oxide insulating film containing zirconium. The amount of oxygen released from such an oxide insulating film containing zirconium by heating is large and a temperature at which oxygen is released is higher in the oxide insulating film than in a conventional oxide film (e.g., a silicon oxide film). When the insulating film is formed using a sputtering target containing zirconium in an oxygen atmosphere, the temperature of a surface on which the insulating film is formed may be controlled to be lower than a temperature at which a film to be formed starts to crystallize.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Erika Takahashi, Yuki Imoto, Yuhei Sato
  • Patent number: 8969131
    Abstract: A thin film transistor panel includes a substrate, a light blocking layer on the substrate, a first protective film on the light blocking layer, a first electrode and a second electrode on the first protective film, an oxide semiconductor layer on a portion of the first protective film exposed between the first electrode and the second electrode, an insulating layer, a third electrode overlapping with the oxide semiconductor layer and on the insulating layer, and a fourth electrode on the insulating layer. The light blocking layer includes first sidewalls, and the first protective film includes second sidewalls. The first and the second sidewalls are disposed along substantially the same line.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hye-Young Ryu, Jin-Won Lee, Woo-Geun Lee, Hee-Jun Byeon, Xun Zhu
  • Patent number: 8969144
    Abstract: Described is a method for manufacturing a semiconductor device. A mask is formed over an insulating film and the mask is reduced in size. An insulating film having a projection is formed using the mask reduced in size, and a transistor whose channel length is reduced is formed using the insulating film having a projection. Further, in manufacturing the transistor, a planarization process is performed on a surface of a gate insulating film which overlaps with a top surface of a fine projection. Thus, the transistor can operate at high speed and the reliability can be improved. In addition, the insulating film is processed into a shape having a projection, whereby a source electrode and a drain electrode can be formed in a self-aligned manner.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Akihiro Ishizuka
  • Publication number: 20150053969
    Abstract: This semiconductor device (100) includes: a gate electrode (3); a gate insulating layer (4); an oxide layer (50) which is formed on the gate insulating layer (4) and which includes a first conductor region (55) and a first semiconductor region (51) that overlaps at least partially with the gate electrode (3) with the gate insulating layer (4) interposed between them; a source electrode (6s) formed to contact with the upper surface of the first semiconductor region (51) of the oxide layer (50); a drain electrode (6d) which is formed to contact with the upper surface of the first semiconductor region (51) of the oxide layer (50) and which is electrically connected to the first conductor region (55); and a conductive layer (60) which is formed in contact with the upper surface of the oxide layer (50) and which a plurality of holes (66) or notches.
    Type: Application
    Filed: March 29, 2013
    Publication date: February 26, 2015
    Inventors: Kazuatsu Ito, Yutaka Takamaru, Tadayoshi MIiyamoto, Mitsunobu Miyamoto, Makoto Nakazawa, Yasuyuki Ogawa, Seiichi Uchida, Shigeyasu Mori
  • Publication number: 20150053968
    Abstract: This semiconductor device (1000A) includes a TFT (100A) with an oxide semiconductor layer 9, a storage capacitor line (12), and a first transparent electrode (15) electrically connected to the storage capacitor line (12). The first transparent electrode (15) includes a portion which overlaps with a first connecting layer (8x) when viewed along a normal to a substrate (1). The portion that overlaps with the first connecting layer (8x) has a point symmetric shape of which a point of symmetry is located inside a contact hole (CH2) when viewed along a normal to the substrate (1). The first transparent electrode (15) is not in direct contact with the first connecting layer (8x). A portion of the first transparent electrode (15) is in direct contact with a second connecting layer (8x). The first connecting layer (8x) is in direct contact with the second connecting layer (19a).
    Type: Application
    Filed: March 11, 2013
    Publication date: February 26, 2015
    Inventors: Katsunori Misaki, Kunio Matsubara
  • Publication number: 20150053966
    Abstract: The present invention relates to a method for producing a semi-conductor laminate comprising a first and a second metal oxide layer as well as a dielectric layer, wherein the first metal oxide layer is arranged between the second metal oxide layer and the dielectric layer. The first and second metal oxide layers are formed accordingly from a first and a second liquid phase. The present invention also relates to a semi-conductor laminate that can be obtained from such a method, and to electronic components comprising such a semi-conductor laminate.
    Type: Application
    Filed: September 12, 2012
    Publication date: February 26, 2015
    Applicant: Evonik Degussa GmbH
    Inventors: Juergen Steiger, Duy Vu Pham, Anita Neumann, Alexey Merkulov, Arne Hoppe
  • Publication number: 20150056750
    Abstract: A first insulating film in contact with an oxide semiconductor film and a second insulating film are stacked in this order over an electrode film of a transistor including the oxide semiconductor film, an etching mask is formed over the second insulating film, an opening portion exposing the electrode film is formed by etching a portion of the first insulating film and a portion of the second insulating film, the opening portion exposing the electrode film is exposed to argon plasma, the etching mask is removed, and a conductive film is formed in the opening portion exposing the electrode film. The first insulating film is an insulating film whose oxygen is partly released by heating. The second insulating film is less easily etched than the first insulating film and has a lower gas-permeability than the first insulating film.
    Type: Application
    Filed: October 29, 2014
    Publication date: February 26, 2015
    Inventors: Shinya SASAGAWA, Hiroshi FUJIKI, Yoshinori IEDA
  • Publication number: 20150056748
    Abstract: Resistive switching nonvolatile memory elements are provided. A metal-containing layer and an oxide layer for a memory element can be heated using rapid thermal annealing techniques. During heating, the oxide layer may decompose and react with the metal-containing layer. Oxygen from the decomposing oxide layer may form a metal oxide with metal from the metal-containing layer. The resulting metal oxide may exhibit resistive switching for the resistive switching memory elements.
    Type: Application
    Filed: October 2, 2014
    Publication date: February 26, 2015
    Inventors: Pragati Kumar, Sean Barstow, Tony P. Chiang, Sunil Shanker
  • Publication number: 20150053970
    Abstract: A display substrate includes a gate electrode on a base substrate, an active pattern which overlaps the gate electrode and includes a metal oxide semiconductor, an insulation pattern on the active pattern, a source electrode which contacts the active pattern, a drain electrode which contacts the active pattern and is spaced apart from the source electrode, and a first passivation layer which covers the active pattern and the insulation pattern, and includes fluorine, where the active pattern includes a first portion which directly contacts the insulation pattern and overlaps the gate electrode and the insulation pattern, a second portion which contacts the first passivation layer and has an electrical conductivity substantially larger than that of the first portion, a third portion which contacts the first passivation layer, has an electrical conductivity substantially larger than that of the first portion and is spaced apart from the second portion.
    Type: Application
    Filed: August 8, 2014
    Publication date: February 26, 2015
    Inventors: Je-Hun LEE, Sung-Hoon YANG, Hiroshi OKUMURA, Jin-Ho HWANG
  • Publication number: 20150056747
    Abstract: A method of forming a thin-film device includes forming an oxide-semiconductor film formed on the first electrical insulator, and forming a second electrical insulator formed on the oxide-semiconductor film, the oxide-semiconductor film defining an active layer. The oxide-semiconductor film is comprised of a first interface layer located at an interface with the first electrical insulator, a second interface layer located at an interface with the second electrical insulator, and a bulk layer other than the first and second interface layers. The method further includes oxidizing the oxide-semiconductor film to render a density of oxygen holes in at least one of the first and second interlayer layers is smaller than a density of oxygen holes in the bulk layer.
    Type: Application
    Filed: September 30, 2014
    Publication date: February 26, 2015
    Applicant: NLT TECHNOLOGIES LTD
    Inventors: Kazushige TAKECHI, Mitsuru NAKATA
  • Publication number: 20150053967
    Abstract: An Oxide TFT, a preparation method thereof, an array substrate and a display device are described. The method includes forming a gate electrode, a gate insulating layer, a channel layer, a barrier layer, as well as a source electrode and a drain electrode on a substrate; the channel layer is formed by depositing an amorphous oxide semiconductor film in a first mixed gas containing H2, Ar and O2. By depositing a channel layer in a first mixed gas containing H2, Ar and O2, the hysteresis phenomenon of the TFT can be mitigated effectively to improve the display quality of the display panel.
    Type: Application
    Filed: July 2, 2013
    Publication date: February 26, 2015
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Changjiang Yan, Tiansheng Li, Shaoying Xu, Zhenyu Xie, Xu Chen
  • Publication number: 20150056749
    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.
    Type: Application
    Filed: October 3, 2014
    Publication date: February 26, 2015
    Inventors: Yun Wang, Tony P. Chiang, Vidyut Gopal, Imran Hashim, Dipankar Pramanik
  • Publication number: 20150053976
    Abstract: With an increase in the definition of a display device, the number of pixels is increased, and thus the numbers of gate lines and signal lines are increased. The increase in the numbers of gate lines and signal lines makes it difficult to mount an IC chip having a driver circuit for driving the gate line and the signal line by bonding or the like, which causes an increase in manufacturing costs. A pixel portion and a driver circuit driving the pixel portion are provided over the same substrate. The pixel portion and at least a part of the driver circuit are formed using thin film transistors in each of which an oxide semiconductor is used. Both the pixel portion and the driver circuit are provided over the same substrate, whereby manufacturing costs are reduced.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 26, 2015
    Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Atsushi UMEZAKI
  • Patent number: 8962387
    Abstract: Some embodiments include methods of forming memory cells in which a metal oxide material is formed over a first electrode material, an oxygen-sink material is formed over and directly against the metal oxide material, and a second electrode material is formed over the oxygen-sink material. The second electrode material is of a different composition than the oxygen-sink material. The metal oxide material is treated to transfer oxygen from a region of the metal oxide material to the oxygen-sink material and thereby subdivide the metal oxide material into at least two regions, with one of the regions nearest the oxygen-sink material being relatively oxygen depleted relative to another of the regions.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Bhaskar Srinivasan
  • Patent number: 8962457
    Abstract: A transistor comprises an active layer of an oxide containing at least one element selected from In, Ga and Zn. The active layer is formed such that a desorption gas monitored as a water molecule by a temperature programmed desorption analysis is 1.4/nm3 or less.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: February 24, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tomohiro Watanabe
  • Patent number: 8963149
    Abstract: A thin film transistor including an oxide semiconductor with favorable electrical characteristics is provided. The thin film transistor includes a gate electrode provided over a substrate, a gate insulating film provided over the gate electrode, an oxide semiconductor film provided over the gate electrode and on the gate insulating film, a metal oxide film provided on the oxide semiconductor film, and a metal film provided on the metal oxide film. The oxide semiconductor film is in contact with the metal oxide film, and includes a region whose concentration of metal is higher than that of any other region in the oxide semiconductor film (a high metal concentration region). In the high metal concentration region, the metal contained in the oxide semiconductor film may be present as a crystal grain or a microcrystal.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Junichiro Sakata, Masayuki Sakakura, Masahiro Takahashi, Hideyuki Kishida, Shunpei Yamazaki
  • Patent number: 8962386
    Abstract: To reduce oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film and to improve electric characteristics of a transistor including the oxide semiconductor film. A semiconductor device includes a gate electrode whose Gibbs free energy for oxidation is higher than that of a gate insulating film. In a region where the gate electrode is in contact with the gate insulating film, oxygen moves from the gate electrode to the gate insulating film, which is caused because the gate electrode has higher Gibbs free energy for oxidation than the gate insulating film. The oxygen passes through the gate insulating film and is supplied to the oxide semiconductor film in contact with the gate insulating film, whereby oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Tetsuhiro Tanaka
  • Publication number: 20150048282
    Abstract: The present invention relates to a transparent compound semiconductor and to a production method therefor, and is adapted to provide a transparent compound semiconductor of high stability and charge mobility while being transparent. The transparent compound semiconductor according to the present invention has a composition of Ba1?XLaXSnO3 (0<x<0.1) and has a charge mobility of at least 10 cm2/V·sec.
    Type: Application
    Filed: April 5, 2013
    Publication date: February 19, 2015
    Inventors: Kookrin Char, Jisoon Ihm
  • Publication number: 20150048371
    Abstract: To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.
    Type: Application
    Filed: October 31, 2014
    Publication date: February 19, 2015
    Inventors: Hidekazu MIYAIRI, Kengo AKIMOTO, Yasuo NAKAMURA
  • Publication number: 20150047417
    Abstract: The present invention relates to a core-shell nanoparticle, a method of fabricating the same and a gas sensor using the same, more particularly to a core-shell nanoparticle which includes a core including a first metal oxide and a shell including a second metal oxide, the first metal oxide and the second metal oxide being oxides of the same metal having different oxidation states, a method of fabricating the same and a gas sensor using the same.
    Type: Application
    Filed: June 6, 2014
    Publication date: February 19, 2015
    Applicants: Electronics and Telecommunications Research Institute, Pusan National University Industry-University Cooperation Foundation
    Inventors: Hyung Ju PARK, Nak Jin CHOI, Moon Youn JUNG, Dae Sik LEE, Hyuntae KANG, Kang Hyun PARK
  • Publication number: 20150048360
    Abstract: A semiconductor device includes a substrate, a TFT supported by the substrate, an auxiliary capacitor, a source wiring line, and a gate wiring line. The auxiliary capacitor has a first auxiliary capacitor electrode, a second auxiliary capacitor electrode, and a first insulating layer. When viewed from the direction normal to the substrate, the gate wiring line and the source wiring line overlap to form a gate-source intersection region in which the first insulating layer and a second insulating layer are formed. The distance between the first auxiliary capacitor electrode and the second auxiliary capacitor electrode is smaller than the distance between the gate wiring line and the source wiring line in the gate-source intersection region.
    Type: Application
    Filed: March 11, 2013
    Publication date: February 19, 2015
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Publication number: 20150049276
    Abstract: A thin film transistor array panel includes: gate lines; data lines insulated from and crossing the gate lines; and shorting bars disposed outside of a display area in which the gate lines cross the data lines. The shorting bars overlap portions of the data lines disposed outside of the display area. The shorting bar includes a semiconductor material.
    Type: Application
    Filed: May 14, 2014
    Publication date: February 19, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventors: Tae-Young CHOI, Bo Sung KIM, Jae Woo PARK, Hee Jun BYEON, Young-Wook LEE, Moon-Keun CHOI
  • Publication number: 20150050774
    Abstract: An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.
    Type: Application
    Filed: August 28, 2014
    Publication date: February 19, 2015
    Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO
  • Publication number: 20150050776
    Abstract: A deposition technique for forming an oxynitride film is provided. A highly reliable semiconductor element is manufactured with the use of the oxynitride film. The oxynitride film is formed with the use of a sputtering target including an oxynitride containing indium, gallium, and zinc, which is obtained by sintering a mixture of at least one of indium nitride, gallium nitride, and zinc nitride as a raw material and at least one of indium oxide, gallium oxide, and zinc oxide in a nitrogen atmosphere. In this manner, the oxynitride film can contain nitrogen at a necessary concentration. The oxynitride film can be used for a gate, a source electrode, a drain electrode, or the like of a transistor.
    Type: Application
    Filed: November 3, 2014
    Publication date: February 19, 2015
    Inventor: Shunpei Yamazaki
  • Publication number: 20150050775
    Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability. In a manufacturing process of a bottom-gate transistor including an oxide semiconductor layer, heat treatment in an atmosphere containing oxygen and heat treatment in vacuum are sequentially performed for dehydration or dehydrogenation of the oxide semiconductor layer. In addition, irradiation with light having a short wavelength is performed concurrently with the heat treatment, whereby elimination of hydrogen, OH, or the like is promoted. A transistor including an oxide semiconductor layer on which dehydration or dehydrogenation treatment is performed through such heat treatment has improved stability, so that variation in electrical characteristics of the transistor due to light irradiation or a bias-temperature stress (BT) test is suppressed.
    Type: Application
    Filed: October 31, 2014
    Publication date: February 19, 2015
    Inventors: Shunpei YAMAZAKI, Ryosuke WATANABE, Suzunosuke HIRAISHI, Junichiro SAKATA
  • Publication number: 20150048299
    Abstract: Provided are a two-terminal switching device having a bidirectional switching property, and a resistive memory cross-point array including the same. The two-terminal switching device includes a first electrode. A first tunneling barrier layer is disposed on the first electrode. An oxide semiconductor layer is disposed on the first tunneling barrier layer. A second tunneling barrier layer is disposed on the oxide semiconductor layer. A second electrode is disposed on the second tunneling barrier layer.
    Type: Application
    Filed: March 28, 2014
    Publication date: February 19, 2015
    Applicant: POSTECH ACADEMY - INDUSTRY FOUNDATION
    Inventors: Hyunsang Hwang, Ji Yong Woo
  • Patent number: 8956913
    Abstract: A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8957416
    Abstract: Disclosed herein is a thin film transistor including: a channel layer made of a crystalline oxide semiconductor having a bixbyte structure, in which (222) planes of the channel layer are roughly parallel to the carrier travel direction.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 17, 2015
    Assignee: Sony Corporation
    Inventor: Mikihiro Yokozeki
  • Patent number: 8956911
    Abstract: The present invention relates to a LED (light-emitting diode) phosphor and fabricating method thereof, and particularly relates to a LED phosphor having a light-emitting thin film (or photoluminescence thin film) made of an organic material and a zinc oxide microstructure (or nanostructure) and a method for fabricating the LED phosphor by hydrothermal method and combination of the organic material and the zinc oxide microstructure (or nanostructure). In this invention, the light-emitting thin film (or photoluminescence thin film) made of the organic material and the zinc oxide microstructure (or nanostructure) is applied instead of rare earth elements to fabricate the LED phosphor. Therefore, the cost of the LED phosphor and the white LED can be reduced and the processes for fabricating the LED phosphor and the white LED can be simplified.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: February 17, 2015
    Assignee: National Taiwan University
    Inventors: Ching-Fuh Lin, Ming-Shiun Lin
  • Patent number: 8956912
    Abstract: To improve productivity of a transistor that includes an oxide semiconductor and has good electrical characteristics. In a top-gate transistor including a gate insulating film and a gate electrode over an oxide semiconductor film, a metal film is formed over the oxide semiconductor film, oxygen is added to the metal film to form a metal oxide film, and the metal oxide film is used as a gate insulating film. After an oxide insulating film is formed over the oxide semiconductor film, a metal film may be formed over the oxide insulating film. Oxygen is added to the metal film to form a metal oxide film and added also to the oxide semiconductor film or the oxide insulating film.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20150041751
    Abstract: In one example, a customizable nonlinear electrical device includes a first conductive layer, a second conductive layer, and a thin film metal-oxide layer sandwiched between the first conductive layer and the second conductive layer to form a first rectifying interface between the metal-oxide layer and the first conductive layer and a second rectifying interface between the metal-oxide layer and the second conductive layer. The metal-oxide layer includes an electrically conductive mixture of co-existing metal and metal oxides. A method forming a nonlinear electrical device is also provided.
    Type: Application
    Filed: April 26, 2012
    Publication date: February 12, 2015
    Inventors: Minxian Max Zhang, Jianhua Yang, Gilberto Medeiros Ribeiro, R. Stanley Williams
  • Publication number: 20150044816
    Abstract: Methods of manufacturing a resistance change layer and a resistive random access memory device are provided. The method of manufacturing a resistance change layer includes forming a preliminary resistance change layer including an oxide semiconductor material on a substrate and irradiating the preliminary resistance change layer with an electron beam to a predetermined depth. On a path along which the electron beam is irradiated, a composition ratio of the resistance change layer changes in a direction in which a density of oxygen vacancies of the oxide semiconductor material increases. Accordingly, the composition ratio of a resistance change layer is easily controlled using electron beam irradiation. In addition, since interfacial surface roughness and internal defect structures of an oxide semiconductor are controlled by electron beam irradiation, a resistance change ratio is improved and thereby device characteristics can be improved.
    Type: Application
    Filed: March 31, 2014
    Publication date: February 12, 2015
    Inventors: Eun Kyu KIM, Dong Uk LEE, Seong Guk CHO, Gyu Jin OH