Abstract: According to one embodiment, a semiconductor device includes a first conductive part, a semiconductor element, a first terminal, and a metal layer. The semiconductor element is located on the first conductive part. The first terminal is separated from the first conductive part in a second direction perpendicular to a first direction. The first direction is from the first conductive part toward the semiconductor element. The first terminal includes a first portion, and a second portion located between the first portion and the first conductive part. A lower surface of the second portion is positioned lower than a lower surface of the first portion and lower than a lower surface of a first insulating portion. The first insulating portion is located between the first conductive part and the second portion. The metal layer is located at the lower surfaces of the first portion and of the second portion.

Abstract: A method includes forming a leadframe assembly to have a pair of opposing sides, and having semiconductor die receiving portions extending between the opposing sides. The method also includes placing semiconductor dies on the leadframe assembly in the die receiving portions. Each die has a row of leads on each of two opposing sides of the die and a longitudinal axis parallel to the rows of leads. The longitudinal axis of each die is orthogonal to the opposing sides of the leadframe assembly. The method further includes applying mold compound to the semiconductor dies. The method includes punching through the leadframe assembly between the opposing sides using a first tool having a first tool longitudinal axis parallel to longitudinal axes of the dies.

Abstract: A metrology apparatus (302) includes a higher harmonic generation (HHG) radiation source for generating (310) EUV radiation. Operation of the HHG source is monitored using a wavefront sensor (420) which comprises an aperture array (424, 702) and an image sensor (426). A grating (706) disperses the radiation passing through each aperture so that the image detector captures positions and intensities of higher diffraction orders for different spectral components and different locations across the beam. In this way, the wavefront sensor can be arranged to measure a wavefront tilt for multiple harmonics at each location in said array. In one embodiment, the apertures are divided into two subsets (A) and (B), the gratings (706) of each subset having a different direction of dispersion. The spectrally resolved wavefront information (430) is used in feedback control (432) to stabilize operation of the HGG source, and/or to improve accuracy of metrology results.

Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.

Abstract: A system to effectuate improved transfer of semiconductor die. A first frame secures a first substrate having the semiconductor die. A second frame secures a second substrate adjacent the first substrate. A needle is disposed adjacent to the first frame. The needle includes: a longitudinal surface extending in a direction toward the second frame, and a base end having a cross-sectional dimension being based, at least in part, on a cross-sectional dimension of the semiconductor die. A needle actuator is operably connected to the needle and is configured to actuate the needle such that, during the transfer operation, when the first substrate is secured in the first frame and the second substrate is secured in the second frame, the needle presses the semiconductor die into contact with the second substrate so as to transfer the semiconductor die onto the second substrate.

Abstract: A 3D semiconductor device, the device including: a first die including first transistors and a first interconnect; a second die including second transistors and a second interconnect; and a third die including third transistors and a third interconnect, where the first die is overlaid by the second die, where the first die is overlaid by the third die, where the first die has a first die area and the second die has a second die area, where the first die area is at least 20% larger than the second die area, where the second die is pretested, where the second die is bonded to the first die, where the bonded includes metal to metal bonding, where the first die includes at least two first alignment marks positioned close to a first die edge of the first die, where the second die is aligned to the first die with less than 800 nm alignment error, where the second die includes at least two second alignment marks positioned close to a second die edge of the second die, and where the third die is bonded to the first d

Abstract: A computer-implemented system for dynamic inventory balancing including at a processor and a memory device comprising instructions that when executed configure the processor to perform operations. The operations including receiving an inventory data feed from at least one fulfillment center, storing (in a database) a plurality of virtual bundles with associated grouping numbers and quantities—the plurality of virtual bundles having item bundles grouping two or more of a same item in the inventory data. The operations also include exposing the database to queries from a seller portal through at least one of RESTful service, a queue based system, an index, or an object table and receiving a client order, the client order comprising a bundle selection from the plurality of virtual bundles, and updating the plurality of virtual bundles by rebalancing the plurality of virtual bundles and corresponding associated quantities based on the bundle selection.

Abstract: A method of making a printed circuit board structure including a closed cavity is provided. The method can include the steps of forming a cavity in a core structure of a core layer, laminating each of a top surface and a bottom surface of the core structure with an adhesive layer and a metal layer to prepare a laminate structure and cover the cavity to define a closed cavity. The method also includes forming vias through the laminate structure, and patterning the metal layers in the laminate structure.

Abstract: A package includes a first lead including a first electrode terminal, and a second lead including a second electrode terminal and provided on the first lead in an overlapping direction such that the first electrode terminal of the first lead overlaps with the second electrode terminal of the second lead when viewed in the overlapping direction. The first electrode terminal and the second electrode terminal are electrically connected to each other without adding additional material.

Abstract: A connection member for connecting an electronic chip, wherein the connection member comprises a bulk body, and a coating at least partially coating the bulk body and comprising a material having higher electric and higher thermal conductivity than the bulk body, wherein a ratio between a thickness of the coating and a thickness of the bulk body is at least 0.0016 at at least a part of the connection member.

Abstract: A system to effectuate improved transfer of semiconductor die. A first frame secures a first substrate having the semiconductor die. A second frame secures a second substrate adjacent the first substrate. A needle is disposed adjacent to the first frame. The needle includes: a longitudinal surface extending in a direction toward the second frame, and a base end having a cross-sectional dimension being based, at least in part, on a cross-sectional dimension of the semiconductor die. A needle actuator is operably connected to the needle and is configured to actuate the needle such that, during the transfer operation, when the first substrate is secured in the first frame and the second substrate is secured in the second frame, the needle presses the semiconductor die into contact with the second substrate so as to transfer the semiconductor die onto the second substrate.

Abstract: A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package sealing the semiconductor chip, the island, the lead, and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.

Abstract: The invention provides a flexible display and method for fabricating the same. The flexible display includes: a first flexible substrate and an oppositely disposed second flexible substrate; a TFT layer and an emitting unit, sequentially formed on the first flexible substrate; a color filter layer and an overcoat formed on the second flexible substrate; a fill formed between the first flexible substrate and the second flexible substrate; and a dam formed between the first flexible substrate and the second flexible substrate and surrounding the fill.

Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.

Abstract: A method for producing an RFID transponder. An RFID chip is attached onto a conductive sheet. A portion of an antenna element is cut from the conductive sheet using a laser beam after the RFID chip has been attached to the conductive sheet.

Abstract: Fabricating a packaged semiconductor device provides first planar leadframe with first leads and pads having attached electronic components. The first leadframe has a set of elongated leads bent at an angle away from the plane of the first leadframe. A second planar leadframe has second leads having attached electronic components. The bent leads of the first leadframe conductively connected to the second leadframe, forming a conductively linked 3-dimensional network between components and leads in two planes.

Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

Abstract: A method of fabricating a packaged semiconductor includes forming a conductive frame as an integral piece of conductive material. The frame includes an inner portion and a ring portion encircling the inner portion. The ring portion includes a first ring portion encircling first and second sides of the inner portion, and a first bar portion located on a third side of the inner portion. The method includes mounting a semiconductor die to a first surface of the inner portion of the frame. The die is configured to receive power via the first ring portion. The method includes applying a casing, which covers the die, to the frame. The method includes, after the casing is applied to the frame, removing (i) sections of the frame that connect the inner portion to the ring portion, and (ii) sections of the frame that connect the first ring portion to the first bar portion.

Abstract: Various aspects of the present invention, for example and without limitation, comprise a semiconductor device package and/or method for manufacturing a semiconductor device package. Such a device package may, for example, comprise a MEMS device package.

Abstract: A method and apparatus of minimizing resin bleed and mold flash on integrated lead finishes by providing groves on the external leads that can control the length of resin bleed.

Abstract: A method of manufacturing a semiconductor device includes mounting at least one of a first semiconductor chip and a second semiconductor chip over a die pad of a leadframe, and inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, wherein the leadframe includes first mark formed to the die pad, for indicating a first mounting region for the first semiconductor chip, and second mark formed to the die pad, for indicating a second mounting region for the second semiconductor chip, the first mark is different from the second mark, in at least either one of size and geometry, wherein, in the inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, a mounting position of the first semiconductor chip is inspected when the first semiconductor chip is mounted.

Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Abstract: Systems, methods, and other embodiments associated with an etched hybrid die package are described. According to one embodiment, a method includes electrically connecting a semiconductor die to at least one of a plurality of primary leads and at least one feature. The method includes applying an encapsulant material to a lead-frame that includes the plurality of primary leads to form a package body. Portions of the primary leads protrude from the package body and portions of the at least one feature are exposed within the package body. The method includes chemically etching a die pad exposed within the package body to form and electrically isolate the at least one feature from the die pad. Chemically etching includes fully etching the at least one feature from the die pad.

Abstract: A semiconductor device has a base substrate with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base substrate. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base substrate and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base substrate. A portion of the second surface of the base substrate is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.

Abstract: Consistent with an example embodiment, there is semiconductor device assembled to resist mechanical damage. The semiconductor device comprises an active circuit defined on a top surface, contact areas providing electrical connection to the active circuit. There is a pedestal structure upon which the active circuit is mounted on an opposite bottom surface; the pedestal structure has an area smaller than the area of the active device. An encapsulation, consisting of a molding compound, surrounds the sides and the underside of the active device and it surrounds the contact areas. The encapsulation provides a resilient surface protecting the active device from mechanical damage. A feature of the embodiment is that the contact areas may have solder bumps defined thereon.

Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a die attach paddle pad and a peripheral lead pad with an inner lead pad between the die attach paddle pad and the peripheral lead pad; forming a component side of the lead frame for exposing an upper portion of a peripheral lead under the peripheral lead pad; forming an encapsulation on the lead frame and the upper portion of the peripheral lead; exposing the peripheral lead pad; depositing a conductive shielding layer on the encapsulation connected to the peripheral lead pad; and forming a mounting side of the lead frame for forming a lower portion of the peripheral lead over a peripheral lead contact pad.

Abstract: The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Abstract: In a semiconductor device, a lead frame made of a copper alloy prevents exfoliation occurring near the surface of the lead frame. A copper oxide layer is formed on the base material made of a copper alloy by immersing the base material into a solution of a strong oxidizer. The copper oxide layer serves as an outermost layer and consists of a copper oxide other than a copper oxide in the form of needle crystals.

Abstract: A lead frame and a semiconductor package including the lead frame are provided. The lead frame includes: a base material; a first metal layer which is formed on at least one side of the base material, of which a surface is roughly formed, and which includes copper or nickel; a second metal layer which is formed on a surface of the first metal layer, of which a surface is roughly formed, and which includes palladium or a palladium alloy; a third metal layer which is formed on a surface of the second metal layer, of which a surface is roughly formed, and which includes gold or a gold alloy; and a fourth metal layer which is formed on a surface of the third metal layer, of which a surface is roughly formed, and which includes metal that includes silver.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle group having a first package paddle electrically isolated from a second package paddle; attaching an integrated circuit device on the first package paddle and the second package paddle; forming a standoff terminal adjacent the package paddle group and electrically connected to the integrated circuit device; connecting a paddle connector to the integrated circuit device and the first package paddle and another paddle connector to the integrated circuit device and the second package paddle; and forming an encapsulation over the integrated circuit device, the first package paddle, the second package paddle, and the standoff terminal, the encapsulation exposing a portion of the first package paddle, the second package paddle, and the standoff terminal.

Abstract: Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking. The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.

Abstract: The present invention specifies a leadframe for electronic components and a corresponding manufacturing process, in which the bonding islands are formed by welding individual, prefabricated segments of a bonding-capable material onto a stamped leadframe.

Abstract: Relating to electronic components, the present disclosure provides a method for welding a gold-silicon eutectic chip, and a transistor. The method for welding a gold-silicon eutectic chip includes: electroplating a gold layer with a thickness smaller than or equal to 1 micron on surfaces of a chip carrier; bonding multiple gold protrusions on the gold layer in a welding region; and rubbing a chip in the welding region at a eutectic temperature to form a welding layer. The transistor includes a chip, a chip carrier, and a middle layer connecting the chip and the chip carrier, where the welding middle layer is a welding layer obtained by using the above welding method. The present disclosure reduces an amount of gold in use and lowers a cost of gold-silicon eutectic welding to a relatively large extent, and, accordingly, cuts down the cost of a transistor.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming signal contacts; forming a power bar having a power bar terminal, the power bar terminal formed in a staggered position relative to the signal contacts; depositing a terminal pad on the power bar terminal; depositing a contact pad on one of the signal contacts; coupling an integrated circuit die to the power bar terminal and the signal contacts; and forming a package body on the integrated circuit die.

Abstract: A light-emitting diode includes a carrier with a mounting face and includes a metallic basic body and at least two light-emitting diode chips affixed to the carrier at least indirectly at the mounting face, wherein an outer face of the metallic basic body includes the mounting face, the at least two light-emitting diode chips connect in parallel with one another, the at least two light-emitting diode chips are embedded in a reflective coating, the reflective coating covering the mounting face and side faces of the light-emitting diode chips, and the light-emitting diode chips protrude with their radiation exit surfaces out of the reflective coating, and the radiation exit surfaces face away from the carrier.

Abstract: A leadframe (e.g., incorporated in a device package) includes a feature (e.g., a die pad or lead) with a vent hole formed between first and second opposed surfaces. The cross-sectional area of the vent hole varies substantially between the surfaces (e.g., the vent hole has a constricted portion). The vent hole may be formed from a first opening extending from the first surface toward the second surface to a first depth that is less than a thickness of the leadframe feature, and a second opening extending from the second surface toward the first surface to a second depth that is less than the thickness of the leadframe feature, but that is large enough for the second opening to intersect the first opening. Vertical central axes of the openings are horizontally offset from each other, and the constricted portion of the vent hole corresponds to the intersection of the openings.

Abstract: A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.

Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.

Abstract: A lead carrier provides support for an integrated circuit chip and associated leads during manufacture as packages containing such chips. The lead carrier includes a temporary support member with multiple package sites. Each package site includes a die attach pad surrounded by a plurality of terminal pads. The pads are formed of a sintered electrically conductive material. A chip is mounted upon the die attach pad and wire bonds extend from the chip to the terminal pads. The pads, chip and wire bonds are all encapsulated within a mold compound. The temporary support member can be peeled away and then the individual package sites can be isolated from each other to provide completed packages including multiple surface mount joints for mounting within an electronics system board. Edges of the pads are contoured to cause the pads to engage with the mold compound to securely hold the pads within the package.

Abstract: A method of assembling semiconductor devices includes placing an array of semiconductor dies on a die support. A cap array structure is provided that has a corresponding array of caps supported by a cap frame structure. The cap array structure and the array of semiconductor dies on the die support are aligned, with the caps extending over corresponding semiconductor dies, in a mold chase. The array of semiconductor dies and the array of caps are encapsulated with a molding compound in the mold chase. The encapsulated units of the semiconductor dies with the corresponding caps are removed from the mold chase and singulated. Singulating the encapsulated units may include removing the cap frame structure from the encapsulated units.

Abstract: A semiconductor package includes a single semiconductor die and an electrically and thermally conductive base. The single semiconductor die includes a semiconductor body having opposing first and second surfaces and insulated sides between the first and second surfaces. The single semiconductor die further includes a first electrode at the first surface and a second electrode at the second surface. The single semiconductor die has a defined thickness measured between the first and second surfaces, a defined width measured along one of the insulated sides, and a defined length measured along another one of the insulated sides. The base is attached to the second electrode at the second surface of the single semiconductor die and has the same length and width as the single semiconductor die.

Abstract: A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices.

Abstract: A stacked semiconductor device includes a unit component including a wiring portion formed by electrically connecting a die pad of and a lead of a lead frame, and a semiconductor package whose connection terminal is connected to the lead, wherein the unit component is stacked, and the leads located to upper and lower sides are connected mutually via an electrode.

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, forming a stiffening mold on a backside of the coreless substrate strip adjacent to sites where solder balls are to be attached, and attaching solder balls to the backside of the coreless substrate strip amongst the stiffening mold. Other embodiments are also disclosed and claimed.

Abstract: A leadless integrated circuit (IC) package comprising an IC chip mounted to a die-attach area and a plurality of electrical contacts electrically connected to the IC chip. The IC chip, the electrical contacts, and the die-attach area are all covered with a molding material, with portions of the electrical contacts and die-attach area protruding from a bottom surface of the molding material.

Abstract: The formation of a void is suppressed in the assembly of a semiconductor device. An MCU chip and an AFE chip are mounted over a die pad formed of a quadrangle having a pair of first sides and a pair of second sides. After wire bonding is carried out on the MCU chip and the AFE chip, resin is supplied from the side of one second side of the two second sides to the side of the other second side. The resin is thereby passed through the opening between a first pad group and a second pad group over the MCU chip to fill the area between the chips and thus the formation of a void is suppressed in the area between the chips.

Abstract: The electronic device package includes a package substrate including a frame portion and a cantilever portion surrounded by the frame portion, at least one semiconductor chip mounted on the cantilever portion, and a molding member disposed on the package substrate to cover the at least one semiconductor chip. The cantilever portion has a first edge connected to the frame portion and declines from the first edge toward a second edge located opposite to the first edge. Related methods are also provided.

Abstract: Described herein are microelectronic packages including a plurality of bonding fingers and multiple integrated circuit chips, at least one integrated circuit chip being mounted onto the bonding fingers. According to various embodiments of the present invention, mounting the integrated circuit chip onto the bonding fingers may reduce the pin-out count by allowing multiple integrated circuit chips to be interconnected within the same microelectronic package. Other embodiments may be described and claimed.

Abstract: A semiconductor device of an illustrative embodiment includes a die, a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die. Most preferably, the package includes at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the leads such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path, and an encapsulant which encapsulates the leads and the conductive element. The leads and, desirably, the conductive element have respective connection regions which are not covered by the encapsulant.