Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.

Abstract: An optoelectronic component including a connection carrier comprising a structured carrier strip in which interspaces are filled with an electrically insulating material and an optoelectronic semiconductor chip attached and electrically connected to a top portion of the connection carrier, wherein the electrically insulating material terminates substantially flush with the carrier strip in places or the carrier strip projects beyond the electrically insulating material, and the carrier strip is not covered by the electrically insulating material on the top portion and/or on a bottom portion of the connection carrier.

Abstract: Performing electrolysis plating to a wiring is made possible, aiming at the increasing of pin count of a semiconductor device. Package substrate 3 by which ring shape common wiring 3p for electric supply was formed in the inner area of bonding lead 3j in device region 3v of main surface 3a is used. Since a plurality of first plating lines 3r and fourth plating lines 3u for electric supply connected to common wiring 3p can be arranged by this, the feeder for electrolysis plating can be arranged to all the land parts on the back. Hereby, it becomes possible to perform electrolysis plating to the wiring of main surface 3a of package substrate 3, and the back surface. Even if the land part of plural lines is formed covering the perimeter of the back surface, electrolysis plating can be performed to the all land parts. As a result, electrolysis plating can be performed to a wiring, aiming at the increasing of pin count of a semiconductor device.

Abstract: In one embodiment, a method for forming a molded flat pack style package includes attaching electronic chips to an array lead frame, which includes a plurality of elongated flag portions with tab portions and a plurality of leads. The method further includes connecting the electronic chips to specific leads, and then molding the array lead frame while leaving portions of the leads exposed to form a molded array structure. The molded array structure is then separated to provide molded flat pack style packages having exposed leads for insertion mount and exposed tab portions. In an alternative embodiment, the separation step produces a no-lead configuration with exposed tab portions.

Abstract: Disclosed herein are a die package and a method of manufacturing the die package. A solder layer is formed on a lower surface of a die. The die is self-aligned and attached to a support plate using surface tension between the solder layer and a metal layer of the support plate, thus reducing attachment lead time of the die.

Abstract: A leadless semiconductor package with an electroplated layer embedded in an encapsulant and its manufacturing processes are disclosed. The package primarily includes a half-etched leadframe, a chip, an encapsulant, and an electroplated layer. The half-etched leadframe has a plurality of leads and a plurality of outer pads integrally connected to the leads. The encapsulant encapsulates the chip and the leads and has a plurality of cavities reaching to the outer pads to form an electroplated layer on the outer pads and embedded in the cavities. Accordingly, under the advantages of lower cost and higher thermal dissipation, the conventional substrates and their solder masks for BGA (Ball Grid Array) or LGA (Land Grid Array) packages can be replaced. The leads encapsulated in the encapsulant have a better bonding strength and the electroplated layer embedded in the encapsulant will not be damaged during shipping, handling, or storing the semiconductor packages.

Abstract: A method, system and program product for bonding two circuitry-including semiconductor substrates, and a related stage, are disclosed. In one embodiment, a method of bonding two circuitry-including substrates includes: providing a first stage for holding a first circuitry-including substrate and a second stage for holding a second circuitry-including substrate; identifying an alignment mark on each substrate; determining a location and a topography of each alignment mark using laser diffraction; creating an alignment model for each substrate based on the location and topography the alignment mark thereon; and bonding the first and second circuitry-including substrates together while aligning the first and second substrate based on the alignment model.

Abstract: Various methods are described where the semiconductor die and the lead frame (or the BGA or LGA substrate) are spaced apart to reduce stress. In one scenario, an air gap is formed between the semiconductor die and the lead frame by depositing a perimeter (made, for example, using polymer) either on the semiconductor die or the lead frame. In another scenario, an anisotropic conducting film (ACF) is formed with an air gap between the semiconductor die and the lead frame (or the BGA or LGA substrate). The air gap relieves stress on the semiconductor die. Further, a lead frame-based isolator package and a BGA (or LGA) isolator package are described. A window-frame ACF-based isolation method for magnetic coupling in a lead-frame package and BGA (or LGA) package is also described.

Abstract: The present invention provides an integrated circuit package system comprising: attaching a die platform to an integrated circuit die; mounting the integrated circuit die over an external interconnect with a bottom side of the external interconnect partially within the die platform; connecting the integrated circuit die and the external interconnect; and forming an encapsulation over the integrated circuit die with the external interconnect partially exposed.

Abstract: A semiconductor device and method is disclosed. In one embodiment, the method includes placing a first semiconductor over an electrically conductive carrier. The first semiconductor is covered with a molding compound. A through hole is formed in the molding compound. A first material is deposited in the through hole.

Abstract: In a method of cutting a wafer, a supporting member is attached to an upper surface of the wafer on which semiconductor chips are formed. An opening is formed at a lower surface of the wafer along a scribe lane of the wafer. The lower surface of the wafer may be plasma-etched to reduce a thickness of the wafer. A tensile tape may be attached to the lower surface of the wafer. Here, the tensile tape includes sequentially stacked tensile films having different tensile modules. The supporting member is then removed. The tensile tape is cooled to increase the tensile modules between the tensile films. The tensile tape is tensed until the tensile films are cut using the tensile modules difference to separate the tensile tape from the semiconductor chips. Thus, the lower surface of the wafer may be plasma-etched without using an etching mask.

Abstract: A semiconductor device has a chip, a first bump electrode, a conductive wire and a second bump electrode. The chip has at least one contact pad, and the first bump electrode is formed on the contact pad. The conductive wire is disposed on an active surface of the chip and electrically connected to the first bump electrode. The second bump electrode is formed on the conductive wire, and the second bump electrode is not disposed over any contact pad of the chip. In addition, a method for packaging a chip and an IC package are also disclosed.

Abstract: A leadless integrated circuit (IC) package comprising an IC chip mounted on a die attach pad and a plurality of electrical contacts electrically connected to the IC chip. The IC chip, the electrical contacts, and the die attach pad are all covered with a molding material, with portions of the electrical contacts and die attach pad protruding from a bottom surface of the molding material.

Abstract: An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads.

Abstract: A leadframe strip production process provides encapsulated semiconductor chips with more than two annular rows of exposed leads by utilizing two types of frames, a leadframe to which IC devices are mounted, and a ring frame strip that is attached to the leadframe with a non-conductive adhesive. The leadframe includes die pads that receive the IC chip devices, and each die pad is positioned within multiple rows of connecting pads for connection with bonding pads of the device to be encapsulated. The connecting pads of the leadframe are arranged in an annular fashion, with inner rows being closer to the die pad and outer rows being farther from the die pad.

Abstract: In at least one embodiment, a source driver of a film package type, includes: a film substrate; a semiconductor chip on a surface of the film substrate, the semiconductor chip having a plurality of terminals each of which is connectable to an external member, the plurality of terminals including input terminals, output terminals, and third terminals; an input terminal wiring region for receiving first wiring lines which are connected to the input terminals, respectively, the input terminal region being provided on the surface of the film substrate; an output terminal wiring region for receiving second wiring lines which are connected to the output terminals, respectively, the output terminal wiring region being provided on the surface of the film substrate; and sprocket portions at opposite ends of the film substrate, each of the sprocket portions having a copper foil on the surface, and a string of holes, the input terminal wiring region and the output terminal wiring region being provided so as to extend to

Abstract: The object of the present invention is to provide an adhesion film for semiconductor that is capable of bonding a semiconductor chip to a lead frame tightly at an adhesion temperature lower than that of the adhesion film of a traditional polyimide resin without generation of voids and that can also be used for protection of lead frame-exposed area, a thermoplastic resin composition for semiconductor for use in the adhesive agent layer therein, and a lead frame having the adhesive film and a semiconductor device; and, to achieve the object, the present invention provides a thermoplastic resin composition for semiconductor, comprising a thermoplastic resin obtained in reaction of an amine component containing an aromatic diamine mixture (A) containing 1,3-bis(3-aminophenoxy)benzene, 3-(3?-(3?-aminophenoxy)phenyl)amino-1-(3?-(3?-aminophenoxy)phenoxy)benzene and 3,3?-bis(3?-aminophenoxy)diphenylether, and an acid component (C), an adhesion film for semiconductor using the same, a lead frame having the adhesion fi

Abstract: There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions. In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is different from an arrangement order of the function terminals on the external package.

Abstract: An integrated circuit package system includes: providing a finger lead having a side with an outward exposed area and an inward exposed area separated by a lead cavity; positioning a chip adjacent the finger lead and connected to the finger lead; and a stack encapsulant encapsulating the chip and the finger lead with the outward exposed area and the inward exposed area of the finger lead substantially exposed.

Abstract: Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink. The nanoink is then cured to remove liquid content. The residual metallic leadframe or electrical interconnect pattern has a substantially consistent thickness of about 10 to 50 microns or less. An associated panel assembly includes a conductive substrate panel having multiple separate device arrays comprising numerous electrical interconnect patterns each, a plurality of integrated circuit devices mounted on the conductive substrate panel, and a molded cap that encapsulates the integrated circuit devices and associated electrical interconnect patterns.

Abstract: A method for making micro-electromechanical system devices includes: (a) forming a sacrificial layer on a device wafer; (b) forming a plurality of loop-shaped through-holes in the sacrificial layer so as to form the sacrificial layer into a plurality of enclosed portions; (c) forming a plurality of cover caps on the sacrificial layer such that the cover caps respectively enclose the enclosed portions of the sacrificial layer; (d) forming a device through-hole in each of active units of the device wafer so as to form an active part suspended in each of the active units; and (e) removing the enclosed portions of the sacrificial layer through the device through-holes in the active units of the device wafer.

Abstract: A multichip integrated circuit apparatus includes first and second integrated circuit die mounted on opposite sides of a leadframe die paddle, with at least one of the integrated circuit die extending further toward the leads than does the die paddle. With this arrangement, the active circuit areas of both integrated circuit die can face in the same direction, and can be wire bonded to the same surfaces of the leads. This avoids wire bonding complications that are often encountered in multichip integrated circuit package designs.

Abstract: The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The thermal clip and source pad can be either top or bottom-exposed. The gate, source and drain leads are exposed through the molding material, and all leads are coplanar with the bottom-exposed surface. The device can have multiple semiconductor dies or various sized dies while still having a single, constant footprint. The method of manufacturing requires attaching the semiconductor die to a thermal clip, and then attaching the die with the attached thermal clip to a lead frame. The resulting device is then molded, marked, trimmed and singulated, in this order, creating a packaged semiconductor device with dual exposed surfaces.

Abstract: Disclosed is a semiconductor device manufacturing method including: preparing a semiconductor wafer which includes a semiconductor device forming region surrounded by dicing streets extending along first and second directions and including columnar electrodes and a sealing film; with respect to the columnar electrodes nearest the dicing streets in the first direction or the columnar electrodes nearest the dicing streets in the second direction, solder paste layers are displaced to an inward side of the semiconductor device forming region; by performing reflow, allowing the solder paste layer contacting with the columnar electrodes nearest the pair of dicing streets extending in the first direction or the solder paste layer contacting with the columnar electrodes nearest the pair of dicing streets extending in the second direction to move so as to form solder bumps.

Abstract: A flip chip type LED lighting device manufacturing method includes the step of providing a strip, the step of providing a submount, the step of forming a metal bonding layer on the strip or submount, the step of bonding the submount to the strip, and the step of cutting the structure thus obtained into individual flip chip type LED lighting devices.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.

Abstract: An integrated circuit package has a substrate; a discrete capacitor coupled to a first surface of the substrate; an integrated circuit die coupled to the first surface of the substrate over the discrete capacitor; and a lid coupled to the substrate, the lid encapsulating the integrated circuit die and the discrete capacitor.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a stack board with a side having a connect contact next to a connect edge and a top contact next to a top edge perpendicular to the connect edge, and a bottom contact on an opposite side; mounting a circuit assembly having an assembly end next to the connect contact and an edge pad over the stack board; connecting the edge pad with the stack board; and applying an edge encapsulant over the connect contact and over the assembly end with the edge encapsulant extending no more than half the width of the stack board.

Abstract: A wired circuit board holding sheet that can permit easy judgment on whether a cutting notch formed has a predetermined depth, and a production method of the wired circuit board holding sheet that can produce the wired circuit board holding sheet simply and easily. In the wired circuit board holding sheet 1 comprising a sheet 2 holding therein a plurality of separable wired circuit boards 3, the respective wired circuit boards 3 are held in the sheet 2 via joints 4 to be cut, and cutting notches 6 to facilitate cutting of the joints 4 and marking notches 7 to indicate that the cutting notches 6 have a predetermined depth to cut the joints 4 are formed simultaneously in both front and back surfaces of the joints 4 by using punches having combination of a main punch portion 13 and a sub-punch portion 14.

Abstract: An LED can include a pair of electrode members, and an LED chip joined to a chip mount portion disposed at the extremity of one of the pair of electrode members. The LED chip can be electrically connected to the pair of electrode members. A transparent resin portion can include a wavelength conversion material mixed therein, the transparent resin portion formed in such a manner as to surround the LED chip, wherein the LED chip is positioned offset toward one side in the transparent resin portion, and wherein the wavelength conversion material mixed in the transparent resin portion has a higher density around the LED chip within the transparent resin portion.

Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.

Abstract: The invention discloses integrated circuits (ICs), molded IC packages, and to leadframe arrays, package arrays and methods for their manufacture. Leadframe arrays and package arrays used for the manufacture of IC packages by transfer molding processes include a locking feature adapted for encapsulation. The locking feature is situated in a strap of the leadframe array overlying a gate between mold cavities. The strap lock formed by curing encapsulant in the locking feature of the strap strengthens the resulting package array and provides improved mold extraction and handling characteristics.

Abstract: An inductor, a semiconductor component including the inductor, and a method of manufacture. A leadframe has a plurality of conductive strips and a flag. A ferrite core is mounted on a die attach material disposed on the conductive strips and a semiconductor die is mounted on a die attach material disposed on the flag. Wire bonds are formed from the conductive strips on one side of the ferrite core to corresponding conductive strips on an opposing side of the ferrite core. The wire bonds and the conductive strips cooperate to form the coil of the inductor. Wire bonds electrically couple one end of the inductor to leadframe leads adjacent the semiconductor die. Wire bonds couple bond pads on the semiconductor die to the leadframe leads coupled to the inductor. An encapsulant is formed around the inductor and the semiconductor die. Alternatively, a stand-alone inductor is manufactured.

Abstract: A method to assemble a non-leaded semiconductor package is disclosed. In one embodiment, a carrier tape is attached to a metal foil. A plurality of leadframes are formed in the metal foil, each leadframe including a die pad laterally surrounded by a plurality of contact leads. A semiconductor die, including an active surface with a plurality of die contact pads, is attached to each die attach pad and electrically connected to the leadframe by a plurality of bond wires connecting the die contact pads and the lead contact areas of the contact leads. A plurality of leadframes, each including a wire bonded semiconductor die, are encapsulated with mold material. The carrier tape is removed and the non-leaded semiconductor packages separated.

Abstract: An integrated circuit package-on-package stacking method includes forming a leadframe interposer including: forming a leadframe having a lead; forming a molded base only supporting the lead; and singulating the leadframe interposer from the leadframe.

Abstract: A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed.

Abstract: A method and apparatus for bonding integrated circuits uniquely suited to high volume tag production is described, where conductive material of a substrate at the die-attach-area is cut before an IC chip or transponder is placed on the conductive material over the cut and bonded. The apparatus performs the method of placing a first chip on a substrate having a conductive layer, measuring the location of the first chip on the substrate, cutting the conductive layer at a location of an expected subsequently placed chip to form a cut based on the measured location of the first chip, and placing the subsequently placed chip on the substrate over the cut.

Abstract: A method for manufacturing an electronic part, including: cutting a wiring substrate, which contains a base substrate, a wiring pattern provided on a first surface of the base substrate, and a reinforcing member provided on a second surface of the base substrate, along a line intersecting with an outer circumference of the reinforcing member; wherein a wire, out of a plurality of wires composing the wiring pattern, arranged closest to an intersecting point of the outer circumference of the reinforcing member and the line has a widest width.

Abstract: A semiconductor chip has at least one first contact and one second contact on its top side and has connecting elements which are arranged jointly on a structure element and which connect the first contact and the second contact of the top side of the semiconductor chip to the external contacts.

Abstract: Embodiments in accordance with the present invention relate to techniques which avoid the problems of deformation in the shape of a solder connection in a flip chip package, resulting from solder reflow. In one embodiment, a solder-repellent surface is created adjacent to the solder to constrain the reflow and thereby maintain the vertical profile of the solder. Examples of such a solder-repellent surface include an oxide (such as Brown Oxide) of the lead frame, or a tape (such as Kapton) which is used as a dam bar to control/constrain the solder flow on the leads prior to the encapsulation step. In another embodiment, the solder connection may be formed from at least two components. The first component may reflow at high temperatures to provide the necessary adhesion between solder ball and the die, with the second component reflowing at a lower temperature to provide the necessary adhesion between the solder ball and the leads.

Abstract: A solid-state imaging device comprises a housing in which a base and ribs forming a rectangular frame are formed in one piece by a resin; a plurality of metal lead pieces embedded in the housing, each of which has an internal terminal portion facing an internal space of the housing and an external terminal portion exposed at an outer portion of the housing; an imaging element arranged on the base in the internal space of the housing; connecting members connecting electrodes of the imaging element to the internal terminal portions of the metal lead pieces; and a transparent plate fastened to an upper face of the ribs. The upper face of the ribs is provided with a lower step portion that is lowered along an external periphery, and the transparent plate is fastened to the upper face of the ribs by an adhesive filled at least into the lower step portion.

Abstract: Methods, systems, and apparatuses for integrated circuit packages, such as ball grid array packages, and processes for assembling the same, are provided. A first strip includes an array of package substrate sections. An IC die is mounted to each package substrate section of the first strip. A second strip includes an array of leadframe sections. The second strip is positioned adjacent to the first strip to couple a planar protruding area of each leadframe section to a corresponding IC die mounted to the first strip. An encapsulating material is applied to the adjacently positioned first and second strips to fill a space between the first and second strips and to fill a cavity in a top surface of each leadframe section. A planar region of the first strip surrounding each centrally located cavity is not covered by the encapsulating material. The adjacently positioned first and second strips are singulated into a plurality of IC packages.

Abstract: A tape carrier includes: a base film with insulating property; a wiring pattern provided on the base film within a product region, the product region being demarcated by a cutting line so as to divide the tape carrier into individual products by cutting along the tape carrier along the cut line; and a solder resist provided on the base film so as to cover the wiring pattern. The solder resist protrudes outward from within the product region.

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes.

Abstract: A semiconductor device has an adhesive layer depositing over a temporary carrier. A plurality of fiduciary patterns is formed over the adhesive layer. A repassivation layer is formed over semiconductor die. The repassivation layer may be a plurality of discrete regions. Alignment slots are formed in the repassivation layer. The fiducial patterns and alignment slots have slanted sidewalls. Leading with the repassivation layer, the semiconductor die is placed onto the carrier so that the alignment slots envelope and lock to the fiducial patterns. Alternatively, a die without the repassivation layer is placed between the fiducial patterns. An encapsulant is deposited over the semiconductor die while the die remain locked to the fiducial patterns. The carrier, adhesive layer, and fiducial patterns are removed after depositing the encapsulant. An interconnect structure is formed over the repassivation layer to electrically connect to contact pads on the semiconductor die.

Abstract: Disclosed are a method for manufacturing a laminated lead frame and a laminated lead frame manufactured thereby, wherein lead frame single plates to be laminated one on top of the other can be reliably bonded together with a relatively light load. Under the method for manufacturing a laminated lead frame by means of stacking and bonding lead frame single plates 10 and 11, each of which has been processed into a predetermined shape, a plurality of protuberance sections 12 are formed in at least one of mutually-opposing surfaces of the lead frame single plates 10 and 11 that vertically pair up with each other. The mutually-opposing lead frame single plates 11, 12 are bonded together via the protuberance sections 12.

Abstract: A method of manufacturing photo couplers is provided. At first, a receiver lead-frame array is cut from a lead-frame matrix having a transmitter lead-frame array and the receiver lead-frame array. Then, the receiver lead-frame array is overturned and placed on the lead-frame matrix to allow light-receiver elements on the receiver lead-frame array to face light-emitting elements on the transmitter lead-frame array of the lead-frame matrix. Finally, the receiver lead-frame array and the lead-frame matrix are connected.

Abstract: A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.

Abstract: Performing electrolysis plating to a wiring is made possible, aiming at the increasing of pin count of a semiconductor device. Package substrate 3 by which ring shape common wiring 3p for electric supply was formed in the inner area of bonding lead 3j in device region 3v of main surface 3a is used. Since a plurality of first plating lines 3r and fourth plating lines 3u for electric supply connected to common wiring 3p can be arranged by this, the feeder for electrolysis plating can be arranged to all the land parts on the back. Hereby, it becomes possible to perform electrolysis plating to the wiring of main surface 3a of package substrate 3, and the back surface. Even if the land part of plural lines is formed covering the perimeter of the back surface, electrolysis plating can be performed to the all land parts. As a result, electrolysis plating can be performed to a wiring, aiming at the increasing of pin count of a semiconductor device.

Abstract: A system for manufacturing an integrated circuit package system is provided. A dual-type leadframe having first and second rows of leads is formed. A first row of bumps is formed on an integrated circuit chip. Solder paste is placed on the first row of leads, and the first row of bumps is pressed into the solder paste on the first row of leads. The solder paste is reflow soldered to form solder and connect the integrated circuit chip to the first row of leads, and the integrated circuit chip, the first row of bumps, the solder, and the leadframe are encapsulated.